WO1999022287A2

WO1999022287A2 - Data retrieval channel detection and compensation

Info

Publication number: WO1999022287A2
Application number: PCT/US1998/022715
Authority: WO
Inventors: Lisa Fredrickson; Daniel Richard Vigil; Dennis C. Stone; Leroy A. Volz
Original assignee: Seagate Technology LLC
Current assignee: Seagate Technology LLC
Priority date: 1997-10-27
Filing date: 1998-10-27
Publication date: 1999-05-06
Anticipated expiration: 2000-04-27

Abstract

A digital peak detector for detecting those peak member values of either polarity in a digitized values sequence having magnitudes greater than, or in some instances equal to, each of those in a selected number of neighboring member values which can selectively be required to be of the same polarity as the corresponding peak value, subject to exceeding both a selected absolute threshold and a selected multiple of a subsequent sequence member value. A peak value and polarity notifier provides a selected one of two alternative indicator pairs of signals of selectable time durations to indicate the occurrences of peak value members and the polarity thereof. The magnitudes of future member values in the digitized values sequence obtained from an analog signal are adjusted by varying the magnitude of that signal based on a magnitude average of selectively weighted differences between a number of past peak member values and a desired value. These differences available for use in this averaging are subject to being excluded if associated with known system operation problems but other member values are subject to being included if too much time has elapsed since the previous difference value based adjustment. Magnitude asymmetries between peak member values of different polarities in the digitized values sequence are compensated by adding and subtracting therefrom based on a magnitude average of these differences after those associated with member values in the digitized values sequence of one polarity are negated and all in the average are selectively weighted. Value based on these magnitude averages are stored for selective use as initial average values for the corresponding next such averaging. Magnitudes over time of the digitized values sequence related to paired zones along tracks in the magnetic medium disk in a magnetic data storage and retrieval system are accumulated and subtracted from one another for each pair. The accumulated difference results for each pair are used as an error signal for estimating the lateral position error with respect to the track of the 'read head' in retrieving information from the stored magnetic data on the disk.

Description

DATA RETRIEVAL CHANNEL DETECTION AND COMPENSATION BACKGROUND OF THE INVENTION The present invention relates to information storage systems and, more particularly, to control of characteristics of the data retrieval channel through which data is retrieved from storage in such systems.

Digital data magnetic recording systems store digital data by recording same in a moving magnetic media layer using a storage, or "write", electrical current-to-magnetic field transducer, or "head", positioned immediately adjacent thereto. The data is stored or written to the magnetic media by switching the direction of flow in an otherwise substantially constant magnitude write current that is established in coil windings in the write transducer in accordance with the data. Each write current direction transition results in a reversal of the magnetization direction, in that portion of the magnetic media just then passing by the transducer during this directional switching of the current flow, with respect to the magnetization direction in that media induced by the previous in the opposite direction. In one recording scheme, often termed nonreturn-to-zero inverted (NRZI), each magnetization direction reversal occurring over a short portion of the magnetic media moving past the transducer represents a binary number system digit "1", and the lack of any such reversals in that portion represents a binary digit "0". Recovery of such recorded digital data is accomplished through positioning a retrieval, or "read" magnetic field-to-voltage transducer, (which may be the same as the storage transducer if both of these transducers rely on inductive coupling between the media fields and the transducer) or "head", is positioned to have the magnetic media, containing previously stored data, pass thereby. Such passing by of the media adjacent to the transducer permits the flux accompanying the magnetization reversal regions between local oppositely magnetized successive portions in that media either to induce a corresponding voltage pulse in forming an analog output read signal for that retrieval transducer or, alternatively, change a transducer circuit parameter to thereby provide such an output signal voltage pulse. In the coding scheme described above, each such voltage pulse in the read transducer output signal due to the reversal of magnetization directions between adjacent media portions is taken to represent a binary digit " 1 ", and the absence of such a pulse in corresponding media portions is taken to represent a binary digit "0".

Digital data magnetic recording systems have used peak detection methods for the detection of such voltage pulses in the retrieved analog signal as the basis for digitizing this signal. Such methods are based on determining which peaks in that signal exceed a selected threshold to determine that a binary digit "1 " related pulse occurred in the retrieved signal, and also use the times between those voltage pulses to reconstruct the timing information used in the preceding recording operation in which the data were stored in the magnetic media as described above. The analog retrieved signal is provided to a phase-locked loop forming a controlled oscillator, or a phase-lock oscillator or synchronizer, which produces an output timing signal, or "clock" signal, from the positions of the detected peaks in this analog retrieved signal. Absolute time is not used in operating the data retrieval system portion since the speed of the magnetic media varies over time during both the storage operation and the retrieval operation to result in nonuniform time intervals, or nonuniform multiples thereof, occurring between the voltage pulses in the analog retrieved signal. There is always a desire in magnetic recording systems to devote less of the magnetic media along a track therein to the storage of a bit to thereby permit increasing the density of the bits stored. The use of peak detection places a limit on the density of bits along a track because increasing that density beyond some point will lead to too much intersymbol interference which in turn leads to errors in the recovery of data using such peak detection methods. Because of this limit, recent increases in bit density along a track in a magnetic media have come with the acceptance of a controlled, or known, amount of intersymbol interference which, since known, allows detection of the pulses involved despite this interference. The read transducer analog output signal generated from the binary bits or symbols stored in the magnetic media is sampled with the resulting positive and negative value samples of the positive and negative pulses in this signal being converted to digital data, and the samples are taken at a rate which leads to more than one sample per pulse rather than the single sample per pulse which would be sufficient for peak detection if sampling was used therewith. Since each individual sample reflects only part of the pulse response, this process used in a system results in referring to such a system as a partial response system.

A digital data magnetic recording system comprises a bandpass data retrieval channel in that it is unable to transmit very low frequencies, and has an upper frequency beyond which its transmission is also quite poor. Although there are a number of possible alternative partial response system arrangements, there is substantial value in matching the partial response spectrum to that expected for the data to be transmitted in the channel. A read transducer analog output signal, x(t), provided through any kind of a data retrieval channel is subject to containing errors therein as a result due to noise, timing errors, gain errors, signal offset, channel nonlinearities such as asymmetry, and the like encountered in the course of retrieval. One such nonlinear distortion in a read channel is asymmetry in the channel response to the binary input values of "0" and "1". One typical source of such asymmetry in a read channel occurs with the use of a magnetoresistive transducer in the read head which often provides a different magnitude output when reading a magnetization transition from the magnetic media in going from a first state to an opposite state than when making a transition from an alternative second state to an opposite state. Feedback control systems are typically used to control the characteristics of data retrieval channels through estimating the errors with respect to desired values in the channel gain, signal offset and sampling timing phase errors and attempting to drive such errors to zero. Such systems used without compensation for channel asymmetry either suffer an undesirable introduction of bias in the estimates or an increase the variance of those estimates over what they would be in the absence of such asymmetry. In general, errors in signal magnitudes are corrected in such feedback systems based on the differences between the peak values occurring for the pulses in the read transducer analog output signal and desired values for such peaks. Hence, a digital peak detector subsystem is used in connection with these feedback channel characteristic error correction systems.

However, there are in actuality two kinds of signals of differing characteristics for which magnitude errors must be corrected, these being user stored data signals and "servo" signals generally including "read head" track positioning servomechanism data signals along with both track identification data signals and track gain selection determination signals. This situation arises because data in magnetic medium disk based magnetic data storage systems is stored as one of the two opposite magnetization directions in the local data regions provided along each of a large number of more or less circular tracks that are more or less concentric with the rotational center of the magnetic medium disk. Such tracks must be each be located by the "read head" to reach the desired user data stored therealong, and then that track must be followed by that head as the track passes thereby on the moving disk to obtain this data. The positioning servomechanism is enabled to perform in this manner by dividing the various track sectors into lead track sector portions, or "servo fields," containing positioning servomechanism stored data followed by succeeding track sector portions containing user stored data, and embedding track positioning, gain and identification information into these servo fields. The servo fields at the beginning of track sectors are formed as four quarter-width tracks which together side-by-side have widths which total the width of a single track. Such quarter-width tracks are formed by a servo field storage or "writing" system in which a "writing head" provides a full track width wide series of magnetization direction changes or transitions along servo field portions of track sectors with each such transition separated by a multiple of 100 ns as an initial servo field track storage operation. This head is then repositioned at the beginning pf the servo field but positioned laterally one quarter track width, and then again provides a full track width wide series of similar transitions along this servo field portion so as to leave a quarter-width track from the initial storage operation substantially undisturbed to thereby provide the first quarter- width track. This kind of operation is repeated until four quarter-width tracks are provided in the lead portion of the track sector for which the servo field is being provided. During subsequent data retrieval operations in the magnetic data storage system, the "read head" is approximately positioned by the system controller adjacent to that particular one of the magnetic medium disk track sectors having the desired user data therein. As a result, the corresponding servo field in the lead portion of that track on the rotating magnetic medium disk will typically pass by the magnetoresistive "read head" which will sense the magnetic contributions of the locally magnetized regions passing thereby from 60 to 90% of the full width of that track. As a result, that head will sense a composite of the magnetic fields due to the transitions occurring in any or all of from three to four of the quarter- width tracks at any particular position along the servo field. The resulting electrical signal due to the sensing of this composite is provided from the head to the retrieval channel by first passing it through a low-pass filter having a bandwidth of approximately 10 MHZ. The resulting filtered signal is presented to a pulse detector used for detecting those pulses in the filtered signal due to the magnetic transitions in the servo field, and subsequently in the following user data field portion of the track sector.

Such servo fields at the beginning of track sectors, each with four such quarter-width tracks therein, are divided along the length of the tracks into four portions: a preamble portion, an identification portion, a lateral positioning portion, and a synchronization portion. Preceding each track sector, and therefore preceding each servo field, is a track gap portion in which there are no magnetic transitions, which gap portion, at the rotation rate of the magnetic medium disk, lasts for approximately 1 μs. The preamble portion of the servo field at the beginning of a track sector is first encountered by the "read head", and has transitions stored along each quarter-width track that alternate in polarity and are separated by 100 ns at the disk rotation rate. Since the four quarter-width tracks, although having such magnetic transitions stored therein over a time interval different from each of the time intervals for such storage in the other quarter- width tracks, have corresponding transitions in each provided at approximately the same distance along that quarter- width track so that the magnetoresistive head encounters the magnetic fields due to corresponding transition in each track at approximately the same time, this being true since the transitions for each quarter-width track were placed there under the control of a crystal reference clock so as to be quite accurately positioned along that quarter-width track. Since preamble quarter-width track transitions are separated by 100 ns, the resulting waveform through the preamble of alternating polarity pulses separated by 100 ns supplied by the head to the filter has a fundamental frequency equal to 10 MHZ which is the maximum unattenuated servo loop frequency permitted by that filter.

However, the pulse waveform from the head provided to the filter, based on the accumulated magnetic responses of each quarter-width track, will not be based on perfectly matched magnetic transitions from each quarter-width track because, even with crystal reference clock control, there will be some transition positioning incoherence among the quarter- width tracks. The result will cause some pulse broadening at preamble transitions as a result of the slightly mismatched corresponding transitions occurring along the quarter-width tracks. In addition, there can be other shortcomings in the pulse waveform due to corresponding transitions as a result of shifts in the zero amplitude base line, of effects of saturation in the magnetoresistive "read head" at lower frequencies, and of significant asymmetry in opposite polarity pulse magnitudes because of an asymmetric response of by the magnetoresistive head. Despite these defects, the preamble waveform emerges from the filter at its output as more or less a sine wave of a 10 MHZ frequency for presentation to the pulse detector for detection of the peaks therein.

The preamble based sine wave provided at the output of the filter to the pulse detector is of sufficient duration so that at least 12 peaks in that signal can be detected as the basis for setting the retrieval channel gain for the rest of the magnetic transitions to be encountered over the course of passing the servo field by the magnetoresistive head. In doing so, the pulse detector and the circuitry associated therewith must determine whether a magnitude value in the sine wave presented thereto represents the occurrence of an actual peak in that wave, which will be indicated by providing a binary value of 1, or represents the absence of a peak which will be represented by providing a binary value of 0. In addition, the polarity of each peak, whether positive or negative, must be determined.

The next portion of the servo field to reach the magnetoresistive head is the identification portion. In that portion, the track number and the sector number are detected which have been previously recorded in the magnetic transitions provided therein in the form of a Gray code during the quarter- width track storage operations.

Next, the lateral positioning portion of the servo field reaches the magnetoresistive head. In this portion, a succession of zones of widths slightly less than the track width are provided along the track in magnetic medium disk 10 with the zones extending along the track for a selected length. These zones in succession along the track are provided in at least a four zone pattern of various lateral positions with respect to that track, and possibly a six zone lateral position pattern, the zones in a four zone lateral position pattern being designated A, B, C and D in succession. In a four zone pattern, zones A and B are typically adjacent to, but on opposite sides, of the center of a full width track, zone C is centered on and straddles the track center, and zone D is offset a half track width (or two quarter width tracks) from the track center. Adding two more zones E and F to the succession of zones typically results in a lateral pattern of zones three quarter track widths wide with zone A adjacent to a full width track edge and positioned over three quarter width tracks in that track, and with zone B straddling the opposite track edge and positioned over a single quarter width track in the full width track. Zones C and D straddle opposite edges of that full width track each positioned over two quarter track widths in that full width track. Zone E is positioned as is zone B but at the opposite edge of this full width track, and zone F is positioned as is zone A but again at the opposite edge of this full width track.

Each zone contains a succession of magnetic transitions providing the basis for a corresponding plurality of series of alternating polarity pulses in the read channel signal. The magnitude-time areas of these pulses in each zone in succession are determined based on full wave rectification of the corresponding read channel signal portions with the differences in areas for corresponding zones being stored for subsequent use by the system controller. The difference in signal areas from zones A and B compared to the difference in signal areas from zones C and D represent an indication as to the lateral position of the "read head" along the servo field track portion which is used as an error signal for operating the lateral positioner servo mechanism for the "read head".

Finally, the synchronization portion of the servo field is reached in which a servo field synchronization indicator is provided, this being the binary value sequence 1011 previously recorded during the quarter- width track storage operations. Thereafter, the user data portion of the track sector begins in which is contained the sought after user data. Such data is also represented by magnetic transitions, and the resulting peaks therefrom must also be detected and analyzed by the peak detector and associated circuitry.

Clearly, the peak detector subsystem and associated circuitry are an important part of the data retrieval channel in a magnetic data storage system, and in the supplementary servo field operations preparatory to the retrieval of such user data. One conventional analog peak detection method is to differentiate the signal to provide zero values for each of the local minimums and local maximums, and then detect zero crossings of the signal derivative to locate these peaks. The amplitude of the signal where the derivative is zero is then compared to a threshold level to identify peak sample values. Such sample values are compared with adjacent sample values to determine whether a relative peak has occurred.

A conventional digital peak detection method is to convert the analog samples to digital samples, and then compare any particular sample to the previous sample and subsequent sample. If the sample of interest is greater in magnitude than the previous and subsequent samples, then that sample is compared with a threshold level. If the magnitude of the sample of interest exceeds the threshold, then the sample is identified as a peak. As a result, similar to the conventional analog peak detection system, such digital methods have apeak comparison window that is three samples wide. One problem with such detection methods is that noise spikes can cause two or more peaks to be reported within a comparison window in which there is only one recorded peak. Such false peaks reduce operating efficiency where they are detected and trigger a second reading of the data. When such errors go undetected, they can cause system failures.

Peak detectors are typically preceded by a variable gain amplifier ("VGA") provided in the read channel to amplify the filtered "read head" signal so that the pulses therein have magnitudes in a desired range to optimize pulse detection. Conventionally, an automatic gain control (AGC) feedback loop provides signals which are averaged and stored as charge on a capacitor to thereby provide a voltage value to control the VGA gain. Two such capacitors are usually used, one capacitor being used for storing signals based on gain errors found in peaks in the read signal due to servo fields and one capacitor being used for storing signals based on gain errors found in peaks in the read signal due to data fields. The capacitors are coupled to the VGA control terminal using a multiplexer to switch between the two capacitors dependent on which kind of field is passing the "read head". When read signal pulses are detected beyond an AGC target value, a gain error of one polarity has occurred and a small amount of charge is discharged from the active gain control capacitor by the loop to update the gain control signal thereon and thereby reduce the VGA gain. The loop charges or discharges this capacitor through a resistor. When read signal pulses fail to reach the AGC target value, a gain error of the opposite polarity has occurred and the loop charges the capacitor through the resistor to update the control signal to thereby increase the VGA gain resulting in an increase in the magnitude of succeeding pulses. One problem with these conventional AGC loops is that if the read head goes through a damaged data field where none of the pulses go beyond the target value then, at the end of the data field, the gain has generally increased to a level higher than is desired for a retrieving data from a subsequent intact data field. This results delays while the AGC loop recovers, i.e. the voltage on the capacitor reaches a suitable value, and may result in detection errors until a sufficient degree of recovery has occurred.

At the end of the "read head" traversing a servo field, the servo gain control capacitor stores the gain control value without further updating until the next servo field is encountered by that head. Similarly, the data gain control capacitor stores the gain control value after the head traverses a data field until the next data field passes thereby. During these control value storage durations without any updating, the stored gain control values deteriorate due to leakage of the corresponding capacitors. A further problem which can occur in a read channel, as indicated above, is asymmetry in channel responses to the channel input values of " 1 " and - 1 , the latter typically represented by the binary value'O". As described, atypical source of such asymmetry in a read channel occurs with the use of a magnetoresistive transducer in the read head which often provides a different magnitude output when reading a magnetization transition from the magnetic media in going from a first state to an opposite state than when making a transition from an alternative second state to an opposite state. In the absence of some compensation, a channel gain that is appropriate for one of the channel inputs will be inappropriate for the other leading to the possibility of errors in the detection process. Providing such asymmetry compensation requires providing an estimate of the amount of asymmetry currently present in the magnitudes of opposite polarity pulses in the read channel for the current value of gain in the VGA. This estimate is used in the asymmetry compensator typically provided following the variable gain amplifier in the read channel.

Thus, there is a desire for a digital peak detector subsystem that can better distinguish peaks in signals presented thereto, and improvements in associated subsystems that prepare the signals presented to the peak detection subsystem and use the results of the peak detection process, such as the gain control subsystem and the asymmetry compensation subsystem, to thereby provide enhanced performance of read channel subsystems in magnetic data storage and retrieval systems.

BRIEF SUMMARY OF THE INVENTION

The present invention provides digital peak detector for detecting those peak member values of either polarity in a digitized values sequence having magnitudes greater than, or in some instances equal to, each of those in a selected number of neighboring member values, that can selectively be required to be of the same polarity as the corresponding peak value, subject to exceeding both a selected absolute threshold and a selected multiple of a subsequent sequence member value. A peak value and polarity notifier provides a selected one of two alternative indicator pairs of signals of selectable time durations to indicate the occurrences of peak value members and the polarity thereof. The magnitudes of future member values in the digitized values sequence obtained from an analog signal are adjusted by varying the magnitude of that signal based on a magnitude average of selectively weighted differences between a number of past peak member values and a desired value. These differences available for use in this averaging are subject to being excluded if associated with known system operation problems but other member values are subject to being included if too much time has elapsed since the previous difference value based adjustment. A value based on this magnitude average is stored for selective use as an initial average value for the next such averaging. A programmable, resettable, extendable timer is used for determining the occurrences of such excessive elapsed times.

Magnitude asymmetries between peak member values of different polarities in the digitized values sequence are compensated by adding and subtracting therefrom based on a magnitude average of these differences after those associated with member values in the digitized values sequence of one polarity are negated and all in the average are selectively weighted. A value based on this magnitude average is also stored for selective use as an initial average value for the next such averaging.

In a magnetic data storage and retrieval system, the magnitudes over time of the digitized values sequence related to paired zones along tracks in the magnetic medium disk are accumulated and subtracted from one another for each pair. The accumulated difference results for each pair are used as an error signal for estimating the lateral position error with respect to the track of the "read head" in retrieving information from the stored magnetic data on the disk.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a mixed block and logic diagram of a peak detector in the present invention;

Figures 2 A and 2B show mixed block and logic diagrams of portions of a gain controller in the present invention;

Figure 3 shows a mixed block and logic diagram of a portion of an asymmetry compensator in the present invention;

Figure 4 shows a mixed block and logic diagram of a portion of an error detector in the present invention; and

Figures 5A, 5B and 5C shows a mixed block and logic diagram of portions of a signal notifier in the present invention along with timing diagrams therefor.

DETAILED DESCRIPTION Figure 1 shows a mixed block and logic diagram of a digital peak detection subsystem provided in connection with the data retrieval, or "read", channel of a magnetic data storage and retrieval system. The system shown allows the user thereof to compare the magnitude value of an incoming channel signal sample with the magnitude values of up to a selected number of both immediately preceding channel signal samples and immediately succeeding channel signal samples in searching for samples which, or which may approximately, coincide with the peaks of channel signal pulses resulting from magnetic transitions on the magnetic medium disk. This comparison process provides the means for determining whether any such channel signal sample has the greatest absolute peak magnitude value in such a set of neighboring samples as the basis for being considered as a sample representing a channel read signal pulse peak. In addition, this peak detector subsystem also allows selection by the user of an alternative peak detection method beyond the method just described, and that is a method determining whether a channel signal sample has the greatest maximum absolute value of just those samples in such a set which have the same polarity.

Furthermore, the peak detection subsystem of Figure 1 can be used to require that a channel signal sample, to be considered to represent a channel signal pulse peak, have an absolute value sufficiently larger than the absolute value of a more recent sample to assure then that this previous channel signal sample does not represent merely an overshoot or an undershoot result in the channel read signal following an even earlier channel read signal pulse rather than being a further valid pulse itself. Also, the subsystem not only requires that a channel signal sample, to be considered to represent a channel signal pulse peak, have a magnitude going beyond a qualifying threshold value to assure that its absolute value represents a valid channel read signal pulse, but further requires that this magnitude go beyond a qualifying threshold value suited to the corresponding sample polarity. That is, there are different qualifying threshold values used for samples corresponding to different polarities, and this arrangement also provides a basis for estimating current read channel response magnitude asymmetry. In the subsystem shown in Figure 1 , a magnetic material support disk,

10, mounted on a spindle, 10', and containing pluralities of magnetization direction reversals along each of a polarity of more or less concentric, circular tracks, is rotated on spindle 10' past a data retrieval transducer arrangement, 11, or "read head", positioned adjacent a selected track by a "head" positioner and initial signal processor, 12, to provide an initial analog channel read signal x(t). This signal is subjected to further processing in a signal processing block, 13, which includes a variable gain amplifier, 13', shown in Figure 2 A, an asymmetry compensator, 13", shown in Figure 3, and a channel equalization filter (not shown) to provide a read channel signal y(t), a signal sampler (not shown) to provide analog samples y(kT), or y, , and an analog-to-digital converter (not shown) providing digitized values for each such y,. The analog samples of the analog channel read signal obtained by the sampler after amplification and equalization of that signal are sent to the analog-to- digital converter where they are converted into digitized samples having six bit digital values in 2's complement form. Five magnitude bits for these digitized sample values plus a sign bit have been found sufficient for subsequent signal processing in the signal detector.

Alternatively, two analog-to-digital converters can be used along with a multiplexer and a delay element so that each such converter converts only every other analog sample to a digital value thereby allowing each converter to operate at half the sample rate. That is, the analog sample sequence is separated on an every other sample basis with the even numbered positions samples subsequence being supplied to an even converter, in one instance, and with the odd numbered positions samples subsequence being supplied to an odd converter in the other instance. The even converter and the odd converter each yield digitized samples for its corresponding subsequence again providing digital values in 2's complement form with five digit positions plus a sign bit. The outputs of two delay registers each connected to the output of one of these converters are each provided to a multiplexer which interleaves the odd and even subsequences of digitized sample values thereon to form a full sequence of digitized sample values for subsequent processing.

In either arrangement, a typical effective sampling rate is 80 mHz resulting in a sample period of 12.5 ns. Thus, there are typically 8 samples taken during the main lobe of the impulse response of the read channel as set by the filter cutoff frequency therein, and during the expected magnetic transition based pulse repetition period in the read channel signal. This is rapid enough to assure that a sample will occur sufficiently close to the occurrence of the peaks of magnetic transition based pulses to provide a reasonably representative value for that peak. Both the storing and retrieving of magnetic transitions from magnetic medium disk 10 are timed under the control of crystal control clocks, and so any frequency offset between the storage rate and the retrieval rate can be ignored. The sampling rate timing control signal forms the read channel system sampling clock signal with a period equal to the sample period, and is provided to various components used in the read channel system with those components in the subsystems shown in the drawings herein receiving that signal at an inverted "V" shape that is positioned at the inside of an edge of the component representation in those drawings.

The output digitized sample sequence from either arrangement described above is supplied from signal processing block 13 over a six digit line interconnection, 13 a, to a single sample clock period delay register, 14, from the output of which a sample digitized value is provided on a six digit line interconnection, 14a, delayed one sample period, for each input sample digitized value. The sign bit of each output sample digitized value of register 14 is also provided on a single digit line interconnection, 14b, to a four sample period delay line comprising four single sample clock period delay registers, 15, 15', 15" and 15'". The resulting sequence of sample digitized values on interconnection 14a is provided to a saturation and absolute value operation block, 16. The sign bit of each sample digitized value after passing through the delay line formed of registers 15, 15', 15" and 15 '" is provided to a subsystem output, 17, as a binary "0" value for a positive sample value or a binary "1" value for a negative value sample in accord with a 2's complement representation to form a sign bit indicator signal at that output.

Saturation and absolute value operation block 16 receives the digital values of the sequence of digitized value samples including the sign bits and transforms them from a magnitude range of -32 to +31 in which they are provided by the analog-to-digital converter to a range of 0 to +31 thus converting negative polarity values to positive values. As a result, the absolute values or magnitudes of the incoming samples digitized values are obtained in block 16, and are furthermore limited to occur in the range of 0 to +31 by having both - 31 and -32 be represented by +32. These sample digitized absolute values on provided at an output of operation block 16 on a five digit line interconnection, 16a. That is, any sample magnitude values exceeding 31 will be limited to a value of +31 by block 16, and, in addition, occurrences of current sample absolute values equal to +31 will be indicated by corresponding output bits provided by operation block 16 on a single digit line interconnection, 16b, indicating saturation has occurred for the current digitized sample received by that block. This saturation indication bit from block 16 for the current sample digitized value is supplied on interconnection 16b to a further four sample period delay line comprising four single sample clock period delay registers, 18, 18', 18" and 18'". Thus, a saturation indication bit appears at a subsystem output, 19, four sample periods following the receipt of the sample digitized value which caused the saturation bit indicator to appear at the output of absolute value and saturation operation block 16.

The absolute value of each current sample digitized value, limited to the range of 0 to 31 , is then provided from the output of operation block 16 on five digit line interconnection 16a to a further four sample clock period delay line comprising four single sample clock period delay registers, 20, 20', 20" and 20'". In addition, the absolute value of each current sample digitized value is supplied over interconnection 16a to the compared signal inputs of four comparators, 21, 21 ', 21 " and 21 '". Finally, the absolute value of each current sample digitized value is supplied on interconnection 16a to a multiplier, 22. The providing of each sample digitized absolute value occurring at the output of operation block 16 to the delay line comprising registers 20, 20', 20" and 20'", and to the compared signal inputs of comparators 21, 21 ', 21 " and 21 '", permits finding (a) whether, initially and concurrently, the current sample digitized absolute value represents a one-sided relative peak value with respect to the absolute values of up to four preceding digitized samples, and then, (b) whether that same sample digitized absolute value on a successive basis also represents a second-sided relative peak value with respect to the absolute values of up to four succeeding digitized samples. A determination that a digitized sample absolute value is both an initial one-sided relative peak value and a second-sided relative peak value with respect to the absolute values of up to four digitized samples on either side of that sample in time results in finding such a digitized sample absolute value to be a two sided peak value, and so represents a local magnitude peak in the channel read signal as sampled and digitized.

This determination is accomplished on the basis of each current digitized sample absolute value provided by block 16 first being compared with the absolute values of the last four preceding digital samples by comparators 21 through 21 '". Each of these comparators provides one of two binary values "1" and "0" at its output to indicate whether the value provided on the compared signal input thereof is greater than the signal value provided on the reference signal input thereof or not.

Thus, a current sample digitized absolute value, serving as a descriptive reference sample in the following description, is provided by operation block 16 over interconnection 16a to single sample period delay register 20. This value of descriptive reference sample from register 20 is provided after a sample period delay over a five digit line interconnection, 16c, to the reference input of comparator 21 as a one sample period delayed sample digitized absolute value for a magnitude comparison in comparator 21. The magnitude comparison will be made with the then current digital sample absolute value provided by block 16 ovgr interconnection 16a to the compared signal input of comparator 21 (the then current digital sample absolute value being the next succeeding sample digitized absolute value occurring at the output of block 16 after the occurrence of the descriptive reference sample value).

The one period delayed sample digitized absolute value in register 20 is also provided over interconnection 16c to single sample period delay register 20 ' . This value from register 20' is provided after a further single sample period delay over a further five digit line interconnection, 16d, to the reference input of comparator 21 ' as a two sample period delayed sample digitized absolute value for comparison in comparator 21 ' with then current sample digitized absolute value provided by operation block 16 to the compared signal input of comparator 21 ' (the second succeeding sample digitized absolute value occurring after the descriptive reference sample value).

Continuing in this manner, the two period delayed sample digitized absolute value in register 20' is further provided over interconnection 16d to single sample period delay register 20". This value from register 20" is provided over another five digit line interconnection, 16e, after a further sample period delay to the reference input of comparator 21 " as a three sample period delayed sample digitized absolute value for comparison in comparator 21 " with the then current sample digitized absolute value provided by operation block 16 to the compared signal input of comparator 21 " (the third succeeding sample digitized absolute value occurring after the descriptive reference sample value).

Finally, the three period delayed sample digitized absolute value in register 20" is further provided over interconnectionlόe to single sample period delay register 20'" . This value from register 20"'is provided after a further sample period delay over yet another five digit line interconnection, 16f, to the reference input of comparator 21 '" as a four sample period delayed sample digitized absolute value for comparison in comparator 21 '" with the then current sample digitized absolute value supplied by operation 16 to the compared signal input of comparator 21 '" (the fourth succeeding sample digitized absolute value occurring after the descriptive reference sample value). The four period delayed sample digitized absolute value stored in register 20'" is also available at a subsystem output, 23, as the descriptive reference sample digitized absolute value delayed four sample periods since it was the current sample digitized absolute value. Thus, each current sample digitized absolute value is initially compared concurrently with each of the immediately preceding four sample digitized absolute values in comparators 21 through 21 '" with this comparison being made in a single sample period. Thereafter, as that same sample value is shifted down the delay line formed by registers 20 through 20 "' , that sample value is further compared with the immediately succeeding four digitized sample absolute values in four separate comparisons each based on a corresponding one of these succeeding sample values which occurs in a corresponding one of the succeeding four sample periods. Hence, in some first sample period in which the descriptive reference sample is the then current sample digitized absolute value provided by operation block 16, that sample value, if it is to be found to represent a peak value, must in that first sample period exceed in magnitude the values of the four immediately preceding samples (unless one or more of the earliest four immediately preceding sample values are chosen to be ignored in the comparison evaluation as will be described below). The occurrence of the situation in which the descriptive reference sample in the sample period in which it is the current sample value at the output of block 16 exceeds in magnitude each of the immediately four sample absolute values will be indicated by each of comparators 21 through 21 '" providing a binary "1" value at its output. Such an occurrence of a binary "1" value at the output of each of comparators 21 through 21 '" indicates that a current sample digitized absolute value provided at the output of block 16 satisfies

|y_i|>|y,_j| forj = l, ..., N where, in the situation so far described, N = 4. Thus, such a sample is indicated to be an initial one-sided peak value relative to those of the four immediately preceding samples.

In each of the next four succeeding sample periods, this sample digitized absolute value, the descriptive reference sample, that was current in the first sample period indicated above, and which is found there to be a one-sided peak, will be compared in magnitude in each of the next four sample periods with the corresponding incoming new sample digitized absolute value occurring in that sample period which is the then current value. In each such sample period, the descriptive reference sample digitized absolute value, after shifting to the next comparator through the single sample period delay register in the delay line formed by single sample period delay registers 20 through 20 '" corresponding to that period, if it is to be found to represent a peak value, must be greater in magnitude than the then current sample digitized absolute value. Such a result in each such sample period will cause the corresponding comparator comparing the descriptive reference sample digitized absolute value with the then current sample digitized absolute value to provide a binary "0" value at its output in that period.

Should each of comparators 21 through 21 '" provide a binary "0" value at its output successively in the corresponding one of the next four sampling periods immediately following the sample period in which the descriptive reference sample digitized absolute value was the then current value, that descriptive reference sample digitized absolute value is indicated to satisfy lYil l Yi+_j I forj = l, ..., N where again, in the situation so far described, N = 4. Thus, such a sample is indicated to be a second-sided peak. If both the one-sided peak and the second- sided peak indications occur for a sample digitized absolute value, i.e. so that, for instance, both of the preceding equations hold for the descriptive reference sample digitized absolute value, that sample value represents a two-sided peak value relative to the values of the four immediately preceding and the four immediately succeeding samples with respect thereto.

The outputs of each of comparators 21 through 21 '" are connected to an input of a corresponding OR logic gate. Thus, the output of comparator 21 is connected to an input of a logic gate, 24. The output of comparator 21 ' is connected to the input of another OR logic gate, 24'. The output of comparator 21 " is connected to an input of a further OR logic gate, 24". The output of comparator 21 '" is connected to an input of a final OR logic gate, 24'". Hence, if any of the output comparators have a binary "1" value at its output, there will be a corresponding binary "1" value at the output of the OR logic gate connected thereto based on the logic followed by such a gate. On the other hand, by the logic of the gate, the presence of a binary "0" value on the output of one of these comparators requires that the OR logic gate connected thereto have a binary " 1 " value on another of its inputs if there is to be a binary "1" value at the output of that logic gate rather than a binary "0" value.

The subsystem of Figure 1 requires that at least one of these comparison results, between a current sample digitized absolute value and a preceding sample digitized absolute value, appear at the output of a corresponding one of these OR logic gates by having the required comparison be made in comparator 21 to appear at the output of gate 24. However, the further comparison results available from comparators 21 ', 21 " and 21 '" may or may not be used in the peak detection process implemented in the subsystem of Figure 1 at the choice of the system user, i.e. N in the inequalities above can be set to equal 1, 2, 3 or 4. These choices are given effect by control logic signals from the system controller, not shown, at any of the inputs to OR logic gate 24', 24" and 24 '"shown as open inputs. Thus, logic gate 24' has a open input, 25, logic gate 24" has an open input, 26, and logic gate 24'" has an open input, 27. Open inputs 25, 26 and 27 are connected to the system controller by control interconnections but such interconnections, as with the controller, are not shown. These same signals are provided over similar interconnections, again not shown, to open inputs, 25', 26' and 27', of three other OR logic gates provided at a subsequent location in the subsystem of Figure 1 to be described below. The control logic signal provided to input 25 has a binary "1" value if N < 2 but a binary "0" value if N = 2 or more. The control logic signal presented to open input 26 has a binary "1" value if N < 3 but a binary "0" value if N = 3 or 4. Finally, the control logic signal provided to open input 27 has a binary "1" value if N < 4 is true but a binary "0" value if N = 4. If one of the control signals to the open inputs 25, 26 and 27 of OR logic gates 24', 24" and 24'" has a binary "1" value, the corresponding one of these logic gates will have a binary "1" value at its output without regard to the binary value present at the output of that one of comparators 21 through 21 '" connected thereto. As a result, the output of such an OR logic gate will have a binary "1 " value thereon equivalent to indicating that the current sample digitized absolute value on the compared signal input of the comparator connected to this gate is greater than the delayed sample digitized absolute value presented to the reference input of that comparator.

In this circumstance, the test of whether the current sample digitized absolute value is greater than a preceding sample digitized absolute value provided by the comparator connected to such an OR logic gate, indicated by a binary "1" value on the gate output, will be indicated to have been passed no matter what magnitude relationship is actually present between two such sample digitized absolute values. On the other hand, the opposite test of whether a delayed sample digitized absolute value is greater than the current sample digitized absolute value provided by the comparator connected to such an OR logic gate, indicated by a binary "0" value on the gate output, cannot be indicated to .have been passed by that OR logic gate even if true. As indicated above, the pulse waveform from the magnetoresistive sensor, based on the accumulated magnetic responses of each quarter-width track in the servo field preamble, will not be based on perfectly matched magnetic transitions from each quarter-width track because there will be some transition positioning incoherence among the quarter-width tracks. The result will cause some pulse broadening at preamble transitions as a result of the slightly mismatched corresponding transitions occurring along the quarter-width tracks. A suitable choice for N determining the number of samples to be compared in determining the existence of a pulse peak can provide some protection against determining the double-humped portion of a waveform occasionally resulting from such mismatches represents two peaks rather than a single peak Thus, choosing N to result in comparing a sample or two more than the number of expected samples between the magnetic transition based pulses in the read signal waveform can be used to prevent the system from identifying more than one pulse during the pulse repetition period. Thus, N would be set to 4 in magnetic storage and retrieval systems in which magnetic transition based pluses in the read channel signal are expected to be separated by eight samples. Alternatively, N could be set to 3 in those systems in which magnetic transition based pulses in the read channel signal are expected to be separated by five samples. In this way, the peak detection subsystem of Figure 1 can analyze magnetic transition based pulses in the read channel signal over a variable sized "window" of samples at the choice of the system controller, not shown.

Each of OR logic gates 24 through 24'" have a further input than those so far described therefor. Thus, logic gate 24 has a further input, 29, logic gate 24' has a further input 30, logic gate 24" has a further input 31, and logic gate 24"' has a further input 32. Logic gate inputs 29 through 32 are connected to a logic arrangement extending from the delay line to which the sign bits of incoming sample digitized values are presented by single sample period delay register 14 as indicated above, the delay line comprising single sample period delay registers 15 through 15'". The sign bits of sample digitized values transmitted along this delay line that are stored in the registers therein are each compared in each sample period with the sign bit of the current sample digitized value to determine whether the sign bit of each delayed stored sample digitized value is the same as the sign bit of the current sample digitized value through the use of four EXCLUSIVE-OR logic gates, 33, 33', 33" and 33'". One input of each of logic gates 33 through 33'" is connected to receive the sign bit of the current sample digitized value from single sample period delay register 14. The other input of logic gate 33 is connected to the output of delay register 15 to receive sign bits of sample digitized values delayed one sample period through register 15 which are also provided to delay register 15'. Similarly, logic gate 33' has its remaining input connected to the output of delay register 15' to receive two sample period delayed sign bits which are also provided to delay register 15 ", and the remaining input of logic gate 33 " is connected to the output of register 15 " to receive three sample period delayed sign bits which are also provided to delay register 15'". Finally, the remaining output of logic gate 33'" is connected to the output of delay register 15'" to receive four sample period delayed sign bits which are also provided to subsystem output 17.

The output of logic gate 33 is connected to the input of an AND logic gate, 34. Similarly, the output of logic gate 33 ' is connected to the input of a further AND logic gate, 34'. The output of logic gate 33" is connected to the input of another AND logic gate, 34", and the output of logic gate 33'" is connected to the input of a final AND logic gate, 34'". The remaining input of each of AND logic gates 34 through 34'" is connected to a control logic signal open subsystem terminal, 35, which is connected over a control interconnection to the system controller both not shown. The control logic signal on terminal 35 provides a binary "1" value thereon in situations where the sign bits of sample digitized values are to have an effect on the results of the comparisons carried out in comparators 21 through 21 '" by acting through OR logic gates 24 through 24"', and provides a binary "0" value thereon when the sign bits of sample digitized values are not to have an effect on the comparison results provided by these comparators. .

Logic gate 33 thus compares the sign bit from the current sample digitized value with the sign bit from the sample digitized value one sample period earlier stored in register 15 and provides a binary "0" value at its output if the two sign bits are the same indicating the sample values had the same polarity, but a binary "1" value at its output if the sign bits are different indicating the sample values had opposite polarities based on the logic followed by that gate. Similarly, logic gate 33' provides similar binary values at its output if the sign bit from the current sample digitized value is the same or different from the two sample period delayed sign bit held in register 15'. Logic gate 33" also provides similar binary values at its output for same and different sign bits on comparing the sign bit from the current sample digitized value with a three sample period delayed sign bit stored in register 15". Finally, logic gate 33 '" provides similar binary values at its output for same and different sign bits upon comparison of the sign bit of the current sample digitized value with a four sample period delayed sign bit stored in register 15'".

Binary "0" values at the outputs of any of EXCLUSTvΕ-OR logic gates 33 through 33'", of course, leaves the outputs of corresponding ones of AND logic gates 34 through 34'" with a binary "0" value thereon following the logic of AND gates. That is, if there are no differences in the sign bits between the sign bit of the current sample digitized value and the delayed sign bits of earlier sample digitized values, there will be no binary "1" value outputs from any of logic gates 34 through 34'". On the other hand, a binary "1" value at the output of any of EXCLUSIVE-OR logic gates 33 through 33'" gives the possibility of having a binary "1" value at the output of the corresponding one of logic gates 34 through 34'" to which it is connected, but only if there is also a binary "1" value on terminal 35 allowing such indications of sign bit differences to be provided to the input of the corresponding one of OR logic gates 24 through 24'".

Thus, if a series of sample digitized values having the same polarity is provided by single sample period delay register 14 leaving binary "0" values at the output of gates 33 through 33'", and the control signal at terminal 35 has a binary "1" value, a further sample digitized value of the opposite polarity will result in a binary "1" value appearing at the outputs of each of logic gates 33 through 33'". This result will, in turn, will result in a binary "1 " value appearing at the outputs of each of logic gates 34 through 34'", and also a binary "1" value appearing at the outputs of each of logic gates 24 through 24'". As a result, there is an indication at the outputs of each of those logic gates 24 through 24'" actually providing magnitude comparison tests in view of the value choice for N that the current sample digitized value, having a polarity opposite those immediately preceding it, effectively has an absolute value which has exceeded the absolute values of those preceding samples of the initial polarity even though this may not in fact be true.

This arrangement is provided because of the possibility of missing a peak of the polarity opposite the polarities of the sample digitized values preceding it. That is, the pulses in the channel read signal of opposite polarity have different absolute value magnitudes due to some characteristic of the channel, such as the asymmetry described above, or the absolute values of pulses of both polarities may reach saturation. If the magnitudes of opposite polarity sample digitized absolute values are compared with the magnitudes of the preceding samples digitized values of an initial polarity by comparators 21 through 21 '" in the manner described above, there is likely to be a peak among the opposite polarity absolute values but which may not exceed the peak value in the initial polarity absolute values.

Forcing the subsystem of Figure 1 to recognize a one-sided peak with the occurrence of an opposite polarity sample digitized value in effect resets the system of Figure 1 to consider pulse peaks in the opposite polarity sample digitized absolute values despite magnitude differences between opposite polarity pulse peak values and initial polarity pulse peak values which may favor the initial polarity pulses. Thereafter, the detection subsystem will evaluate the succeeding opposite polarity sample digitized absolute values following the first of the opposite polarity sample digitized absolute values in the usual manner to determine whether there is an actual peak among the opposite polarity sample digitized absolute values since the sign bits for these samples will be the same. This evaluation, though, will begin comparing the current sample with fewer of the preceding samples as the polarity differences therewith keep the outputs of some of the earlier sample associated ones of OR logic gates 24 through 24 '"at a binary "1 " value without regard to relative magnitudes. That is, the detection subsystem will continue to exclude the effects of any initial polarity sample digitized values still in the delay line formed by single sample period delay registers 20 through 20'" since the corresponding sample sign bits will continue to differ from the most recent sample sign bits. This forcing of the subsystem of Figure 1 to recognize a one-sided peak with the occurrence of an opposite polarity sample digitized value is activated by the providing of a binary " 1 " value on terminal 35

The outputs of each of OR logic gates 24 through 24'" are provided to a corresponding one of the inputs of an AND logic gate, 36. Since the output of each OR gates 24 through 24'" must have a binary "1" value thereon to cause the output of AND logic gate 36 to have a binary "1 " value thereon , a binary "1" value at the output of gate 36 represents the occurrence of a one-sided peak having been detected in the sequence of digitized sample values with respect to up to four of the preceding digital samples of interest depending on the value of N (or a polarity change between the current digitized sample and those preceding samples). Each occurrence of a binary "1" value at the output of AND logic gate 36 is stored in a single sample period delay register, 37. This binary "1" value at the output of gate 36 is also complemented by a NOT logic gate, 38, and the resulting output binary "0" value of gate 38 is supplied to one input of each of a series of OR logic gates, 39, 39', 39" and 39'".

Assuming temporarily that the other inputs to OR logic gates 39 through 39'" are at a binary "0" value, the outputs of each of logic gates 39 through 39'" will, following the logic of OR logic gates, be at a binary "0" value which is supplied to an input of a corresponding one of aplurality of AND gates, 40, 40', 40" and 40'". Since a binary "0" value at the input of an AND logic gate results in a binary "0" value at the output of such a gate for the logic followed thereby, AND logic gate 40 provides a binary "0" value in a single sample period delay register, 37', connected to the output thereof. Similarly, AND logic gate 40' provides a binary "0" value in a further single sample period delay register, 37", connected to the output thereof. In the same manner, AND logic gate 40" provides a binary "0" value in another single sample period delay register, 37'", connected to the oytput thereof . Finally, the last of these AND logic gate 40'" provides a binary "0" value to an input of another AND logic gate, 41, connected to the output thereof which serves as the peak detection subsystem output device.

Also, the output of register 37 is connected to the second input of AND logic gate 40. In addition the output of register 37' is connected to the second input of AND logic gate 40', and the output of register 37" is connected to the second input of AND logic gate 40". Finally, the output of register 37'" is connected to the second input of AND logic gate 40'".

Once a one-sided peak digitized sample has been found, as indicated by a binary "1" value having been stored in register 37, that value is shifted through the series of single sample period delay registers 37', 37" and 37'" under the control of AND logic gates 40 through 40'" alternately connected therewith so long as that one-sided peak sample digitized absolute value continues to be greater in magnitude than each of up to four of the next sample digitized absolute values following thereafter. If the one-sided peak sample digitized absolute value is followed by a next current sample digitized absolute value which is of a smaller magnitude, the output of comparator 21 is a binary "0" value leading to a binary "0" value at the output of OR logic gate 24, assuming this current digital sample has not had a change in polarity from the preceding digital sample. This occurrence alone will lead to a binary "0" value at the output of AND logic gate 36.

This binary "0" value at the output of gate 36 is then stored in register

37 and a complement binary "1" value is provided at the output of NOT logic gate

38 to the inputs connected thereto of each of OR logic gates 39 through 39'". As a result, the binary "1" value previously stored in register 37, representing the previously detected one-sided peak sample digitized absolute value, is in effect passed from register 37 to the other input of AND logic gate 40 to which the output of register 37 is connected, and so to register 37' because of the output of logic gate

39 being at a binary "1" value due to the binary "1 " value on its input from gate 38. Binary "0" values are provided in a similar manner to registers 37" and 37'" from registers 37' and 37", respectively.

Similarly, if the next following current sample digitized absolute value is less in magnitude value than the last previous one-sided peak sample digitized absolute value, a binary "0" value will occur at the output of comparator 21 ' which will lead to a binary "0" value at the output of OR logic gate 24' if N is of a value 2 or greater, and if there has not been a change in the polarity of the current digitized sample from that of the preceding sample. This result again will lead to a binary "0" value at the output of AND logic gate 36 which will be stored in register 37, and the binary "1" value complement thereof resulting at the output of logic gate 38 will be provided to the inputs of OR logic gates 39 through 39'" connected thereto. This will result in providing the binary "1" value previously stored in register 37' from that register to register 37 ", and providing the binary "0" value previously stored in register 37" to register 37'". In the same manner, a further following current sample digitized absolute value that is less in magnitude than the last previous one-sided peak digital sample absolute value will lead to comparator 21 " causing a binary "0" value to appear at the output of AND logic gate 36 to result in providing the binary "1 " value previously stored in register 37" to register 37'". Finally, one more following current sample digitized absolute value that is less in magnitude than the last previous one-sided peak digital sample absolute value will lead to comparator 21 '" causing a binary "0" value to appear at the output of AND logic gate 36 to result in providing the binary "1 " value previously stored in register 37'" through AND logic gate 40'" to AND logic gate 41.

Any occurrence of in this succession of comparisons of a current sample digitized absolute value exceeding in magnitude the value of the last previous one-sided peak sample digitized absolute value, or being of opposite polarity to the preceding samples, will lead to a binary "1" value appearing at the output of AND logic gate 36, and so result in a new binary "1 " value being stored in register 37 as a one-sided peak sample indicator (or a sample polarity change indicator). For a one-sided value indication, binary "0" values will also be provided in registers 37', 37" and 37'". For a polarity change indication, the contents of registers 37', 37" and 37'" will be preserved and transmitted to AND logic gate 41 as the difference in polarity between the initial polarity sample sign bits and the current and immediately thereafter coming sample sign bits of opposite polarity will keep binary "1" values at the outputs of the earlier sample associated ones of OR logic gates 39, 39', 39" and 39'" because they each connected to a sign bit polarity difference indicator gate. That is, there is an input from each of OR logic gates 39 through 39'" connected to the output of a corresponding one of AND logic gates 34 through 34'" which have a binary "1" value at the outputs thereof following a change in polarity between the current sample digitized value and the immediately preceding sample digitized values. As indicated above, such a result also leads to a binary "1" value at the output of AND logic gate 36 which is supplied to register 37, and causes the previous contents of register 37 and of registers 37' through 37'" to be transmitted to the input of the one of the AND logic gates connected thereto. Further current digital samples of the changed polarity are tested for being peak values in the successive sampling periods, and the values stored in register 37', 37" and 37'" are transmitted to the inputs of the AND logic gates 40, 40', 40" and 40'" connected thereto without modification to allow any previous initial polarity sample peak to be indicated to AND logic gate 41. Referred to above are open inputs 25', 26' and 27'of corresponding ones of OR logic gates 39', 39" and 39'". As stated there, the control signals provided on these open inputs by the system controller are the same ones that are supplied to open inputs 25, 26 and 27of OR logic gates 24', 24" and 24'". Thus, if N does not equal 4 but instead equals a lesser integer, one or more of OR logic gates 39'", 39" or 39' will always have a binary "1" value at its output to thereby assure transmission, through the AND logic gate to which that output is connected, of the binary value stored in the preceding register connected to the input of that AND logic gate. This transmission will be to the succeeding gate or register connected to the output of that AND logic gate as appropriate. The foregoing arrangement for verifying a two-sided peak digitized sample results in those sample digitized absolute values found to be two-sided peak values being characterized by the absolute value inequalities given above if the control signal provided on subsystem terminal 35 has a binary "0" value during operation. However, a binary "1" value for that signal during operation results in sample digitized absolute values found to be two-sided peak values being characterized by having a one-sided peak characteristic of

I y, I > I y,-_j I f°^r all j = 1, 2, ..., N where sgn(y,) = sgn(y,._J), and also having a second-sided peak characteristic of I y, I > I Yi_+j I for all j = 1, 2, ..., N where sgn(y) = sgn(y_i+j).

The arrival of a binary "1" value at the input of AND logic gate 41 from AND logic gate 40'" indicates that the sample digitized value corresponding to the sample digitized absolute value then held in register 20'" represents a two- sided peak value relative to up to N of the immediately preceding digital samples and up to N of the immediately succeeding digital samples (all of the same polarity if a binary "1 " value is on subsystem input 35) in being greater in magnitude than any of them. However, this status alone for the digital sample absolute value currently in register 20'" is not sufficient for the subsystem of Figure 1 to provide an indication that this two-sided peak sample digitized value is indeed a read channel signal peak value representing a magnetic transition in a track on disk 10 sensed by magnetoresistive sensor 11 rather than a peak value due to some other cause such as a noise burst or some other anomaly. Two other tests are imposed by the subsystem of Figure 1 that must be passed by the two-sided peak sample digitized absolute value currently stored in register 20 '" . These tests, if passed, also lead to binary "1" values being presented to the other inputs of AND logic gate 41 beyond the input to which the out put of AND logic gate 40'" is connected. The presence of binary "1" values at each of the inputs of AND logic gate 41 results in a binary "1" value appearing at the output of gate 41 which indicates the value in register 20'" is a two-sided sample digitized absolute value qualified to be considered a read channel signal peak value.

The first of these tests guards against the peak detection subsystem determining that a read channel signal undershoot or overshoot recovery following the occurrence of a magnetic transition pulse in that signal is another magnetic transition based peak value. A positive polarity magnetic transition based pulse transmitted through the channel, for instance, can have an undershoot develop in the channel read signal following such a pulse which is typically characterized by a rather long duration opposite polarity excursion in this signal rather than a relatively sharp pulse-like excursion signal. Similarly, a negative polarity magnetic transition pulse can be followed by an overshoot in the read channel signal typically appearing as a positive polarity relatively long duration excursion in the read channel signal rather than a sharp pulse-like excursion. The system of Figure 1 guards against mistaking such undershoots and overshoots for a magnetic transition based pulse by requiring, in a first test for these occurrences, that digital sample absolute values stored in register 20'" exceed a selected multiple of the current digital sample absolute value provided by operation block 16 to thereby assure any signal excursion for which peak has been detected is a sufficiently abrupt or sharp excursion to be a magnetic transition pulse.

As indicated above, sample digitized absolute values provided by operation block 16 are in turn provided over interconnection 16a to multiplier 22. Conveniently, multiplier 22 provides the current digital sample absolute value multiplied by two as one output signal therefrom, that value multiplied by four as another output signal, and that value multiplied by eight as a further output signal. Choosing these multiples of two, four and eight allows multiplier 22 to be shift register based with multiplication involving merely shifting the current sample digitized absolute value one digit position to the left for multiplying by two, two digit positions to the left for multiplying by four, and three digit positions to the left for multiplying by eight. These three multiplication product digitized value output signals are all provided by multiplier 22 to a multiplexer, 42, which also has a zero digital value input signal indicated by the open terminal input thereto.

Multiplexer 42 directs the connection of a selected one of the multiples of the current sample digitized absolute value from multiplier 22 to a five digit line interconnection, 42a, at the output of that multiplexer. This selection by a user selection signal from the system controller, not shown, is provided on a two digit line control interconnection, 43 , extending therefrom but shown in part, that is connected to a selection control input of multiplexer 42. The selected sample multiple signal is provided over interconnection 42a to the compare signal input of a comparator, 44, which also has the sample digitized absolute value currently stored in register 20'" supplied thereto. If the sample digitized absolute value from register 20'" exceeds the multiple of the current digital sample absolute value indicating a relatively large excursion in the read channel signal is being represented by the value in register 20"'which is characteristic of a relatively sharper signal excursion, comparator 44 provides a binary "1" value at its output. Otherwise, a binary "0" value occurs at the output of comparator 44..

A further waythe subsystem ofFigure 1 guards against mistaking an undershoot or an overshoot for a magnetic transition pulse in the read channel signal is to accept that a pulse in that signal is sufficiently abrupt or sharp to be a magnetic transition pulse in those instances when the polarity of the digitized sample having its absolute value stored in register 20 "' is opposite to the polarity of the current digitized sample. As described above, the output of AND logic gate 34'" provides a binary "1" value to indicate there is a polarity difference between the four sample period delayed sign bit of a previous sample digitized value and the sign bit of the current sample digitized value. A binary "0" value is provided at the output of AND logic gate 34 '"if these sign bits are identical.

The outcomes of these two tests are combined by connecting the output of AND logic gate 34'" to the input of an OR logic gate, 45, and the output of comparator 44 is connected to the other input of logic gate 45. Hence, if either of the tests used for guarding against mistaken determination of undershoots and overshoots being magnetic transition pulses is passed, logic gate 45 provides a binary "1" at its output which is connected to input of AND logic gate 41. Since logic gate 41 , as previously described, has connected to an input thereof the output of gate 40'" providing the indicator signal that a two- sided peak sample digitized absolute value has been detected, the passing of the undershoot-overshoot tests is given effect only in connection with the determination of the presence of a two-sided peak sample digitized absolute value stored in register 20'". A further test which a two-sided peak sample digitized absolute value must pass to be considered representing a magnetic transition pulse in the read channel signal is that the peak value be of sufficient magnitude to exceed a selected threshold value to thereby eliminate consideration of smaller peak values. Such smaller peak values have been judged more likely to be due to noise or other effects rather than due to a magnetic transition pulse being sensed by sensor 11 from a track in magnetic disk 10. However, the same threshold value may not be suitable for use with both positive polarity read channel signal pulses and negative polarity pulses. This is true in situations where there is asymmetry in the magnitudes of magnetic transition based pulses of opposite polarity due to polarity dependent responses of the magnetoresistive sensor in data retrieval transducer arrangement 11 , or to other effects in the read channel, in the absence of any compensation therefor somewhere in the read channel prior to their reaching the peak detection subsystem of Figure 1. Such a situation occurs, for instance, if asymmetry compensation is performed in the detection process rather than attempting to compensate for the magnitude asymmetries in the pulses prior to reaching the peak detector system. This need for different threshold values for different polarity pulses can also arise where such polarity dependent magnitude asymmetries are compensated by an asymmetry compensator acting on the read channel signal pulses somewhere in the read channel prior to their reaching the peak detection subsystem of Figure 1 but with insufficient compensation. Hence, this threshold test is supplied with possibly different threshold values in such situations in the peak detection subsystem of Figure 1 for read channel signal pulses of different polarities. A multiplexer, 46, directs to a five digit interconnection, 46a, at the output thereof either a positive threshold digitized value provided on a five digit line first control interconnection, 47, by the system controller, not seen, or a negative threshold digitized value provided by that system controller on a further five digit line control interconnection, 48. The selection of which threshold value appearing on one of the inputs of multiplexer 46 to provide at the output thereof is determined by the signal provided over the interconnection from the output of register 15'" to a selection control input of multiplexer 46. This signal provides the sign bit delayed four sample periods of a previous sample digitized value to the selection control input of multiplexer 46, this being the sign bit of the same sample digitized value for which the digitized absolute value magnitude is stored in register 20'".

This sample digitized absolute value stored in register 20'" is provided to the compared signal input of a further comparator, 49, which also receives the selected threshold value at the output of multiplexer 46 at its reference signal input. The magnitude of the sample digitized absolute value from register 20'" being beyond the threshold value provided from multiplexer 46 results in comparator 49 having a binary "1" value at its output. If this sample value falls short of the magnitude of the corresponding threshold value, a binary "0" value appears at the output of comparator 49. This comparator output is connected to a further input of AND logic gate 41 so that the information of the sample digitized absolute value in register 20'" is beyond the corresponding threshold value is given effect only for two-sided peak sample digitized values because of AND logic gate 41 requiring binary "1 " values at all of its inputs to provide a binary "1 " value at its output, 50. Such a binary "1 " value in the qualified two-sided peak indicator signal provided at output 50 indicates that a qualified two-sided peak sample digitized absolute value has been identified. Finally, the sample digitized absolute values stored in register 20'" are provided to a subtractor, 51. A user selectable average value desired for pulse peaks in the read channel signal to attain is supplied by the system controller, not seen, on a five digit line control interconnection, 52, to the other input of subtractor 51. The differences between this desired average value and the magnitudes of the sample digitized absolute values provided from register 20'" is a measure of the gain error in the control of the variable gain amplifier in signal processing block 13, and these gain error values are provided from the output of subtractor 51 in succession over a six digit line interconnection, 51a, (the added digit line carries a sign bit) to a subsystem output, 53, to form an output gain error signal at that output.

Figure 2A shows a mixed block and logic gate diagram of a portion of a gain control subsystem used for controlling the gain of the variable gain amplifier provided in signal processing block 13 of Figure 1. This gain control subsystem uses the six digit gain error signal developed in subtractor 51 of Figure 1, as provided at subsystem output 53 thereof, as the basis for adjusting the gain of the variable gain amplifier in signal processing block 13. This is done in a manner so as to aid in the detection of peak value magnitudes of pulses due to magnetic transitions in the read channel signal generated by the rotating of track sector servo fields in magnetic medium disk 10 past the magnetoresistive sensor in data retrieval transducer arrangement 11 .

Alternatively, adjusting the gain of that amplifier to aid in detecting peak values of pulses in the read channel signal due to rotating track sector data fields by the magnetoresistive sensor is based on gain error signals for such data fields generated in the system controller arrangement for read channel estimation and control, not shown here, which six digit signals are provided to the input of a six digit line interconnection, 60. Because servo field data and data field data are recorded at different times under different conditions, the characteristics of the read channel signal developed from such data can differ from one another and therefore must be separately treated in controlling the effective gain in the variable gain amplifier for each of those kinds of data. Gain error signals based on read channel signal servo field pulses provided on interconnection 53 and gain error signals based on data field pulses provided on intersection 60 are transmitted thereover to corresponding inputs of a multiplexer, 61. Control signals provided on a selection control input, 62, of multiplexer 61 determine which of these gain error signals on interconnections 53 and 60 are directed by multiplexer 61 to a six digit line interconnection, 63, at an output thereof which is a further five digit line interconnection. A binary "0" value for the control signal on terminal 62 results in the data gain error signal on interconnection 60 being present at the output of multiplexer 61, and a binary "1 " value signal at terminal 62 results in the servo gain error signal and intersection signal 53 being present at the output of multiplexer 61.

The control signal for selection control input 62 of multiplexer 61 is provided at an open terminal, 64, by the system controller over an intersection between that terminal and the controller where both the system controller and this interconnection are not shown in Figure 2A, and this signal serves as the servo field indicator signal. This control signal at terminal 64 has a binary "0" value unless a servo field in magnetic medium disk 10 is rotating past the magnetoresistive sensor in data retrieval transducer arrangement 11 on which occasions the system controller changes this control signal to have a binary "1" value. The system controller changes the signal value back to "0" after the servo field has finished passing the sensor.

A change in value of the control signal at terminal 64 is delayed in further transmission for two sample clock periods by two single sample period delay registers, 65 and 66, connected in series with terminal 64 through having the input of register 65 connected to that terminal and the output of register 65 connected to selection control input 62. Thus, a value change indicating that a servo field has been encountered by the magnetoresistive sensor is provided to selection control input 62 of multiplexer 61 two sample periods after this encounter has begun. Since the time at which a servo field begins passing the magnetoresistive sensor is not synchronized with the system sampling clock, such a signal is an asynchronous signal. Because of this characteristic, the signal at terminal 64 through unfortunate timing could result in a "hang-up" in register 65 leaving it uncertain as to which binary value should be reflected at the output thereof until an electrical noise pulse results in forcing the register to take the current binary value provided. Hence, two such registers are employed together in series to give adequate time for the input binary value to register 65 to become established therein so that a proper binary value ultimately appears at the output of register 66. The delayed servo field indicator signal at the output of delay register 66 is also provided as a gain control subsystem output, 67.

Whichever of servo field gain error signal on interconnection 53 and data field gain error signal on intersection 60 is selected for provision at output of multiplexer 61 on interconnection 63 is transmitted to the input of a further multiplexer, 68. The other input of multiplexer 68 is a five digit line interconnection to a fixed binary "0" value indicated by the open terminal extending therefrom. Thus, multiplexer 68 provides either the selected one of the servo field and data field gain error signals or a zero value signal on a further six digit line interconnection, 69, at the output thereof under the direction of a control signal provided at a selection control input, 70, thereof. Thus, this control signal selects between providing a gain error correction signal at the output of multiplexer 68 or a zero value signal effectively preventing any gain value correction input for use in the subsequent gain control accumulator, to be described below, controlling the gain value of variable gain amplifier 13'. A binary "1" value at input 70 directs multiplexer 68 to provide a gain error correction signal at the output thereof and a binary "0" directs multiplexer 68 to provide a zero value signal at that output This control signal at selection control input 70 of multiplexer 68 is provided from an AND logic gate, 71 , having its output connected to selection control input 70 of that multiplexer. Thus, following the logic of that gate, the signals to the inputs of AND logic gate 71 determine together whether multiplexer 68 provides an gain error updating signal or not to the gain control accumulator.

One signal applied to an input of AND logic gate 71 is the signal from the output of a NOR logic gate, 72, which is also provided as a gain control subsystem output signal at a subsystem output terminal, 73. As a result, there can be a binary "1" value at the input of AND logic gate 71 connected to NOR logic gate 72 only if the input signals to gate 72 are all at a binary "0" value following the logic of gate 72. There are three inputs to NOR logic gate 72, each of which on those occasions it receives a signal having a binary "1" value prevents any gain error corrections by the gain error signals provided on interconnection 63 to multiplexer 68. A first such input to NOR logic gate 72 is provided at an open terminal, 74, as a control signal from the system controller over an interconnection to that terminal, neither of which is shown, which allows the system controller to prevent any corrections for gain errors from taking place in the gain control accumulator under conditions selected by that controller. The remaining two open inputs, 75 and 76, to NOR logic gate 72 permit preventing gain error signals from providing gain error corrections in the gain control accumulator due to detection by either the system itself in an arrangement not shown, or by an external entity not shown, of conditions making any such correction at the time subject to unacceptable error or risk of error. One such condition which could introduce unacceptable errors in the gain value of voltage gain amplifier 13' is the occurrence of thermal asperities in the magnetoresistive sensor because of a change in the separation distance between the sensor and magnetic medium disc 10 thereby leading to greater or lesser average resistance in that sensor to result in shifting the zero signal reference value of the read channel signal.

The other input to AND logic gate 71 is provided by an a single digit line interconnection, 77, at the output of a further multiplexer, 78. A first input to multiplexer 78 is provided by the output signal from a series connected pair of single sample period delay registers connected to an open input, 79, which is connected to the system controller over an interconnection neither of which is shown in Figure 2 A. Terminal 79 is connected to the input of single sample period delay register, 80, having an output which is connected to the input of a further single sample period delay register, 81, with an output connected to the input of multiplexer 78. The system controller provides a signal to terminal 79 as a data field indicator signal which has a binary " 1 " value whenever a data field in magnetic medium disk 10 is being rotated past the magnetoresistive sensor in data retrieval transducer arrangement 11. Series connected delay registers 80 and 81 are again used because the data field indicating signal provided to terminal 79 is also an asynchronous signal subject to causing register 80 to "hang up" between providing either a binary "0" value or a binary "1" value until forced toward the one representing the input signal by electrical noise therein. The remaining input signal to multiplexer 78 is provided by an

OR logic gate, 82, having its output connected to the remaining input of multiplexer 78. One input of OR logic gate 82 is connected to an open terminal, 83, connected by an interconnection to an output of the circuit shown in Figure 2B that provides a signal indicating the need for a gain error correction in the absence of such a correction having occurred within a selected period of time after the preceding one as will be described below. The other input of OR logic gate 82 is connected to the output of a further OR logic gate, 84. The inputs of OR logic gate 84 are the sample digitized absolute value saturation magnitude indicator signal from peak detection subsystem output 19 in Figure 1, and the qualified two-sided peak value indicator signal from the peak detector subsystem output 50 in that figure. The output of OR logic gate 84 also provides an output signal for the gain control subsystem of Figure 2A at an open output terminal, 85.

Which of these inputs of multiplexer 78 is directed to provide its signal to output 77 thereof is determined by a control signal provided at a selection control input, 86, of that multiplexer. Selection control input 86 of multiplexer 78 is connected to the output of delay register 66. Thus, the signal on terminal 64, indicating whether a servo field in magnetic medium disk 10 is being rotated past the magnetoresistive sensor in arrangement 11 or not, determines which of the inputs of multiplexer 78 is directed to be connected to provide the signal thereat to interconnection 77 at the output thereof.

A binary "0" value at the output of delay register 66 on selection control input 86 of multiplexer 78 results in the input of multiplexer 78 connected to delay register 81 to be connected to interconnection 77 at the output of that multiplexer. As a result, the absence of a binary "1" value in the two sample period delayed servo field indicator signal from delay register 66 results in the two sample period delayed data field indicator signal from delay register 81 being transmitted through multiplexer 78 to the input of AND gate , 71. A binary "1 " value in this indicator signal, in the absence any conditions preventing providing gain error corrections, results in a binary "1" value occurring at the output of gate 71. Such a value on selection control input 70 of multiplexer 68 results in connecting input interconnection 63 to output interconnection 69 to thereby transmit the gain error signal over interconnection 69 to the following gain control accumulator. This gain error signal so transmitted is that due to data gain errors because the signal from delay register 66 also appears at selection control input 62 of multiplexer 61.

On the other hand, a binary "1" value in the delayed servo field indicator signal from delay register 66 on selection control input 86 of multiplexer 78 causes the signal at the output of OR logic gate 82 to be connected to interconnection 77 at the output of multiplexer 78. As stated above, the delayed servo field indicator signal from register 66 also appears at selection control input 62 of multiplexer 61 to result in the servo field gain error signal, provided over interconnection 63 to an input of multiplexer 68, to appear on interconnection 69 at the output thereof when any of the signals on terminals 83, 50 or 19 have a binary "1" value. Such values will result in a binary "1" value at the output of AND logic gate 71 if there are not conditions at that time preventing gain corrections.

That is, the servo field gain error signal will be provided to the subsequent gain control accumulator whenever there is detected a digitized sample value in the digital peak detector system of Figure 1 that is a two-sided peak resulting in a binary "1" value in the qualified peak indicator signal at subsystem output 50 or saturates operation block 16 resulting in a binary "1" value in the saturation indicator signal at subsystem output 19. Alternatively, a servo field gain error update will be permitted to be introduced to the gain control accumulator through terminal 83 if no qualified two-sided peak sample digitized value or a saturated sample digitized value occurs within a selected period of time.

The delayed servo field indicator signal from terminal 64 is also provided to a negating input of an AND logic gate, 87, and to the input of a single sample period delay register, 88, and further, to a direct input of another AND logic gate, 89. The output of delay register 88 is provided to the other input of AND logic gate 87 which is a direct input, and to the other input of AND logic gate 89 which is a negating input. A period of time passing between the last encounter by the magnetoresistive sensor in arrangement 11 with a servo field in magnetic medium disc 10 and the next such encounter exceeding a few sampling periods will result in there being a binary "0" value stored in delay register 88 provided from delay register 66.

The occurrence of the next encounter between the magnetoresistive sensor and a servo field will result in the servo field indicator signal on terminal 64 switching from a binary "0" value to a binary "1" value which, after two sample delay periods, is applied to the negating input of AND logic gate 87, the input of delay register 88, and to the direct input of AND logic gate 89. Since a binary "0" value has been theretofore stored in delay register 88, the negating of that value at the negating input of logic gate 89 results in effectively being a binary "1" value provided to the AND logic of that logic gate. The switching of the servo field indicator signal from a binary "0" value to a binary "1" value after two sample periods results in the binary "1" value at the output of delay register 66 causing AND logic gate 89 to switch its output value from a binary "0" value to binary "1" value.

After a sampling period, a binary "1" value is stored in delay register 88 which is provided to the negating input of logic gate 89 and results in there being an effective binary "0" value provided to the AND logic of gate 89 causing the output thereof to switch back from a binary "1" value to a binary "0" value. Thus, a change in the servo field indicator signal from a binary "0" value to a binary "1 " value, indicating a servo field has been encountered by the magnetoresistive sensor, leads to a single sample clock period duration, binary "1" value pulse occurring at the output of AND logic gate 89. This pulse is supplied to an output of the gain control subsystem of Figure 2A at an open terminal, 90. The subsequent ending of the encounter leaves the output of AND logic gate 89 at a binary "0" value.

Such a binary "0" to binary "1" value change in the servo field indicator signal at terminal 64 after a two sampling period delay at the beginning of such an encounter is also provided to the negating input of AND logic gate 87. The binary "1" value effectively provided to the logic of gate 87 prior to encountering a servo field is then switched effectively to a binary "0" value. This occurrence, along with the binary "0" value provided from the output of delay register 88, leaves the output of logic gate 87 at a binary "0" value. The subsequent binary "1" value stored in delay register 88 following the encountering of a servo field is applied after a sampling period to the other input of logic gate 87, but the output of that gate remains at a binary "0" value because of the situation just described at the negating input thereto. However, upon the encounter between the magnetoresistive sensor and the servo field coming to an end, the servo field indicator signal at terminal 64 switching from a binary "1" value back to a binary "0" value which is applied to the negating input of gate 87. This change results in a binary "1" value being effectively provided to the AND logic of gate 87 causing the output of that logic gate to switch from a binary "0" value to a binary "1 " value. The output of gate 87 switches back to a binary "0" value following a single sampling delay period because of the binary "0" value then stored in delay register 88. As a result, the ending of an encounter between a servo field and a magnetoresistive of sensor results in a binary "1" value pulse of a single sample clock period duration appearing at the output of AND logic gate 87.

Encounters between data fields in magnetic medium disk 10 and the magnetoresistive sensor in arrangement 11 lead to the data field indicator signal at terminal 79 changing from a binary "0" value to a binary "1" value. After a two sampling period delay, this change is applied from delay register 81 to the negating input of an AND logic gate, 91, and to the input of a single sampling period delay register, 92, and further, to a direct input of another AND logic gate, 93. The output of delay register 92 is connected to the remaining input of AND logic gate 91 which is a direct input, and also to the remaining input of AND logic gate 93 which is a negating input.

The arrangement of logic gates 91 and 93, delay register 92, and the interconnections therebetween, being identical to the arrangement of logic gates 87 and 89, along with delay register 88 and the interconnections therebetween, results in the former arrangement exhibiting the same behavior with respect to value changes in the data field indicator signal at terminal 79 as is exhibited by this latter arrangement with respect to changes in value of the servo field indicator signal at terminal 64. Thus, the encounter between a data field in magnetic medium disc 10 and the magnetoresistive sensor leads to a binary "1 " value that, after a two sample period delay, will result in the output of delay register 81 going from a binary "0" value to a binary "1" value. A concomitant single sample clock period, binary "1" value pulse occurs at the output of logic gate 93, and so at an output terminal, 94, of the gain control subsystem of Figure 2A connected thereto. At the termination of such an encounter between a data field and the magnetoresistive sensor, a single sample clock period duration binary "1" value pulse will appear at the output of AND logic gate 91.

As can be seen in Figure 2A, the single sample clock period duration, binary "1 " value pulses occurring at the output of AND logic gates 89 and 93 to indicate the beginnings of encounters between the magnetoresistive sensor in arrangement 11 with servo fields and data fields, respectively, are immediately routed to other portions of the gain control subsystem of Figure 2A as control signals for use in operating those other portions of that subsystem. On the other hand, the single sample period duration, binary "1" value pulses appearing at the outputs of AND logic gates 87 and 91 to indicate the endings of encounters with servo fields and data fields, respectively, are not immediately used as control signals for other portions of the gain control subsystem. Rather, the output of AND logic gate 87 is connected to an input of a further AND logic gate, 95, and to the input of a NOR logic gate, 96. Similarly, the output of AND logic gate 91 is connected to an input of a further AND logic gate, 97, and to a further input of NOR logic gate 96. This arrangement is provided so as to prevent the single sample period duration, binary "1" value pulses, indicating terminations of encounters between the magnetoresistive sensor and either a servo field or a data field, from being given effect as control signals in those situations where thermal asperities have been detected in connection with those track sector portions of magnetic medium disk 10 associated with these fields.

As indicated above, the detection signals provided on terminals 75 and 76, indicating the detection of internal and external problems, respectively, by value changes therein, carry information of any occurrence of a thermal asperity problem in connection with a track sector portion on magnetic medium disc 10 being rotated past the magnetoresistive sensor in arrangement 11. Thus, an OR logic gate, 98, has a corresponding one of a pair of inputs thereof connected to terminals 75 and 76. The output of OR logic gate 98 is connected to an input of an AND logic gate, 99.

A control signal is provided from the system controller over an interconnection, both of which are not shown in Figure 2A, to an open terminal, 100, connected to an input of AND logic gate 99, which allows the system controller to determine whether to give effect to detected thermal asperities. That is, the system controller can determine whether the pulses at the outputs of logic gates 87 and 91, indicating terminations of encounters between the magnetoresistive sensor and servo and data fields, respectively, will be permitted or prevented from acting as control signals in other portions of the gain control subsystem of Figure 2 A.

Of course, any signals representing detected problems in the system should only be given effect for thermal asperity purposes when a servo field or a data field in magnetic medium 10 is being encountered by the magnetoresistive sensor in arrangement 11. Thus, a further OR logic gate, 101, is provided having a corresponding one of a pair of inputs thereof connected to the output of delay register 66 to thereby receive the delayed servo field indicator signal, and the remaining input connected to the output of delay register 81 to receive the delayed data field indicator signal. The output of OR logic gate 101 is provided to another input of AND logic gate 99. Thus, the output of AND logic gate 99 is at a binary "0" value unless a thermal asperity problem is detected during an encounter between the magnetoresistive sensor and either a servo field or a data field on magnetic medium disc 10, and unless thermal asperity problems are directed to prevent pulses at the end of such servo fields and data fields from having effect in other portions of the control system.

The output of AND logic gate 99 is provided to the reset input of an R-S flip-flop, or latch, 102. The output of NOR logic gate 96 is provided to the input of a single sample period delay register, 103, with the output of delay register 103 being connected to the set input of latch 102. The output of latch 102 is connected to an input of each of AND logic gates 95 and 97.

The outputs of AND logic gates 87 and 91 will have a binary "0" value thereon if, as explained above, the magnetoresistive sensor is not encountering a servo field or a data field or, during such encounters, the ends of those fields have not yet been reached. As a result, the output of NOR logic gate 96 in these circumstances will be at a binary "1 " value which is stored in delay register 103, and from there provided to the set input of latch 102. Thus, the output of latch 102 typically has a binary "1" value thereon which is provided as an input to each of AND logic gates 95 and 97.

An end of a field value change from a binary "1" value to abinary "0" value in either the servo field indicator signal on terminal 64 or the data field indicator signal on terminal 79 will, as indicated above, lead to a single sample period duration, binary "1 " value pulse at the output of the corresponding one of AND logic gates 87 and 91. Such a pulse from one of these logic gates is applied to the input of the corresponding one of AND logic gates 95 and 97 to which that pulsing gate is connected, the outputs of gates 95 and 97 being binary "0" values without such a pulse occurring at that input thereof. In the absence of a binary "1" value at the output of AND logic gate 99 indicating a thermal asperity problem, a single sample period pulse with a binary "1" value at the outputs of either of AND logic gates 87 and 91 will lead to a binary "0" value at the output of NOR logic gate 96 for storage in delay register 103. However, delay register 103 by its delay will prevent this "0" value from being immediately applied to the set input of latch 102. Thus, the occurrence of a pulse with a binary "1" value at the outputs of either of AND logic gates 87 and 91 results in both inputs of the corresponding one of AND logic gates 95 and 97 being at a binary "1 " value leading to the output of that gate changing to a binary "1" value for a single sampling clock period.

The output signal from logic gate 95 is supplied to a gain control subsystem output shown as an open terminal, 104, in Figure 2 A. Similarly, the output of AND logic gate 97 is provided as a subsystem output at an open terminal, 105. In addition, the output signals from gates 95 and 97 are also provided as control signals to other portions of the gain control subsystem.

On the other hand, a problem condition concerning thermal asperities, or some other problem condition, may be determined to have occurred during the passing of a servo field or data field in magnetic medium disc 10 by the magnetoresistive sensor in arrangement 11. If that condition is permitted by the system controller to have an effect on the control signals otherwise generated by the occurrence of the end of a servo or data field, a binary "1" value will occur at the output of AND logic gate 99 which is applied to the reset input of latch 102. Thus, in the absence of a pulse occurring at the outputs of AND logic gates 87 and 91 due to value changes from a binary "1" value to a binary "0" value in either the servo field indicator signal on terminal 64 due to the end of a servo field, or in the data field indicator signal on terminal 79 due to the end of a data field, there will be binary "1" values applied to both the set and reset inputs of latch 102 forcing its output to a binary "0" value. The subsequent occurrence of a single sample clock period binary "1 " value pulse at the output of AND logic gate 87 due to the end of a servo field, or at the output of AND logic gate 91 due to the end of a data field, will leave the output of the corresponding one of AND logic gates 95 and 97 at a binary "0" value. This results because of the binary "0" value at the output of latch 102 prevents either of gates 95 and 97 from indicating that an end of field pulse has occurred for either a servo field or a data field, and the outputs of the corresponding one of logic gates 95 and 97 remains at a binary "0" value after the single sample clock period binary "1" value pulse at the output of either of logic gates 87 and 91 ends.

This situation will continue until the output of AND logic gate 99 changes from a binary "1" value to a binary "0" value indicating the erroneous parts of the track sector have passed by the magnetoresistive sensor. At such a point the logic value at the output of gate 99 will return to a binary "0" value allowing the output of latch 102 to return to a binary "1" value.

As described above, the occurrence or not of a servo field in magnetic medium disk 10 rotating past the magnetoresistive sensor in arrangement 11 is indicated in the servo field indicator signal on terminal 64 by that signal having a binary "0" value in the absence of a servo field passing the magnetoresistive sensor, and having a binary "1" value upon the occurrence of a servo field moving past that sensor. The servo field indicator signal determines first in multiplexer 61 , in being applied at selection control input 62 thereof, whether the gain error signal based on a servo field on interconnection 53, or the gain error signal based on a data field on interconnection 60, is to appear on interconnection 63 at the output of multiplexer 61. In addition, this servo indicator signal is applied to selection control input 86 of multiplexer 78 to determine which of those signal values, in whichever of the gain error signals reaches interconnection 63, will be transmitted through multiplexer 68 to appear on interconnection 69 to thereby have an effect in the subsequent gain control accumulator in adjusting the gain of variable gain amplifier 13'. Those other gain error signal values in the gain error signal reaching interconnection 63 not selected through multiplexers 78 and 68 have values of zero substituted therefor. However, those selected gain error signal values provided on interconnection 69 do not directly affect the gain of the variable gain amplifier through the subsequent gain control accumulator by their magnitudes alone but instead are "weighted" by a multiplicative factor resulting in just the "weighted" signal values being used in the subsequent gain control accumulator for adjusting the gain of variable gain amplifier 13'. Such multiplications are provided in a multiplier, 110, with the multiplicative "weighting" factors being provided by the system controller, not shown, over interconnections extending therefrom, 111, 112 and 113, shown only in part in Figure 2 A. These "weighting" factors are negative values tp provide the desired negative feedback effect so that increasing error magnitudes lead to reduced gain values for variable gain amplifier 13', in effect, providing a negative signal gradient for operating that amplifier. Each of these interconnections comprises three digit lines thus allowing multiplicative factors with values between 0 and 8. The value of a multiplier is chosen by the system controller based on balancing the need for sufficiently rapid acting control loop to adjust the gain of the variable gain amplifier versus the need for stability of that loop and for stability of its interactions with other loops affecting the read channel signal such as the asymmetry compensation loop to be described below. Typically, the loop gain for the gain control subsystem will be relatively high as the sources of gain errors can change characteristics relatively quickly. There are two different multiplicative factors made available for multiplying those of the gain error values based on data fields used in the subsequent gain control accumulator, the first of these factors being provided on interconnection 112 by the system controller, not shown, which is used during the initial stages of acquiring the proper gain for read channel signals based on data fields. The second multiplicative factor is provided on interconnection 113 by the system controller and is used, once the initial gain value has been established, to adjust the gain during the traversal of the remainder of that data field. Interconnections 112 and 113 provide these multiplicative factors to a multiplexer, 114, in which the selection is implemented as to which of the factors on interconnections 112 and 113 is to be provided on a three digit line interconnection, 115, at the output thereof. The selection is implemented under control signals provided at a selection control input, 116, of multiplexer 114. The control signals are provided at selection control input 116 of multiplexer 114 by the system controller over an interconnection, neither of which is shown, extending therefrom to an open terminal, 117, which is connected to control selection input 116.

The selected one of the two data field multiplicative factors appearing on interconnection 115 from the output of multiplexer 114 is provided to an input of a further multiplexer, 118. A further, alternative multiplicative factor to be used in connection with gain error signals based on servo fields is provided on interconnection 111 by the system controller to the other input of multiplexer 118. The appropriate one of the servo field associated multiplicative factor and the data field associated multiplicative factor is selected in multiplexer 118 to appear on a three digit line interconnection, 119, at the output thereof by the delayed servo field indicator signal provided on terminal 64 through the connection from delay register 66 to a selection control input, 120, of multiplexer 118. The occurrence of a servo field in magnetic medium disk 10 being rotated past the magnetoresistive sensor in arrangement 11 , indicated by a binary "1 " value in the servo field indicator signal on terminal 64, leads to the selection of the servo field multiplicative factor on interconnection 111 to appear on interconnection 119 at the output of multiplexer 118. In the absence of a servo field being rotated past magnetoresistive sensor, the corresponding binary "0" value in the delayed servo field indicator signal provided to selection control input 120 results in the data field multiplicative factor selected in multiplexer 114 appearing on interconnection 119 at the output of multiplexer 118.

As described above, the selected signal values either from the selected one of the gain error signals based on servo fields, provided on interconnection 53, or from the gain error signals based on data fields, provided on interconnection 60, are present on interconnection 69 interspersed with the zero values substituted for the other signal values in that selected gain error signal which were not selected values. These selected six bit signal values from the selected gain error signal and the interspersed zero values on interconnection 69 are provided to an input of multiplier 110, along with providing the corresponding selected three bit "weighting" factor, or multiplicative factor, on interconnection 119 to the other input of multiplier 110, for being multiplied together therein. The sixteen bit multiplication result is provided at the output of multiplier 110 on a further sixteen digit line interconnection, 121. These "weighted" gain error values are provided to a gain control accumulator formed by an adder, 122, to which the "weighted" values on interconnection 121 are provided at an input thereof, and further formed by a multiplexer, 123, and a single sample clock period delay register, 124, having its output fed back to a second input of adder 122.

In more detail, this gain control accumulator has the output of adder 122 provided on a further sixteen bit interconnection, 125, which transmits the weighted gain error value sums provided thereby to an input of multiplexer 123. The other input of multiplexer 123 is connected to an arrangement for providing initial values, developed as described below, as a basis for initiating, or reinitiating, the operation of the gain control accumulator using a beginning value other than zero through selecting such a value rather than the sums from adder 122 to appear at the output thereof. The output of multiplexer 123 is provided on a further sixteen digit line interconnection, 126, which provides the output of multiplexer 123 to single sample clock period delay register 124. The output of the gain control accumulator is taken from the output of delay register gain control accumulator output signal on yet a further sixteen digit line interconnection, 127, which is fed back to the second input of adder 122. Furthermore, the eight most significant bits of the values in this signal supplied by delay register 124 are taken from interconnection 127 and provided on an eight digit line interconnection, 128a, to a digital-to-analog converter, 129. The analog signal developed in converter 129 is supplied to the gain control input of variable gain amplifier 13 ' as the gain setting value signal therefor.

Thus, assuming an initial gain setting value has already been placed in delay register 124 through multiplexer 123, the gain control accumulator operates by providing either such an initial value after storage thereof previously in delay register 124, or sum of the formed by the last value stored in delay register 124 and the most recent "weighted" gain error value after storage thereof in delay register 124, over interconnection 127 to the input of adder 122. The next "weighted" signal value provided from multiplier 110 (which may be zero), is then added in adder 122 to either this previously stored initial value or to this previously stored sum, whichever is present, and the result is transmitted through multiplexer 123 to delay register 124 to replace the previously stored value held therein (assuming a new initial value is not to be introduced by multiplexer 123). This operation continues until such a new initial value is inserted into delay register 124 to restart the process. Thus, the gain control accumulator output signal, g_co^_c^, provided from delay register 124 as the output signal of the accumulator for servo fields can be expressed as:

where y_p represents two-sided peak, saturated or timed-out sample digitized absolute values and k represents the designation of the first two-sided peak, saturated or timed-out sample digitized absolute value occurring after the injection of Y_mιt into delay register 124. Multiplier m_uis the "weighting" factor applied, and a_v is the desired threshold value for the polarity of the sample digitized value involved. Also, d represents the delay through the processing subsystems. This summing continues to the occurrence of the next such initial value injection or to the ending of the current rotation of a corresponding servo field or data field in magnetic medium disk 10 past the magnetoresistive sensor in arrangement 11. The eight most significant bits of the values in this gain control accumulator output signal supplied at the output of delay register 124 are taken frora interconnection 127 and also provided on a further eight digit line interconnection, 128b, to the first inputs of each of two further multiplexers, 130 and 131. Thus, the signal supplied to the first inputs of these two multiplexers is also the gain setting signal supplied to converter 119, and is supplied to these multiplexers to store the final ones of such signal values, i.e. the final gain setting values, that correspondingly occur at the termination of rotation of either a servo field or a data field past the magnetoresistive sensor. Multiplexers 130 and 131 are each part of a corresponding gain setting value holding and maintainance feedback loop. Thus, multiplexer 130 forms such a loop with a holding register,

132, which is a single sample clock period delay register. Similarly, multiplexer 131 forms such a loop with a holding register, 133, which again is a single sample clock period delay register. The output of multiplexer 130 is provided on an eight digit line interconnection, 134, which provides output signal values from multiplexer 130 to the input of delay register 132. Delay register 32 provides the signal value stored therein during the preceding sampling period at its output to an eight digit line interconnection, 135, which provides that signal value to the remaining input of multiplexer 130. In the presence of a binary "0" value at a selection control input, 136, of multiplexer 130, that multiplexer presents the value from interconnection 135 to interconnection 134 and so to the input of delay registerl32 resulting in this value recirculating in this loop to thereby be maintained available from the loop. Selection control input 136 of multiplexer 130 is connected to the output of AND logic gate 95 which provides a binary "0" value at its output at all times except when the end of a servo field in magnetic medium disk 10 rotates past the magnetoresistive sensor in arrangement 11 so as to hold the recirculating value in the loop.

However, since the output of AND logic gate 95 is connected to selection control input 136 of multiplexer 130, a single sample clock period duration, binary "1" value pulse is provided at the output of AND logic gate 95 in the absence of thermal asperity problems at the end of a servo field rotating past the magnetoresistive sensor as described above. Thus, a new gain setting value is obtained as a replacement for the currently recirculating one from gain control delay register 124 on interconnection 127 at the end of a servo field rotating past the magnetoresistive sensor as this pulse causes multiplexer 130 to direct a gain value setting from interconnection 127 to interconnection 134 from where it is stored in delay register 132. Termination of the pulse after a single sample period at the output of AND logic gate 95 leaves again a binary "0" value on that output which is applied to selection control input 136 of multiplexer 130 to keep this new gain setting value recirculating and maintained in the loop.

Similarly, the loop containing multiplexer 131 recirculates and holds gain setting values provided to multiplexer 131 on interconnection 128b from gain control delay register 124 by directing such values to its output and so onto another further eight digit line interconnection, 137, to the input of delay register 133 for storage therein. A single sample clock period later this value is placed on a further eight digit line interconnection, 138, that connects the output of register 133 with the remaining input of multiplexer 131. Thus, the setting value is recirculated and so maintained available in this loop until such time as a new value is injected therein at the end of a data field in magnetic medium disk 10 passing by the magnetoresistive sensor in arrangement 11. Such an occurrence of the end of a data field is, as described above, indicated by a single sample clock period duration, binary "1" value pulse occurring at the output of AND logic gate 97 which is connected to a selection control input, 139, of multiplexer 131. In the absence of such a pulse, the binary "0" value otherwise at the gate 97 output causes multiplexer 131 to direct the value on interconnection 138 to interconnection 137 to provide the desired recirculation of that value. The binary "1" value pulse causes the injection of a new gain setting value into this loop in the same manner as such a value was introduced in the loop based on multiplexer 130 and register 132 for servo fields.

Thus, the final gain setting value determined at the end of the last servo field encountered by the magnetoresistive sensor, and the final gain setting value determined at the end of the last data field encountered by the magnetoresistive sensor, are provided in the loops based on multiplexer 130 and delay register 132 and based on multiplexer 131 and delay register 133, respectively. These recirculating gain setting values can then be provided at such later times as when either a new servo field or a new data field is encountered by magnetoresistive sensor in magnetic medium disc 10 rotating thereby. The availability of such values in the loops assures that an initial gain setting value can be provided for variable gain amplifier 13 ' at the beginning of such field encounters even though the gain adjustment subsystem has no data from such a field concerning the needed gain at the outset of the encounter. The providing of these initial gain control setting signal values at the beginning of such field counters will be described below.

However, the values recirculated and maintained in these loops based on multiplexer 130 and delay register 132 on the one hand, and on multiplexer 131 and delay register 33 on the other hand, are not the only values useable as initial gain setting values at the beginning of servo field and data field encounters. That is, the system controller can override the use of these stored gain setting values, obtained from operation of the subsystems shown in Figures 1 and 2A during encounters between the magnetoresistive sensor and either servo fields or data fields, by instead directly supplying gain setting values chosen by that controller to either of two further registers 140 and 141. The system controller, not shown, can insert a servo field gain setting value in register 140 chosen by that controller over an interconnection extending therebetween of which only part, 142, is shown in Figure 2 A. Similarly, the system controller can insert a data field gain setting signal value chosen by it into register 141 over a further interconnection of which only a part, 143, is shown in Figure 2A. This override capability of the system controller to insert chosen values in register 140, used as a servo field initial gain setting value rather than the value then being recirculated and maintained in the loop based on multiplexer 130 and delay register 132, is given effect through a further multiplexer, 144. Similarly, the system controller exerts its override capability to use gain setting values stored by it in register 141, instead of the value being recirculated and maintained in the loop based on multiplexer 131 and delay register 133, through a further multiplexer, 145. The gain setting value being recirculated and maintained in the loop based on multiplexer 130 and delay register 132 is provided to multiplexer 144 on interconnection 135. The value stored in register 140 is supplied to multiplexer 144 over a further eight digit line interconnection, 146. In the same manner, the gain control setting signal value being recirculated and maintained in the loop based on multiplexer 131 and delay register 133 is provided to multiplexer 145 on interconnection 138. The value stored in register 141 is provided to multiplexer 145 on a further eight digit line interconnection, 147.

Whichever gain setting value provided to the inputs of multiplexer 144 on interconnections 135 and 146 is selected, in the manner described below, to be used for a servo field encounter is provided by multiplexer 144 at its output on a further eight digit line interconnection, 148. Similarly, whichever gain setting value provided to the inputs of multiplexer 145 on interconnections 138 and 147 is selected, as will be described below, to be used for a data field encounter is provided at the output of multiplexer 145 on a further eight digit line interconnection, 149. A further multiplexer, 150, has interconnections 148 and 149 connected to inputs thereof, and directs either the selected servo field gain setting value on interconnection 148 or the selected data field gain setting value on interconnection 149 to a final eight digit line interconnection, 151, at the output thereof as will be described below. Interconnection 151 is connected to the remaining input of multiplexer 123 to provide one of these gain setting values for insertion by multiplexer 123 into the eight most significant bit positions in gain control delay register 124 as the initial value Y_lnit for controlling the gain of variable gain amplifier 13' at the beginning of a corresponding servo field or data field. This selection of either the selected servo field gain setting value on interconnection 148 or the selected data field gain setting value on interconnection 149 is accomplished in multiplexer 150 by signals provided to a selection control input, 152, thereof. Selection control input 152 is connected to the output of delay register 66 so as to receive the two sample periods delayed servo field indicator signal provided on terminal 64. Thus, whenever the delayed servo field indicator signal has a binary "1 " value indicating that a servo field in magnetic medium disc 10 is rotating past the magnetoresistive sensor in arrangement 11, multiplexer 150 directs the servo field gain setting value on interconnection 148 to interconnection 151 at the output thereof so as to transmit that value to multiplexer 123. In other situations without a servo field rotating past the magnetoresistive sensor, the delayed servo field indicator signal at the output of delay register 66 has a binary "0" value and, as a rersult, multiplexer 150 directs the data field gain setting value on interconnection 149 to interconnection 151 for transmission to the input of multiplexer 123. A selection must be made in multiplexer 144 between the servo field gain setting value inserted in register 140 by the system controller and the servo field gain setting value recirculating and maintained in the loop based on multiplexer 130 and delay register 132 prior to the selection made in multiplexer 150 described above. This selection in multiplexer 144 is made through signals provided at a selection control input, 153, of multiplexer 144. This selection occurs under the control of the system controller, not shown, through providing signals over interconnections extending therefrom, also not shown, to a pair of open terminals, 154 and 155, connected as inputs to an OR logic gate, 156, and in connection with the signal developed at the output of AND logic gate 89. As indicated above, the signal developed at the output of AND logic gate 89 includes a single sample clock period duration, binary "1 " value pulse following a change in value of the delayed servo field indicator signal provided on terminal 64 from a binary "0" value to a binary " 1 " value. Such a signal value change on terminal 64 indicates that a servo field in magnetic medium disc 10 has begun rotating past the magnetoresistive sensor in arrangement 11.

The output of AND logic gate 89 is connected to the input of a NOT logic gate, 157. The output of gate 157 is connected to an input of an AND logic gate, 158, which has its output connected to an input of OR logic gate 156. In addition, the output of AND logic gate 89 is connected to an input of an OR logic gate, 159, having its output connected to a selection control input, 160, of multiplexer 123. A binary "1 " value pulse at the output of AND logic gate 89 causes that multiplexer to direct a servo field gain setting value from interconnection 151 to interconnection 126 for transmission to, and storage in, gain control delay register 124 as the initial value Y_ιnlt for controlling the gain of variable gain amplifier 13' at the beginning of a corresponding servo field or data field. The binary "0" value at the output of AND logic gate 89 otherwise causes multiplexer 123 to direct sums from adder 122 to interconnection 126 for transmission to, and storage in, gain control delay register 124.

A binary "0" value will remain stored in a single sampling period delay register, 161, having its input connected to the output of OR logic gate 156, if AND logic gate 89 has a binary "0" value at its output and there have been no binary "1" values in signals received at terminals 154 and 155 from the system controller since the last time there was as binary "1 " value at the output of AND logic gate 89. Though a binary "0" value at the output of AND logic gate 89 leads to a binary "1" value at the output of NOT logic gate 157 and so at the input of AND logic gate 158 to which it is connected, the previous occurrence of a binary "1" value pulse at the output of AND logic gate 89 lead to a binary "0" at the output of NOT logic gate 157 and so at that input of AND logic gate 158. This binary "0" value was stored in register 161 leading to that register providing a binary "0" value to the input of AND logic gate 158 to which it is connected.

In these circumstances, the occurrence of a single sample clock period duration, binary "1" value pulse in the signal developed at the output of AND logic gate 89 will result in a binary "0" value continuing to be stored in delay register 161 absent binary "1" values occurring at terminals 155 and 156. This situation follows because the binary "0" value in delay register 161 is supplied to one input of AND logic gate 158 so that the signal value at the output of AND logic gate 89, whether a binary "0" value or a binary "1" value, is unable to cause the output of AND logic gate 158 to change from a binary "0" value to a binary "1" value. The output of register 161 is also connected to selection control input 153 of multiplexer 144, and so a binary "0" value is also applied to selection control input 153 of multiplexer 144. Multiplexer 144 in this condition directs the gain setting value on interconnection 135 connected to its input to interconnection 148 connected to its output for transmission through multiplexer 150 to multiplexer 123. Thus, a change in value in the servo field indicator signal on terminal 64 from a binary "0" value to a binary "1 " value, indicating the start of a servo field rotating past the magnetoresistive sensor, results in the delayed version of that signal from the output of delay register 66 causing multiplexer 150 to accept from multiplexer 144 on interconnection 148 the servo field gain setting value stored in the loop based on multiplexer 130 and delay register 132. Multiplexer 150 transmit this value over interconnection 151 to multiplexer 123. The single sample clock period duration, binary "1" value pulse that results at the output of AND logic gate 89 from this change in value in the signal on terminal 64 directs multiplexer 123 to accept that signal value from multiplexer 150 on interconnection 151 and transmit it over interconnection 126 to the eight most significant bit positions in gain control register 124 as an initial value to be used for this servo field. However, the system controller, not shown, may direct that a newly substituted gain setting value be used as the next servo field initial value. To do so, the system controller causes the control signal on terminal 154 to change from a binary "0" value to a binary ' 1 " value which will load the selected new value provided by the system controller across the interconnection therefrom which includes interconnection portion 142 into register 140 through providing this value change at terminal 154 to the clock input of that register. In concurrence, this value change at terminal 154 will cause the output of OR logic gate 156 to change from having a binary "0" value to having a binary "1 " value, following the logic of that gate, thereby resulting in a binary "1" value being thereafter stored in delay register 161. As a result, a binary "1" value is applied

to selection control input 153 of multiplexer 144 and to the input of AND logic gate 158 to which the output of delay register 161 is connected. In the absence of a servo field being rotated past the magnetoresistive sensor, the output of AND logic gate 89 will be a binary "0" value leading to the putput of NOT logic gate 157 being a binary "1" value. In these circumstances, the binary "1" value in delay register 161 will continue until the next occurrence of a single sample clock period duration, binary "1" value pulse at the output of AND logic gate 89 as a result of a value change from binary "0" value to a binary "1" value on terminal 64 due to a servo field beginning to pass the magnetoresistive sensor. The occurrence of such a pulse will cause the output of NOT logic gate 157 to change from a binary "1 " value to a binary "0" value so that the output of AND logic gate 158 goes from a binary "1" value to a binary "0" value which is supplied to OR logic gate 156 and will lead to a binary "0" value subsequently being stored in delay register 161.

However, during the single sample clock period in which this binary " 1 " value pulse is present at the output of AND logic gate 89, the binary "1" value stored in delay register 161 will continue to be applied to selection control input 153 of multiplexer 144. Thus, the gain setting value stored in register 140 by the system controller is presented on interconnection 146 to multiplexer 144 which, in this situation, provides that value on interconnection 148 to be transmitted through multiplexer 150 to multiplexer 123. Since the single sampling period binary "1" value pulse at the output of AND logic gate 89 is also provided to the input of OR logic gate 159, this value provided by the system controller to register 140 will be provided by multiplexer 123 on interconnection 126 to be stored in the eight most significant bit positions of gain control delay register 123.

In a further alternative, the system controller, again not shown, may direct that the currently stored gain setting value in register 140 be used as the next servo field initial value without substituting a new value therefor. To do this, the system controller causes the control signal on terminal 155 change from a binary "0" value to a binary '1" value. This value change at terminal 155 will cause the output of OR logic gate 156 to change from having a binary "0" value to having a binary "1" value, following the logic of that gate, thereby resulting in a binary " 1 " value being thereafter stored in delay register 161. As a result, a binary "1" value is applied to selection control input 153 of multiplexer 144 and to the input of AND logic gate 158 to which the output of delay register 161 is connected. The operation from this point to insert an initial gain setting value in the eight most significant bit positions of gain control delay register 124 proceeds just as described above for inserting a newly substituted gain setting value but instead inserting therein the currently stored value in register 140.

The selection of a data field initial gain setting value for insertion in gain control delay register 124, based on either the gain setting value provided by the system controller to register 141 or the gain setting value which is recirculating and maintained in the loop formed by multiplexer 131 and delay register 133, proceeds in an identical manner as for the servo field initial gain setting value insertion therein just described except for the substitution of some different control signals. Thus, the subsystem for the data field initial gain setting value insertion in gain control delay register 124 relies on the servo field indicator signal at terminal 64 remaining at a binary "0" value and the data field indicator signal supplied to terminal 79 when a data field on magnetic medium disc 10 begins to rotate past the magnetoresistive sensor in arrangement 11 changing from a binary "1" value to a binary "0" value. This value change at terminal 79 provides a corresponding single sample clock period duration, binary "1" value pulse at the output of AND logic gate 93. The output of AND logic gate 93 is connected to another input of OR logic gate 159.

In addition, the system controller, not shown, provides control signals over interconnections, not shown, to a pair of open terminals, 164 and 165. These open terminals are connected to inputs of an OR logic gate, 166. A NOT logic gate, 167, having an input also connected to. the output of AND logic gate 93 to receive the binary "1" value pulse therefrom, has its output connected to an input of an AND logic gate, 168. The output of AND logic gate 168 is connected to the remaining input of OR logic gate 166. The output of logic gate 166 is connected to the input of a single sampling period delay register, 169, having an output connected both to the remaining input of AND logic gate 168 and to a selection control input, 170, of multiplexer 145. This arrangement comprising multiplexer 145, logic gates 159, 166, 167, 168 and single sample clock period delay register 169 operate in the same manner with the same kinds of control signals on terminals 164 and 165 for data fields to insert gain setting values in register 124 as does the arrangement comprising multiplexer 144, delay register 161 and the logic gates and terminals in this latter arrangement having numerical designations 10 less than the corresponding components in the first arrangement.

As indicated above, a "watch dog" timer can be used to assure that there is a maximum time duration between the last gain error signal value, as "weighted" by a multiplier factor, that is added into the accumulated total stored in gain control delay register 124 and the occurrence of adding the next such "weighted" gain error signal value to that accumulated sum. The resulting forced adding of a "weighted" gain error signal value to the accumulated sum of such values in delay register 124 when such duration is exceeded occurs, as indicated above, by the signal provided to input terminal 83 of the gain control subsystem of Figure 2A. The signal to terminal 83 is developed in the programmable "watch dog" timer system shown in Figure 2B.

The maximum duration to be permitted between the last "weighted" gain error signal value being added to the accumulated total stored in gain control delay register 124 in the gain update subsystem of Figure 2 A and the next such value added is set by the system controller, not shown. The system controller provides a selected initial count value to an eight-bit storage register, 180, over an interconnection, not shown, except for a terminal portion, 181, thereof. This count value is an input to register 180 and is loaded into that register by the system sampling clock signal after its arrival thereat.

The initial count value stored in register 180 is provided across seven digit lines to the inputs on the left-hand side of a nine bit down counter, 182, and is loaded into that counter by a change in value of the signal provided to a load control input, L, from a binary "0" value to a binary "1" value. Counter 182 begins counting down toward a zero value from the loaded initial count value after being enabled to do so by a change in value of the signal provided to an enable input, E, from a binary "0" value to a binary "1" value at a rate based on the sampling clock rate. The initial count value loaded into counter 182, as selectively multiplied in a manner to be described below, in connection with the rate of counting down to the zero count value, defining the end of the clocked counter time-out, determines the maximum time duration permitted between the providing of a "weighted" gain error signal value to the accumulated total in gain control delay register 124 in Figure 2 A and the providing of the next such value thereto.

Thus, this maximum time duration can be adjusted by the system controller for differing conditions occurring in the read channel and associated circuitry, including differences in the kinds and formatting of magnetic medium disks 10 being used and differences in selected sampling rates. Typically, this means that the maximum time duration for this "watch dog" timer should exceed other characteristic durations occurring in the magnetic data storage and retrieval system during which the gain errors measured are not reliable or should otherwise not be used in adding to the accumulated total in gain control delay register 124 for adjust the gain value of variable gain amplifier 13'. One such example mentioned above is the one microsecond gap preceding servo fields during which no valid magnetic transition based pulses occur. Any attempt to use the gain errors measured in that duration would lead to forcing the gain of variable gain amplifier 13 ' below what it should be for the following servo field.

Valid timeouts of the "watch dog" timer of Figure 2B, i.e. counter 182 reaching a zero value after counting down from the initial count value last loaded therein, are prevented from happening by the occurrence of a) selected events indicating that gain error values are being u_^sed sufficiently often in adjusting the gain of variable gain amplifier 13 ', or b) that the system controller has determined that available gain error signal values are not to be used in connection with further adjustments of the gain of variable gain amplifier 13'. These events or determinations are used to reset counter 182 through forcing a new initial count value to be inserted therein prior to counter 182 counting down to a zero count value.

Each of these events or determinations, as a basis for causing a reset of counter 182, is represented by a corresponding change from a binary "0" value to a binary "1" value on one of the inputs to an OR logic gate, 183. The output of logic gate 183 is connected to load control input L of counter 182, and a change from a binary "0" value at the output of logic gate 183 to a binary "1 " value causes counter 182 to accept the initial count value provided to the inputs thereof from register 180. Counter 182 is a nine-bit counter with its two least significant input bits set to a binary "0" value as indicated by the two open input terminals on the left-hand input side of that counter. The seven most significant bit inputs of counter 182 are connected to the seven least significant bit outputs of register 180 so that the seven least significant bits in the initial count value stored in register 180 are correspondingly provided in order as the seven most significant bits in counter 182.

The system controller, not shown, can force a new initial count from register 180 into counter 182 at any time that controller determines to do so by providing an initial count value over interconnection 181 which has a binary "1" value as its most significant bit. This follows because the most significant bit output of register 180 is connected to an input of OR logic gate 183 resulting in a binary "1" value appearing at the output of gate 183 and at input L of counter 182. Since counter 182 is always reset to the initial count value currently stored in register 180 upon a binary " 1 " value occurring on input L thereof, an initial count value which has a binary "1" value as its most significant bit will be immediately loaded into counter 182.

Counter 182 is reset to the initial count value currently stored in register 180 at the beginning of an encounter involving a servo field in magnetic medium disc 10 revolving past the magnetoresistive sensor in arrangement 11. This occurs because of the corresponding single sample clock period duration, binary "1" value pulse provided in this circumstance on output terminal 90 of the gain control subsystem of Figure 2A. As described above, this pulse is provided at the output of AND logic gate 89 in response to a delayed servo field indicator signal appearing on input terminal 64 of that system. This reset of counter 182 at the start of a servo field passing the magnetoresistive sensor assures, for a sufficiently small initial count value, that gain errors determined in that servo field will be given effect in adjusting the gain to an acceptable value for variable gain amplifier 13' to make certain the peak detection subsystem of Figure 1 acquires and transmits the remaining information in the servo field necessary for proper operation of the read channel.

The determination in the peak detection subsystem of Figure 1 that a qualified two-sided peak sample digitized absolute value has been identified, or that a sample digitized absolute value has saturated the maximum absolute value available in operation block 16, is indicative of the gain of variable gain amplifier 13' being satisfactorily adjusted by the gain control subsystem of Figure 2A. Thus, a binary "1" value indicator of the occurrence of either of these conditions is provided on terminal 85 of the gain control subsystem of Figure 2 A after the binary "1" value indicator of a specific one of these conditions on subsystem outputs 50 and 19 in the peak detection subsystem of Figure 1 has been provided to the corresponding input of OR logic gate 84 of Figure 2 A. Finally, any signals supplied by the system controller, not shown, indicating that a gain error signal value is not to be used in providing a corresponding "weighted" value addition to the accumulated total of such values in gain control delay register 124 of Figure 2 A will also result in the insertion of a current initial count value from register 180 into counter 182. In effect, counter 182 is reset when the system controller determines that a gain error signal value, otherwise available for adjusting the total in delay register 124, will not be used since this gain error value is not an indication of a gain setting value problem in variable gain amplifier 13 '. Such a "no problem" indicator signal is provided at output terminal 73 of the gain control subsystem of Figure 2A as the result of any such signal being provided from the system controller at any of input terminals 74, 75 and 76 of that subsystem which are provided to NOR logic gate 72. Because of the use of a NOR logic gate for logic gate 72, a NOT logic gate, 184, is connected between terminal 73 and the corresponding input of OR logic gate 183 as shown in Figure 2B. The nine bits at the outputs of counter 182 on the right side thereof are all supplied to a corresponding input of a further OR logic gate, 185. As a result, so long as there is any binary "1" values on any of the bit outputs of counter 182, the output of logic gate 185 will be a binary "1" value. A further NOT logic gate, 186, has its input connected to the output of OR logic gate 185, and so this circumstance leads to a binary "0" being provided at output terminal 83 which is also the input terminal mentioned above for the gain control subsystem of Figure 2A. Hence, only when counter 182 reaches a zero value so that there are binary "0" values on each of its bit outputs will there be a binary "0" value at the output of OR logic gate 185 to be complemented to a binary "1 " value by NOT logic gate 182. Such a binary "1 " value thus appears on terminal 183 to thereby force the addition of a "weighted" gain error signal value to the total in gain control delay register 124. The loading of an initial count value into counter 182, in one of the ways just described above, results in a binary "1" value appearing at the output of OR logic gate 185 as indicated. This value is supplied to an AND logic gate, 187, having an input thereof connected to the output of OR logic gate 185. The other input of AND logic gate 187 is connected to the output of another OR logic gate, 188. The system controller, not shown, provides a control signal over an interconnection, not shown, to an open terminal, 189, shown in Figure 2B. If that control signal has a binary "1" value, the output of OR logic gate 188 will also be a binary "1" value which is provided to the remaining input of AND logic gate 187. In this circumstance, the loading of an initial value from register 180 into the inputs of counter 182 will lead to the resulting binary "1" value at the output of OR logic gate 185 causing the output of AND logic gate 187 to change from a binary "0" value to a binary "1 " value. This binary "1" value at the output of gate 187 is provided to enable input E of counter 182 thereby initiating the counting operation of that counter. On the other hand, a binary "0" value from the system controller on terminal 189 will leave the output of OR logic gate 188 at a binary "0" value, absent the appearance of a binary "1" value on its other input, which output value will prevent a binary "1 " value from appearing at the output of AND logic gate 187 upon the appearance of a binary "1" value at the output of OR logic gate 185. Thus, there will be no binary "1" value supplied to enable input E of counter 182, and so counting in that counter cannot begin upon the appearance of a binary "1" value at the output of OR logic gate 185. However, the output of OR logic gate 183 is also connected to the reset input of a five-bit up counter, 190. Counter 190 starts counting upward from zero following every loading of a new initial count value into counter 182 as begun by the change from a binary "0" value to a binary "1 " value at the output of OR logic gate 183 which resets counter 190. Counter 190 , upon reaching a count value of 31, changes from a binary "0" value to a binary "1" value the output thereof for one sample clock period, and then returns to a zero count value to begin counting to 31 again. Concurrently, counter 190 also returns to providing a binary "0" value at its output which is connected to the remaining input of OR logic gate 188.

This binary "1" value at the output of counter 190 for a sample clock period leads to a binary "1 " value occurring at the output of logic gate 188 for that period and so at the input of AND logic gate 187 for that period. The resulting change at the output of logic gate 187 from a binary "0" value to a binary "1" value for that period thereby enables counter 182 to count down one count. After a further 32 counts in counter 190, counter 182 again counts down another count. Thus, the system controller, by providing either a binary "0" value or a binary "1 " value at terminal 189, can determine whether 32 additional sampling periods are added for each count in counter 182 to the time required to count down to zero in counter 182 to thereby multiply its count range by 32, or whether the output at terminal 83 of Figure 2B depends only on the time required to count down to zero in counter 182 without regard to counter 190.

Many of the control signals used to operate the gain control subsystem of Figure 2 A are also used to operate the read channel asymmetry compensation subsystem shown in the mixed block and logic gate diagram of

Figure 3. This subsystem is provided to compensate magnitude asymmetries occurring between pulses of opposite polarity in the read channel signal in which such pulses are due to the occurrence of magnetic transitions in the tracks of magnetic medium disc 10 that are encountered by the magnetoresistive sensor in arrangement 11 in generating the read channel input signal. Here again, because the characteristics of the read channel signal developed from the servo field data and the data field data can differ from one another due to their being recorded at different times under different conditions, the providing of signal asymmetry compensation for read channel signals is performed separately for signals based on each of those kinds of data.

The gain error signals at subsystem output interconnection 53 of the peak detection subsystem shown in Figure 1 provide the basis for operating the asymmetry compensation subsystem of Figure 3 in those instances where servo fields in magnetic medium disc 10 are rotating past the magnetoresistive sensor in arrangement 11. Thus, an extension of subsystem output interconnection 53 of Figure 1 is shown as a subsystem input interconnection 53 in Figure 3 leading to both the input of an algebraic sign negator, 199, and to a first input of a multiplexer, 200. Multiplexer 200 has a selection control input, 201 , and a remaining input to which the output of negator 199 is connected over a six digit line interconnection, 202. Providing a negative feedback effect in the asymmetry compensation loop requires the algebraic signs of these gain error signal values provided from register 20'" to subtractor 51 in Figure 1 form a negative signal gradient upon reaching multiplexer 200 as asymmetry error signals. Thus, the algebraic signs of these gain error signal values from subtractor 51 , when used to form these asymmetry error signals, are to have positive values when the sample digitized absolute values are less than the desired average magnitude value therefor, and negative values when the magnitudes of those samples are greater than the desired average value therefor.

Subsystem output terminal 17 of the peak detection subsystem of Figure 1 carries the sign bit of each sample digitized absolute values stored in register 20'" and used in subtractor 51 to form the current gain error value. As a result, a binary "1" value in the signal on terminal 17, indicating negative sample values in a 2's complement representation, causes multiplexer 200 to direct corresponding sample digitized absolute values on interconnection 53 having negative values directly through multiplexer 200 to a six digit line interconnection, 203, at the output thereof. However, a binary "0" value in the signal on terminal 17 causes multiplexer 200 to direct the sample digitized absolute values of a positive polarity on interconnection 53 to interconnection 203 only after being received therein over interconnection 202 following the polarity thereof having been made negative in negator 199. These negative gradient signal values on interconnection 203 form the servo field asymmetry error signal. Similarly prepared gain error signal values based on the read channel signal developed when a data field in magnetic medium disc 10 is being rotated past the magnetoresistive sensor in arrangement 11 are provided on a six digit line interconnection, 204, from the controller arrangement for read channel estimation and control. These negative gradient signal values on interconnection 204 form the data field asymmetry error signal, and this signal is provided to a first input of a further multiplexer, 205, having a further six digit line interconnection, 206, connected to the output thereof. The servo field asymmetry error signal on interconnection 203 is provided to the remaining input of multiplexer 205. The servo field indicator signal on subsystem input terminal 64 of the gain control subsystem of Figure 2 A, after being delayed by two sample clock periods, becomes the delayed servo field indicator signal appearing on subsystem output 67 of that subsystem, as described above. An extension of subsystem output 67 of Figure 2A is shown as a subsystem input interconnection 67 in Figure 3 leading to a selection control input, 207, of multiplexer 205. As a result, the data field asymmetry errors on interconnection 204 are directed to interconnection 206 at the output of multiplexer 205 whenever a servo field in magnetic medium disc 10 is not being rotated past the magnetoresistive sensor in arrangement 11 leaving the signal on terminal 67 with a binary "0" value. When there is such a rotation of a servo field past the sensor so the signal on terminal 67 has a binary "1" value, the servo field asymmetry errors, provided on interconnection 203 to the remaining input of multiplexer 205, appear on interconnection 206 at the output of that multiplexer.

However, again, only selected ones of either of the data field asymmetry errors or the servo field asymmetry errors are allowed to reach the subsequent asymmetry compensation accumulator for use in determining the asymmetry compensation value generated therein for asymmetry compensator 13". Whichever of the data field asymmetry error signal and the servo field asymmetry error signal that is directed by multiplexer 205 to occur on interconnection 206 also appears at a first input of a further multiplexer, 208. The other input of multiplexer 208 is connected to a zero value as is indicated by the open terminal thereat. Thus, signals provided at a selection control input, 209, of multiplexer 208 determine whether a value, in whichever of the data field asymmetry error signal and the servo field asymmetry error signal appears on interconnection 206 to reach the first input of multiplexer 208, further reaches another six digit line interconnection, 210, to go on to the asymmetry compensation accumulator. In the absence of a binary "1" value at selection control input 209 of multiplexer 208 allowing such a value presented on interconnection 206 to reach the output of multiplexer 208 and interconnection 210, a zero value is substituted in place of that error value which then appears instead on interconnection 210.

A single digit line interconnection, 211, is provided to selection control input 209 of multiplexer 208, and extends from the output of a further multiplexer, 212. Multiplexer 212 has a first input to which a data field asymmetry error selection signal is provided by the system controller arrangement for data field estimation and control, not shown, on an interconnection extending therefrom, not shown, to a subsystem input open terminal, 213, connected to first input. The output of an AND logic gate, 214, is connected to the remaining input of multiplexer 212. A selection control input, 215, of multiplexer 212 is connected to subsystem input terminal 67 to receive the delayed servo field indicator signal from the gain control subsystem of Figure 2A. As a result, when a servo field in magnetic medium disc 10 is not being rotated past the magnetoresistive sensor in arrangement 11 , a binary "0" value is provided on selection control input 215 of multiplexer 212 to result in the signal on terminal 213 being directed by multiplexer 212 over interconnection 211 to selection control input 209 of multiplexer 208. In this circumstance, the provision of a binary "1" value on terminal 213 results in having multiplexer 208 direct a corresponding data field asymmetry error value provided on interconnection 206 to interconnection 210 at the output thereof. In the absence of a binary " 1 " value in the signal at terminal 213, zero values are directed by multiplexer 208 to interconnection 210.

When a binary "1" value occurs in the delayed servo field indicator signal provided on terminal 67, indicating a servo field in disc 10 as being rotated past the magnetoresistive sensor, multiplex er212 directs signals provided to it by AND logic gate 214 to selection control input 209 of multiplexer 208. A binary "1" value from logic gate 214 will result in the corresponding servo field asymmetry error value on interconnection 206 presented to multiplexer 208 appearing on interconnection 210 at the output thereof. A binary "0" value at the output of logic gate 214 directed to selection control input 209 by multiplexer 212 will result in a zero value being substituted by multiplexer 208 for the data field asymmetry error value presented thereto on interconnection 206 which zero value then appears on interconnection 210.

A binary "0" value appears at the output of AND logic gate 214 in the absence of the occurrence of a binary "1 " value at each input thereof. The first input to AND logic gate 214 is a control signal provided by the system controller, not shown, over an interconnection extending therefrom, also not shown, to an open input terminal, 216 in Figure 3. Thus, the system controller permits servo field asymmetry error values presented on interconnection 206 to be directed by multiplexer 208 to interconnection 210 by providing a binary " 1 " value at terminal 213. However, such permitted servo field asymmetry error values must also be associated with the occurrence of a qualified two-sided peak sample digitized absolute value as indicated by a binary "1 " value in the signal provided at subsystem output 50 of the peak detection system shown in Figure 1. Thus, an extension of subsystem output interconnection 50 of Figure 1 is shown as a subsystem input interconnection 50 in Figure 3 leading to an input to AND logic gate 214.

Furthermore, there must not be possible error problems due to thermal asperities or other system controller reasons to thereby prevent updating of the servo asymmetry error compensation value in the subsequent asymmetry compensation accumulator. Hence, the signal at the output of NOR logic gate 72 in Figure 2 A must be at a binary "1" value resulting in such a value appearing at subsystem output 73 of the gain control subsystem shown in Figure 2 A. An extension of subsystem output interconnection 73 of Figure 2 A is shown as a subsystem input interconnection 73 in Figure 3 also leading to an input of AND logic gate 24, and the signal thereon will be a binary "1" value in the absence of any signals having a binary "1" value at subsystem input terminals 74, 75 and 76 of the gain control subsystem shown in Figure 2A indicating the detection of such a problem or such other reasons. The data field asymmetry error gradient values and the servo field asymmetry error gradient values provided on interconnection 210 are also "weighted" by "weighting" factors selected by the system controller, not shown. The system controller provides a positive "weighting" factor for multiplying the selected servo field asymmetry error values on a three digit line interconnection extending therefrom, not shown, except for a portion, 217, shown in Figure 3. Similarly, the system controller provides a positive "weighting" factor for multiplying the selected data field asymmetry error values on a further three digit line interconnection extending therefrom shown only in part, 218, in Figure 3. Positive factors can be used for this purpose as the negative gradient values are already formed.

The "weighting" factors on interconnections 217 and 218 are provided to the inputs of a multiplexer, 219, which directs either the servo field asymmetry error values factor or the data field asymmetry error values factor to an interconnection, 220, at the output thereof under the control of signals provided at a selection control input, 221, thereof. Selection control input 221 of multiplexer 219 is connected to terminal 67 to receive the delayed servo field indicator signal. A delayed servo field indicator signal having a binary "0" value results in the "weighting" factor for read field asymmetry errors appearing on interconnection 220, and a binary "1" value in the delayed servo field indicator signal, indicating a servo field is being rotated past the magnetoresistive sensor, results in the "weighting" factor for servo field asymmetry errors appearing on interconnection 220. Each of interconnections 217 and 218 allow multiplicative factors with values between 0 and 8. The value of a multiplier is chosen by the system controller is again based on balancing the need for sufficiently rapid acting control loop to adjust the gain of the variable gain amplifier versus the need for stability of that loop and for stability of its interactions with other loops affecting the read channel signal such as the gain control loop described above. Typically, the loop gain for the asymmetry compensation subsystem will be relatively low as the sources of asymmetry errors change characteristics only relatively slowly. This lower loop bandwidth significantly reduces the risk of instability due to interactions between the gain control and the asymmetry compensation loops.

The remaining portion of the asymmetry compensation subsystem shown in Figure 3 for providing compensation values to use in asymmetry compensator 13" operates in the same manner as the corresponding portion of the gain control subsystem shown in Figure 2A as those portions of each subsystem share the same diagrammatic topology. Furthermore, the same control signals are used to operate these portions of each subsystem. Thus, the asymmetry compensation accumulator provides analog asymmetry compensation values for both servo field based and data field based pulses in the read channel signal in the same manner as the gain control subsystem provides gain setting values. The asymmetry compensation accumulator also provides initial values for such servo and data field based compensation values based on either the stored value from the previous such field encountered by the magnetoresistive sensor or on values inserted by the system controller. As a result, the operation and components of the remaining portion of the subsystem shown in Figure 3 will not be again described. The description can be obtained from the description of the corresponding portion of the gain control subsystem of Figure 2A which can be conveniently followed for the subsystem portion shown in Figure 3 because the components in this latter portion carry the same numerical designations as they do in the corresponding portion of subsystem shown in Figure 2 A except for the addition of a prime symbol thereafter.

The magnetoresistive head, or "read head", lateral positioning feedback loop is operated by an error signal developed from magnitude-time areas of pulses resulting from zones extending in succession along the track in the lateral positioning portion of the servo field as described above. These zones are provided in a four or six zone pattern involving the zones in various lateral positions with respect to that track in which pattern the zones are designated A, B, C and D, or A, B, C, D, E and F, in succession. The magnitude-time areas of the pulses generated in a zone, or part of a zone, are obtained by summing the sample digitized absolute values provided in single sample clock period delay register 23 in the peak detection subsystem shown in Figure 1 over some portion or all of the zone currently passing the magnetoresistive head in arrangement 11. That is, the sample digitized absolute values at subsystem output interconnection 23 of the peak detection subsystem shown in Figure 1 provide the basis for operating the "read head" lateral positioning feedback loop error signal generator of Figure 4 when servo fields in magnetic medium disc 10 are rotating past the magnetoresistive sensor in arrangement 11. Thus, an extension of subsystem output interconnection 23 of Figure 1 is shown as a subsystem input interconnection 23 in Figure 4 leading to both the input of an algebraic sign negator, 240, and to a first input of a multiplexer, 241. Multiplexer 241 has a selection control input, 242, and a remaining input to which the output of negator 240 is connected over a five digit line interconnection, 243. Control signals provided at selection control input 242 determine whether multiplexer 241 directs the sample digitized absolute values obtained from peak detection subsystem output terminal 23 directly onto a further five digit line interconnection, 244, at its output or the negative of such values onto interconnection 244.

These control signals are supplied by a sequencer, 245. Sequencer 245 receives control signals from the system controller, not shown, on three inputs thereof. The system controller provides the first of these on an interconnection extending therefrom, not shown, to an open terminal, 246, connected to a sequencer input, a zone start indicator signal for each zone encountered along the servo field track by that signal changing from a binary "0" value to a binary "1 " value at the start of a new zone, and back to a binary "0" value at the end of the zone. Further, the system controller provides on an interconnection extending therefrom, not shown, to an open terminal, 247, also connected to a sequencer input, a sequencer reset signal following each zone completing its rotation past the magnetoresistive sensor. This resets a sampling clock driven counter in sequencer 245 that sets by its count-out value the number of those samples are taken during the rotating of a zone past the sensor that are to be used in determining the magnitude-time area measured for that zone. The count-out value for this counter is selected and provided by the system controller on an interconnection extending therefrom, not shown, to an open terminal, 248, connected to another sequencer input. A further single digit line interconnection, 249, extends between an output of sequencer 245 and selection control input 242 of multiplexer 241. Sequencer 245 over this interconnection provides control signals to multiplexer 241 to direct the sample digitized absolute values taken to used from a first zone member of a corresponding pair of zones onto interconnection 244 at its output. Thereafter, sequencer 245 over this interconnection provides control signals to multiplexer 241 to direct the sample digitized absolute values taken to used from the second zone member of such a corresponding pair of zones onto interconnection 244 at its output only after having those values negated in negator 240. Thus, sample digitized absolute values obtained based on a zone A are provided directly onto interconnection 244 by multiplexer 241 , but sample digitized absolute values obtained based on a zone B are acted on by negator 240 before being provided onto interconnection 244. This selection relationship is followed also for zones C and D, respectively, and for zones E and F, respectively (if provided). The sample digitized absolute values, or negated sample digitized absolute values, provided on interconnection 244 are provided to a lateral positioning error accumulator comprising an adder, 250, having a twelve digit line interconnection, 251 , at an output thereof connected to an input of a further multiplexer, 252. A further twelve digit line interconnection, 253, at the output of multiplexer 252 is connected to the input of a single sample clock period delay register, 254, serving as the lateral positioning error accumulator register. A final twelve digit line interconnection, 255, for this accumulator at the output of register 254 connects that output to another input of multiplexer 252 and to another input of adder 250. Multiplexer 252 has a further input connected to a zero value as shown by the open terminal connection at that input, and a selection control input, 256. A two digit line interconnection, 257, connects an output of sequencer 245 to selection control input 256. The zone start indicator signal on terminal 246, indicating the start of zone A rotating past the magnetoresistive sensor, results in sequencer 245 providing a control signal on interconnection 249 at selection control input 242 of multiplexer 241 that causes multiplexer 241 to direct sample digitized absolute values on interconnection 23 to interconnection 244 at the output thereof. Furthermore, this zone start indicator signal causes sequencer 245 to provide a control signal on interconnection 257 to selection control input 256 of multiplexer 252 that results in multiplexer 252 directing the initial acceptance of a zero value at the zero value input of that multiplexer for provision on interconnection 253 at the output thereof, and so provided to lateral positioning error accumulator register 254 to clear that register.

Once cleared, a further control signal provided thereafter by sequencer 245 on interconnection 257 results in multiplexer 252 directing acceptance of signals at the input thereof connected to interconnection 251 that represent the results of adding, in adder 250, the direct sample digitized absolute values on interconnection 244 to the preceding total thereof in register 254. Each new total is directed, as a result of this control signal, by multiplexer 252 to interconnection 253 for storage in lateral positioning error accumulator register 254. The number of direct sample digitized absolute values of the read channel signal portion due to zone A on interconnection 244 involved in this sum is equal to the count-out value selected by the system controller for the counter in sequencer 245, the magnitude-time area in the read channel signal portion for that zone is taken as that sum value times the number of sample clock periods involved with those samples. The resulting sum of adding together all of these values is effectively held in register 254 of the accumulator through sequencer 245 providing a further control signal in interconnection 257 to multiplexer 252 causing multiplexer 252 to direct the acceptance of the sum value on interconnection 255 connected to the output of register 254. As a result, the value in register 254 continues to recirculate through multiplexer 252 to register 254 so as to be continually held in that register.

Interconnection 255 also extends to the signal inputs of three further 12-bit storage registers, 258, 259 and 260. As a result, the sum value held in lateral positioning error accumulator register 254 is also provided to the inputs of each of these storage registers. However, the effective magnitude- time area enclosed by the read channel signal portion provided by the magnetic transitions in zone A represented by this sum value now stored in register 254 will be entered only into register 258 because sequencer 245 provides at this point a load signal only to register 258 on a further single digit line interconnection, 261, extending from the sequencer to a load and hold input thereof. A change in value on the control signal on interconnection 261 from binary "0" value to a binary "1" value causes the value on interconnection 255 at the input of register 258 to be loaded therein with the next sample clock signal transition, and the return to a binary "0" value on interconnection 261 causes that value to be held in storage register 258 until the next occasion on which a new value is loaded into that register.

Thus, a binary "1" value introduced into the signal on interconnection 261 will cause the sum value on interconnection 255 to be loaded into register 258 on the next clock edge of the sampling clock signal. Similar single digit line interconnections, 262 and 263, are provided to the load and hold inputs of registers 259 and 260, respectively. Values stored in register 258 are thereafter available on a further interconnection, 264, at the output thereof. Similarly, values stored in register 259 and 260 are available at further interconnections, 265 and 266, at the outputs of those registers, respectively, after storage therein.

After the magnitude-time area due to zone A has been accumulated in register 254 and loaded into register 258, zone B will next be encountered by the magnetoresistive sensor in arrangement 11 the start of which will be indicated by another change to a binary "1" value in the zone start indicator signal on terminal 246. However, on this occasion, sequencer 245 provides a control signal on interconnection 249 to selection and control input 242 of multiplexer 241 resulting in that multiplexer now directing the acceptance of negated sample digitized absolute values on interconnection 243 to be provided on interconnection 244 at the output of multiplexer 241. Without any clearing of the magnitude-time area sum value for zone A stored in register 254, sequencer 245 provides a control signal on interconnection 257 resulting in multiplexer 252 directing acceptance of values on interconnection 251 to be provided on interconnection 253 at the output thereof for storage in register 254. Again, the number of samples taken from the read channel signal portion due to zone B is equal to the count-out value provided by the system controller to sequencer 245.

The accumulation of that number of sample digitized absolute values again represents the magnitude-time area for the read channel signal portion provided as a result of the magnetoresistive sensor encountering zone B. However, since the samples of that signal portion pass through negator 240, only the net difference between the effective magnitude-time area of the read channel signal portion due to zone A and that due to zone B will result in lateral positioning error accumulator register 254. That net difference is representative of the error in the lateral position of the "read" head along the servo field portion of the current track as measured by those two zones, A and B. This net difference is next loaded into register 258 by a control signal appearing on interconnection 261 to overwrite the effective magnitude-time area due to zone A previously stored therein.

The same process is repeated for zones C and D with the net difference result being stored in register 259. Finally, the net difference due to zones E and F (if used) is stored in register 260. These net differences in register 258, 259 and 260 are used by the "read head" lateral positioning feedback loop as error signals in the lateral positioning of that head along the track.

Error signals for feedback loops need fine resolution, however, to provide close control of the read head lateral position. The magnitude resolution of five bits in the samples digitized absolute values used in forming these error signals at a minimum sampling rate for loop signals would be insufficient to provide the needed resolution in the error signal for the operation of this feedback loop because of the resulting relatively large quantization error or noise. Thus, oversampling is used as described above to the extent of being sixteen times the fundamental frequency of the repetition period for the magnetic transition based pulse rate in the read channel signal. This oversampling provides enough spreading out of the quantization noise along the frequency axis to give a sufficient signal-to-noise ratio equivalent to that which would be achieved by ten bits of resolution in the measurement of the sample digitized absolute values at the minimum sampling rate.

The system controller, not shown, needs to obtain information concerning occurrences of two-sided peak values in samples taken of the servo field based read channel signal indicating a pulse peak in that signal, and the corresponding polarity of that peak value, for use in its various operations. The peak occurrence and polarity subsystem shown in the logic diagram of Figure 5 A provides alternative capabilities, as will be described below, for indicating to the system controller that a two-sided peak sample digitized absolute value has been detected in the servo field based read channel signal, and the polarity of that sample.

The polarity information for samples of the servo field based read channel signal are provided on subsystem output 17 of the peak detection subsystem of Figure 1. An extension of subsystem output 17 of Figure 1 is shown as a subsystem input interconnection 17' in Figure 5 A, following the complementing of that signal (not shown). Input interconnection 17' is connected to an input of a NOT logic gate, 269, to the signal input of a storage register, 270, and finally to an input of an AND logic gate, 271. A two-sided peak indicator signal appears on subsystem output 50 in the peak detection subsystem of Figure 1 , an extension of subsystem output 50 of Figure 1 is shown as subsystem input interconnection 50 in Figure 5 A leading to the load and hold control input of register 270, and to a second input of AND logic gate 271, and to an input of a further AND logic gate, 273, and finally to an input of a single sample clock period delay storage register, 274.

Two different control signals are supplied to the subsystem of Figure 5A from the system controller, not shown, on two further inputs thereof. The system controller provides the first of these signals on an interconnection extending therefrom, not shown, to an open terminal, 275, which is an output type selection control signal indicating in which of two alternative output signal forms the system controller has chosen to receive indications of occurrences of two-sided peaks and corresponding polarities. In the first output form, a binary "0" value in the output type selection signal on terminal 275, upon the occurrence of a two-sided peak value, results in an indication on a first subsystem output, 276, that a positive polarity two-sided peak has occurred, or an indication instead on a second subsystem output, 277, that a negative polarity two-sided peak has occurred. In the alternative output form for a binary "1" value in the output type selection signal on terminal 275, the subsystem of Figure 5A provides an indication on output 276 of the polarity of any two-sided peak that occurs, and an indication on output 277 that such a two-sided peak has occurred. Thus, in this second form, the occurrence of a peak value and its polarity are separately indicated by the two output signals, but the switching rate to indicate peak occurrences in each output signal is twice as rapid as is needed in the first output form because every peak is indicated rather than just those of one polarity.

The system controller provides the other of these two control signals on an interconnection extending therefrom, not shown, to an open terminal, 278, in Figure 5 A which is a two-sided peak indicator duration control signal. That is, the occurrence of a two-sided peak value indicating a pulse peak in the servo field based read channel signal can be indicated to the system controller for either of two selected durations as specified by the system controller. In particular, occurrences of a two-sided peak values can be indicated by output pulse signals on the subsystem outputs that are either of a two sample clock period duration if a binary "0" value appears on terminal 278, or of a four sample clock period duration if a binary "1" value appears on terminal 278.

In a first operating situation, the output type selection control signal on terminal 275 has a binary "1" value. As a result, the output signal form for an indication of the occurrence of a two-sided peak sample digitized absolute value, and its polarity, is a polarity indication signal on subsystem output 276 and a separate two-sided peak occurrence indication signal on subsystem output 277. In addition, the two-sided peak indicator duration control signal on terminal 278 will be taken in this situation to have a binary "0" value so that the two-sided peak occurrence indication signal provided on an output 277 will be a two sample clock period duration pulse. The polarities of the sequence of sample digitized absolute values provided by operational block 16 in the peak detection subsystem of Figure 1 are provided in a corresponding succession by the sign bits of the corresponding member values of the sample digitized values sequence generated by the sampler and analog-to-digital converter of signal block 13 in Figure 1. This succession of sign bits, after delays in registers 14, 15, 15', 15" and 15'", forms the sign bit indicator signal on terminal 17 of the Figure 1 peak detection subsystem which, after being complemented, is provided to terminal 17 ' and then to storage register 270 in the subsystem of Figure 5 A.

However, only those complemented sign bit values from the sign bit indicator signal are stored in register 270 that are concurrent with the receipt of an enabling signal on the load/hold input thereof, and then are stored only on the occurrence of the next sample clock signal pulse. Since the load/hold input of register 270 is connected to terminal 50, such an enabling control signal only occurs upon the identification of a qualified two-sided peak value among the sample digitized absolute values in the sequence thereof. As a result, the output of register 270 provides a binary value indicative of the polarity of the last qualified two-sided peak value to occur among the sample digitized absolute values in the succession thereof, and this value is provided at the output thereof on a single digit line interconnection, 279, extending to an input of a multiplexer, 280. A sign bit value loaded into register 270 is maintained therein until the occurrence of a next complemented sign bit that is loaded therein upon the identification of another qualified two-sided peak value in the sample digitized values provided by block 13 through delay register 14 in Figure 1. The binary "1" value on input terminal 275 is provided to a selection control input, 281, of multiplexer 280 to result in having multiplexer 280 direct the signal on interconnection 279 to a further interconnection, 282, at the output thereof. The value on interconnection 282 is provided to the input of a single clock period delay storage register, 283, and then, after a clock period delay, to subsystem output 276 as the bit polarity indicator signal. This subsystem output signal has a value representing the complement of the sign bit of the qualified two-sided peak value last identified among the sample digitized values taken of the read channel signal. Figures 5B and 5C show signal timing diagrams representing the operation of the subsystem shown in Figure 5 A with the uppermost waveform, 284, in each representing the clock signal for the sampler in block 13. The next waveform therebelow in each of these diagrams represents the polarity of the sample digitized absolute values obtained from the read channel signal after the above mentioned delays, i.e. the complemented sign bit indicator signal on subsystem input terminal 17' where this numerical designation for the terminal is also used in these diagrams for the waveform of the signal occurring thereon. The waveforms shown for the signal on terminal 17' is for an assumed series of alternating polarity magnetic transition based pulses in that read channel signal. The next waveform down in each diagram represents the signal indicating identifications of corresponding qualified two-sided peak values for the read channel magnetic transition based pulses having the polarity shown in the waveform immediately above. That is, the third waveform down in each diagram is the qualified two-sided peak indicator signal on subsystem input terminal 50. Note that the one clock period long binary "1 " value pulses each indicating the occurrence of a two-sided peak value are separated by different time durations characteristic of the variation in time occurring in the detection of the peak value location. The waveform below the waveform representing the qualified two-sided peak indicator signal on subsystem input terminal 50 in each diagram is the polarity indication signal on subsystem output terminal 276 indicating the polarity of the sample that was last determined to be a qualified two-sided peak value for that output signal form selected for the indication of occurrences of two-sided peak sample digitized absolute values in the present situation. This waveform is the signal appearing on interconnection 279 at the output of register 270 after a single sample clock period delay in register 283. As indicated above, the complemented sign bit provided on subsystem terminal 17', corresponding to a two-sided peak sample digitized absolute value, is stored in register 270 during the sample clock period over which the corresponding binary "1" value pulse in the qualified two-sided peak indicator signal on terminal 50 occurs to be held therein until the next such indicator signal. After storage in register 270, a further sample clock period passes due to storage in register 283 before a corresponding binary value change occurs on output 276 to indicate the polarity of the just identified two-sided peak sample.

A positive sign bit, i.e. a binary "0" value in a 2's complement representation, leads to a complemented binary "1 " value on subsystem terminal 17' and the concurrent occurrence of a binary "1" value pulse in the qualified two-sided peak indicator signal on terminal 50 results in a binary "1" value at the output of AND logic gate 271 following the logic of that gate. This result has no effect on the signal value at output 276 as the signal path through the logic diagram of Figure 5 A from the output of logic gate 271 to output 276 passes through only the input of multiplexer 280 not selected by the control signal on selection control input 281 thereof. Such a situation also leads to the output of AND logic gate 273 being at a binary "0" value because of the provision of such a complemented sign bit on terminal 17' to the input of NOT logic gate 269. Furthermore, the output of AND logic gate 273 is provided on a single digit line interconnection, 285, to a further multiplexer, 286. Subsystem input terminal 275 is connected to a selection control input, 287, of multiplexer 286, and the binary "1" value thereon in the present situation results in multiplexer 286 directing the other input of multiplexer 286 be connected to a further single digit line interconnection, 288, at the output thereof. This other input of multiplexer 286 has a further single digit line interconnection, 289, extending from the output of single sample clock period delay register 274 to that input thereof. Thus, each binary "1" value pulse provided on terminal 50 for a single sample clock period, indicating that a qualified two-sided peak value has been identified, is, after a single sample clock period delay in register 274, directed by multiplexer 286 from interconnection 289 at the input thereof to interconnection 288 at the output thereof. Delay register 274 provides a delay for a qualified two-sided peak value indicator binary "1" value pulse to match the delay in register 270 for storage therein of the corresponding polarity indicator to thereby maintain the relative timing of these two indicators to meet the relationship expected by the system controller for receiving peak and polarity information in the present output signal form.

A binary "1" value pulse on interconnection 288 from terminal 50 through multiplexer 286, corresponding to the occurrence of a two-sided peak value, reaches a further single sample clock period delay register, 290, which, after the delay provided thereby, results in a binary "1" value pulse appearing on a further single digit line interconnection, 291, at the output thereof. A binary "0" value is then introduced in register 274 from terminal 50 as the binary "1" value pulse thereon ends. Interconnection 291 passes the binary "1" value pulse thereon to a further single sample clock period delay register, 292, and to an input of an OR logic gate, 293, leaving a binary "0" value in register 290 from register 274 through multiplexer 286. As a result, a binary " 1 " value appears at the output of logic gate 293 following the logic of that gate which is provided on a further interconnection, 294, to an input of an EXCLUSFVE-OR logic gate, 295. Because of the binary "1" value in the present situation in the control signal provided on subsystem input terminal 275 connected to the other input of logic gate 295, the output of logic gate 295 has been a binary "1" value heretofore in view of the output of logic gate 293 having previously been a binary "0" value. The binary "1" value subsequently appearing on the output of logic gate 293 because of the binary "1" value pulse on terminal 50, as just described, therefore causes the output of logic gate 295 to change to a binary "0" value which appears on a further interconnection, 296, connected thereto and to the input of a further single sample clock period delay register, 297. The output of register 297 is subsystem output 277.

The fifth waveform down in the diagrams of Figures 5B and 5C, following the waveform for the polarity indication signal on subsystem output terminal 276, is the two-sided peak occurrence signal on subsystem output 277 in the present situation. Thus, as can be seen in Figures 5B and 5C, three sample clock periods following the initiation of each binary "1" value pulse shown in the waveform representing the signal on subsystem terminal 50, the waveform for subsystem output 277 shows a change from a binary " 1 " value to a binary "0" value. The three sample period clock delays are those due to delay registers 274, 290 and 297. These two-sided peak indicator pulses on terminal 277 can be converted from a binary "0" value indicator pulse to a binary "1 "value indicator pulse by merely omitting EXCLUSIVE-OR logic gate 295 and, instead, connecting the output of OR logic gate 293 directly to the input of delay register 297.

The binary "1" value stored in register 292 from terminal 50 through multiplexer 286,as described above, is provided, after a single sample clock delay period in that register, on a further interconnection, 298, connected to the output thereof. Register 292 thereafter stores a binary "0" value therein received from register 290 over interconnection 291. Interconnection 298 is connected to the input of a further single sample clock period delay register, 299, and to another input of OR logic gate 293. As a result, the output of logic gate 293 is kept at a binary "1 " value by the binary "1 " value in register 299 for a succeeding sample clock period, and so causes the subsystem output 277 to remain at a binary "0" value for this succeeding sample clock period on the same basis as described above for output 277 initially changing to a binary "0" value. The binary "1 " value stored in single sample clock period delay register 299 is then provided on a further interconnection, 300, connected to the output thereof leaving a binary "0" value stored therein received from register 292. This binary "1" value on interconnection 300 reaches a further single sample clock period delay register, 301, and an input of another OR logic gate, 302. This gate input value change results in the output of logic gate 302 changing from a binary "0" value to a binary "1" value which output value is provided on a further interconnection, 303, connected to the output thereof, to reach the input of an AND logic gate, 304. However, the other input of logic gate 304 is connected to subsystem input terminal 278 which has a control signal with a binary "0" value thereon in the present situation as indicated above. As a result, the output of logic gate 304 remains at a binary "0" value.

Hence, the shift of the binary "1 " value pulse in delay register 299 to delay register 301 results in the output of OR logic gate 293 returning from a binary "1" value to a binary "0" value so that the output of EXCLUSIVE-OR logic gate 295 returns to a binary "1 " value. Thus, after two sample clock delay periods, output 277 returns to a binary "1" value as can be seen for the output 277 waveform in Figure 5B. Therefore, a two sample clock period binary "0" pulse on output 277 has been provided to indicate the occurrence of a qualified two-sided peak having been identified in the read channel signal. As stated above, such two-sided peak indicator pulses on terminal 277 can be converted from a binary "0" value indicator pulse to a binary "1 "value indicator pulse by removing EXCLUSIVE-OR logic gate 295 and, instead, connecting the output of OR logic gate 293 directly to the input of delay register 297.

Changing to a new situation by having the control signal value provided on terminal 278 be a binary "1" value to indicate that a four sample clock period indication pulse has been chosen by the system controller to be provided at output 277 as a two-sided peak value occurrence indicator alters the operational sequence just described above. The storing of a binary "1" value in register 299 due to a binary "1" pulse value on terminal 50, as described above, along with there now being a binary "1 " value on terminal 278, leads to a binary "1" value appearing at the output of AND logic gate 304 rather than a binary "0" value as before. This binary "1 " value appears on a further interconnection, 305 , connected to the output of gate 304, to reach a further input of OR logic gate 293 to which it is also connected.

As a result of this binary "1" value on the input of gate 293, a binary "1" value appears at the output of that gate for two further sample clock delay periods. This result is due to the storing of a binary "1" value in register 299 for one sample clock period which is passed over interconnection 300 to gates 302 and 304 to gate 293, and the passing of that same value over that interconnection for storage in register 301 for a further sample clock period. This value stored in register 301 is passed in that further sample clock period again over interconnection 300 to gates 302 and 304 to gate 293. As a result, as can be seen in Figure 5C, the subsystem output 277 waveform has a four sample clock period binary "0" pulse therein three sample clock periods after the start of each binary "1" value pulse in the signal on subsystem terminal 50. The alternative form of output indications in the subsystem of Figure 5A provides a pulse indication on subsystem output 276 for the occurrence of a positive polarity qualified two-sided peak value and a pulse indication on subsystem output 277 for the occurrence of a negative polarity qualified two-sided peak. This alternative output indication form is selected by the system controller providing a binary "0" value on subsystem input terminal 275. As a result, multiplexer 286 will direct signals on its input from AND logic gate 273 over interconnection 285 to interconnection 288 at the output thereof rather than directing signals on its input from register 274 over interconnection 289 to its output. For the same reason, multiplexer 280 will direct signals on its opposite input to interconnection 282 at the output thereof rather than directing signals on its input from register 270 over interconnection 279 to its output.

In a first instance, a negative polarity sample digitized absolute value will lead to a binary "0" value being provided on complemented subsystem input terminal 17', and so on an input of AND logic gate 271 resulting in a binary "0" value on its output. Also, this binary "0" value on terminal 17 ' will result in binary "1" value at the output of NOT logic gate 269, and so at one of the inputs of AND logic gate 273. In this circumstance, a binary "1" value pulse on subsystem terminal 50, corresponding to the occurrence of a two-sided peak value, will provide a binary " 1 " value pulse on the other input of AND logic gate 273 which will lead to a binary "1" value pulse at the output of gate 273 and at the input of multiplexer 286 over interconnection 285. This binary " 1 " value pulse will be directed by multiplexer 286 to interconnection 288 at the output thereof because of the binary "0" value on selection control input 287 thereof from terminal 275.

Such a binary "1" value pulse on interconnection 288 results in the same behavior of the logic subsystem portion between interconnection 288 and subsystem output 277 as did a binary 'T'pulse on interconnection 288 from interconnection 289, as described above, except for complementing the signal on out 277 because of the binary "0" value now on the input of EXCLUSTVE- OR logic gate connected to subsystem input terminal 275. The resulting signal is designated 277' in Figures 5B and 5C , and can be seen to be a complemented version of the signal designated 277 in those figures but with the binary "1" value pulses therein starting one sample clock period earlier than the binary "0" value pulses in the signal designated 277 since the signal designated 277' is generated without use of delay register 274.

Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.

Claims

CLATMS:

1. A digital peak value detection system for detecting relative peak values of either polarity among a succession of member values forming a digitized values sequence, said system comprising: a magnitude determiner for receiving said digitized values sequence at an input thereof and providing a succession of member values at an output thereof representing magnitudes of corresponding member values of said digitized values sequence to thereby form a digitized single polarity values sequence; a comparator tapped delay line having a plurality of storage registers each of which has an input and an output, an initial storage register having an input serving as said comparator tapped delay line input and a last storage register having an output serving as said comparator tapped delay line output, said plurality of storage registers each having a said output thereof electrically connected at a line junction to an input of a succeeding one of said storage registers excluding said last storage register, said comparator tapped delay line input being coupled to said magnitude determiner output; a plurality of digitized value comparators each having a compare input which is coupled to said magnitude determiner output, and each having a reference input which is coupled to a corresponding one of said line junctions in said comparator tapped delay line, and each having an output, said plurality of digitized value comparators each having said output thereof in one of two states depending on whether a digitized value at said compare input thereof is greater or lesser than a digitized value concurrently at said reference input thereof; a response collection logic gate having a plurality of inputs each of which is coupled to a corresponding one of said outputs of said digitized value comparators and having an output, said response collection logic gate having said output thereof in one state for each of said inputs thereof being in a common state, and in another state for said inputs thereof being in another common state or in differing states; and an intermixed logic delay line having a plurality of logic gates each with first and second inputs and an output, and further having a plurality of storage registers each with an input and an output including an initial storage register having an input serving as said intermixed logic delay line input, each of said intermixed logic delay line storage registers having an output electrically connected to a said first input of a corresponding one of said plurality of intermixed logic delay line logic gates with each of those gates having an output thereof connected to an input of one of those storage registers excluding a last one thereof to result in a sequential interconnection of alternating ones of said intermixed logic delay line storage registers and logic gates, said collection response logic gate output being coupled to said intermixed logic delay line input and to a second input of each of said plurality of said intermixed logic delay line logic gates, said intermixed logic delay line logic gates each having said output thereof in one state for each of said first and second inputs thereof being in a common state, and in another state for said first and second inputs thereof being in another common state or in differing states.

2. The apparatus of claim 1 further comprising a plurality of response supplement logic gates each having a first input which is coupled to a said output of a corresponding one of said plurality of digitized value comparators and each having an output coupled to a corresponding one of said plurality of inputs of said response collection logic gate to thereby couple said output of a corresponding one of said plurality of digitized value comparators to a corresponding one of said plurality of inputs of said response collection logic gate, as aforesaid, said plurality of response supplement logic gates each having said output thereof in one state for any input thereof being in one state, and in another state for all of said inputs thereof being in a opposite state.

3 The apparatus of claim 1 further comprising a multiplier having a signal input coupled to said magnitude determiner output, and having a selection input, and having an output, and using said multiplier to provide member values at said output thereof equal to corresponding member values of said digitized single polarity values sequence each multiplied by a selected constant value chosen by signals provided at said selection input to thereby form a digitized multiplied values sequence; and still further comprising a sufficiency comparator having a compare input which is coupled to said multiplier output, and having a reference input which is coupled to said comparator tapped delay line output, and having an output, said sufficiency comparator output being in one of two states depending on whether a digitized value at said compare input thereof is greater or lesser than a digitized value concurrently at said reference input thereof.

4. The apparatus of claim 1 further comprising a source of threshold values selectively provided at an output thereof; and still further comprising a threshold comparator having a compare input which is coupled to said comparator tapped delay line output, and and having a reference input which is coupled to said source of threshold values output, and having an output, said threshold comparator being in one of two states depending on whether a digitized value at said compare input is greater or lesser than a digitized value concurrently at said reference input.

5. The apparatus of claim 1 wherein said digitized values sequence is obtained from an information retrieval signal based on a signal generated by a magnetic field sensor positioned adjacent to magnetic material supported on a disk in a magnetic data storage and retrieval system.

6. The apparatus of claim 2 wherein a two-sided peak occurrence indicator signal is formed at an output of said intermixed logic delay line and said apparatus further comprises: a sign determiner for receiving said digitized values sequence at an input thereof and providing member values at an output thereof representing polarities of corresponding member values of said digitized values sequence to thereby form a sign indicator values sequence; and a two-sided peak occurrence notifier having a pair of outputs and having a first input coupled to said intermixed logic delay line output, a second input coupled to said sign determiner output, and a format input to receive control signals directing whether a polarity indication should appear on one of said pair of outputs if a peak value is indicated in said two-sided peak occurrence indicator signal along with a peak indication appearing on that one remaining in said pair of outputs, or whether a peak and polarity indication for one polarity should appear on one of said pair of outputs if a peak value of one polarity is indicated in said two-sided peak occurrence indicator signal along with a peak and polarity indication for that other polarity appearing on that one remaining of said pair of outputs if a peak value of another polarity is indicated in said two-sided peak occurrence indicator signal.

The apparatus of claim 2 further comprising: a sign determiner for receiving said digitized values sequence at an input thereof and providing member values at an output thereof representing polarities of corresponding member values of said digitized values sequence to thereby form a sign indicator values sequence; a sign indicator tapped delay line having a plurality of storage registers each of which has an input and an output, an initial storage register having an input serving as said sign indicator tapped delay line input and a last storage register having an output serving as said sign indicator tapped delay line output, said plurality of storage registers each having a said output thereof electrically connected at a line junction to an input of a succeeding one of said storage registers excluding said last storage register, said sign indicator tapped delay line input being coupled to said sign determiner output; a plurality of difference determination logic gates each having an output, each having a first input which is coupled to an input of one of said plurality of storage registers in said sign indicator tapped delay line, and each having a second input which is coupled to said output of a corresponding one of said plurality of storage registers in said sign indicator tapped delay line, said plurality of difference determination logic gates each having said output thereof in one state for said inputs thereof being in differing states, and in another state for said inputs thereof being in a common state, said plurality of response supplement logic gates each having a second gate input which is coupled to a said output of a corresponding one of said plurality of difference determination logic gates; and a plurality of intermixed supplement response logic gates each having a first input which is coupled to an output of a corresponding one of said plurality of difference determination logic gates, and each having a second input which is coupled to said output of said response collection logic gate output, and each having an output which is coupled to a second input of a corresponding one of said plurality of said intermixed logic delay line logic gates to thereby couple said collection response logic gate output to said second input of each of said plurality of said intermixed logic delay line logic gates, as aforesaid, said plurality of intermixed response supplement logic gates each having said output thereof in one state for either of said first and second inputs thereof being in one state, and in another state for all of said first and second inputs thereof being in another common state.

8. The apparatus of claim 2 wherein at least some of said plurality of response supplement logic gates have a second input which is coupled to a source of control signals.

9. The apparatus of claim 6 wherein said signals on said format input also direct which of alternative time durations should be used in exhibiting a said peak indication.

10. A method of detecting relative peak values of either polarity among member values of a digitized values sequence, said method comprising: providing a digitized single polarity values sequence from said digitized values sequence; comparing each current member value of said digitized single polarity values sequence concurrently with a selected number of preceding member values thereof to determine which current member values of said digitized single polarity values sequence are one-sided peak values through exceeding in magnitude each of said selected number of preceding member values; providing, for said one-sided peak values so determined, a corresponding indicator signal value to an input of a storage line having a plurality of sequentially arranged value stores therein; comparing each said one-sided peak value sequentially with a selected number of subsequent member values of said digitized single polarity values sequence; and advancing said indicator signal value corresponding to each said one-sided peak value to that said value store next in sequence in said storage line for each successive determination of a said subsequent member value of said digitized single polarity values sequence corresponding to that said one-sided peak value being exceeded by that said one-sided peak value.

11. The method of claim 10 wherein said comparing of a said current member value of said digitized single polarity values sequence with said selected number of preceding member values thereof to determine occurrences of one-sided peaks is accomplished with a number of said preceding member values of said digitized single polarity values sequence that is selectively reduced from said selected number of said preceding member values thereof by selectively predetermining that such said current member values exceed one or more corresponding said preceding member values in said selected number thereof without regard as to whether that is so; and wherein comparing each said one-sided peak value sequentially with a selected number of subsequent member values of said digitized single polarity values sequence is accomplished with a number of said subsequent member values of said digitized single polarity values sequence that is selectively reduced from said selected number of said subsequent member values thereof by selectively predetermining that such said current member values exceed one or more corresponding said subsequent member values in said selected number thereof without regard as to whether that is so.

12. The method of claim 10 wherein said comparing ofa said current member value of said digitized single polarity values sequence with said selected number of preceding member values thereof to determine occurrences of one-sided peaks is accomplished with a number of said preceding member values of said digitized single polarity values sequence that is selectively reduced from said selected number of said preceding member values thereof by predetermining that such said current member values exceed any one or more corresponding said preceding member values in said selected number thereof having a polarity different therefrom without regard as to whether that is so.

13. The method of claim 10 further comprising multiplying each said current member value of said digitized single polarity values sequence by a selected constant to form member values ofa digitized multiplied single polarity values sequence, and comparing each said member value of said digitized multiplied single polarity values sequence with a corresponding selected one of said preceding member values in said digitized single polarity values sequence.

14. The method of claim 10 further comprising comparing each member value of said digitized single polarity values sequence with a selected threshold value.

15. The method of claim 10 further comprising forming a two-sided peak occurrence indicator signal at an output of said storage line from said indicator signal values advanced therethrough, and directing whether a polarity indication should appear on one of a pair of outputs if a said indicator value occurs in said two-sided peak occurrence indicator signal along with a peak indication appearing on that one remaining in said pair of outputs, or whether apeak and polarity indication for one polarity should appear on one of said pair of outputs if a said indicator value occurs in said two-sided peak occurrence indicator signal along with a peak and polarity indication for another polarity appearing on that one remaining in said pair of outputs.

16. The method of claim 10 wherein said digitized values sequence is obtained by sampling an information retrieval signal based on a signal generated by a magnetic field sensor positioned adjacent to magnetic material supported on a disk in a magnetic data storage and retrieval system.

17. The method of claim 15 further comprising directing which of alternative time durations should be used in exhibiting a said peak indication.

18. A method for selecting gain values for a variable gain amplifier to be applied to an input signal provided at an signal input thereof to result in an output signal therefrom provided at an output thereof, said variable gain amplifier having a gain control input at which gain control signals can be provided to select said gain values for said variable gain amplifier, said method comprising: sampling and digitizing said variable gain amplifier output signal at selected times to provide successive member values in a digitized values sequence; detecting those said member values in said digitized values sequence having locally maximal magnitudes as two- sided peak member values; determining deviations in magnitude of member values in said digitized values sequence from a desired value to provide successive member values in a digitized gain error values sequence; selecting those member values of said digitized gain error values sequence corresponding to said two-sided peak member values of said digitized values sequence for multiplication by a selected value to provide successive member values in a digitized weighted gain error values sequence; summing in succession each member value of said digitized weighted gain error values sequence with a current gain setting value from a gain setting value sequence to provide a corresponding current summed gain setting value as a next member value in a summed gain setting value sequence; selecting between said cuπent summed gain setting value and an initial gain setting value to provide a replacement gain setting value; storing said replacement gain setting value as a next said current gain setting value of, and member value in, said gain setting value sequence; coupling a representation of said current gain setting value to said gain control input of said variable gain amplifier; and providing a representation of a selected one of said current gain setting values for use selectively as a next said initial gain setting value.

19. The method of claim 18 further comprising providing a selected external value for use selectively as said initial gain setting value, and selecting between said representation ofa selected one of said current gain setting values and said selected external value to provide said initial gain setting value.

20. The method of claim 18 wherein said input signal provided at said variable gain amplifier can be provided by alternative first and second signal sources, and further comprising selecting said initial gain setting value to provide said replacement gain setting value at a beginning of an input signal provided at said variable gain input from said first source, and providing said representation of a said current gain setting value for use selectively as said initial gain setting value at an ending of providing said input signal to said variable gain amplifier from said first source.

21. The method of claim 18 further comprising selecting, after a selected time duration following a last detecting ofa said member value in said digitized values sequence as a two-sided peak member value, a member value of said digitized error values sequence for multiplication by a selected value to provide a member value in said digitized weighted eπor values sequence.

22. The method of claim 18 further comprising a method for selecting asymmetry compensation values for a signal asymmetry compensator to be applied to an input signal provided at an signal input thereof to result in an output signal therefrom provided at an output thereof, with said signal asymmetry compensator having an asymmetry control input at which asymmetry compensation control signals can be provided to select said asymmetry compensation values for said signal asymmetry compensator: - Ho using said deviations in magnitude after negating those of said deviations associated with member values in said digitized values sequence of one polarity to provide successive member values in a digitized asymmetry error values sequence; selecting those member values of said digitized asymmetry error values sequence coπesponding to said two-sided peak member values of said digitized values sequence for multiplication by a selected value to provide successive member values in a digitized weighted asymmetry error values sequence; summing in succession each member value of said digitized weighted asymmetry error values sequence with a current asymmetry compensation setting value from an asymmetry compensation setting value sequence to provide a corresponding current summed asymmetry compensation setting value as a next member value in a summed asymmetry compensation setting value sequence; selecting between said current summed asymmetry compensation setting value and an initial asymmetry compensation setting value to provide a replacement asymmetry compensation setting value; storing said replacement asymmetry compensation setting value as a next said current asymmetry compensation setting value of, and member value in, said asymmetry compensation setting value sequence; - I l l - coupling a representation of said current asymmetry compensation setting value to said asymmetry control input of said signal asymmetry compensator; and providing a representation of a selected one of said current asymmetry compensation setting values for use selectively as a next said initial asymmetry compensation setting value.

23. The method of claim 18 wherein said input signal is obtained from an information retrieval signal based on a signal generated by a magnetic field sensor positioned adjacent to magnetic material supported on a disk in a magnetic data storage and retrieval system.

24. The method of claim 22 further comprising providing a selected external value for use selectively as said initial asymmetry compensation setting value, and selecting between said representation ofa selected one of said current asymmetry compensation setting values and said selected external value to provide said initial asymmetry compensation setting value.

25. The method of claim 22 wherein said input signal provided at said variable gain amplifier can be provided by alternative first and second signal sources, and further comprising selecting said initial asymmetry compensation setting value to provide said replacement asymmetry compensation setting value at a beginning of an input signal provided at said variable gain input from said first source, and providing said representation of a said current asymmetry compensation setting value for use selectively as said initial asymmetry compensation setting value at an ending of providing said input signal to said variable gain amplifier from said first source.

26. A method for determining lateral position errors of a magnetic field sensor with respect to a track on a rotating magnetic medium disk in a magnetic data storage and retrieval system having a succession of zones in various lateral positions with respect to said track each containing a plurality of magnetization direction transitions therein, said method comprising: sampling and digitizing a first zone signal developed from said magnetic field sensor being past by a first said zone at selected times to provide successive member values in a first zone digitized values sequence; summing in succession each member value of said first zone digitized values sequence with a sum of those member values preceding that member value to form a first zone sum; sampling and digitizing a second zone signal developed from said magnetic field sensor being past by a second said zone at selected times to provide successive member values in a second zone digitized values sequence; negating and summing in succession each member value of said second zone digitized values sequence with a sum of those member values preceding that member value and with said first zone sum to form a first net paired zone sum.

27. A special member occuπence notifier for signaling occurrences of special member values, and polarities thereof, from a succession of member values of either polarity in a digitized values sequence, said notifier having a pair of outputs and having an occurrence input coupled to receive an occurrence indicator pulse signal indicating occurrences of said special member values in said digitized values sequence, a polarity input coupled to receive a polarity indicator pulse signal indicating polarities of said special member values in said digitized values sequence, and a format input coupled to receive control signals directing whether a polarity indication should appear on one of said pair of outputs if a special member value is indicated in said occurrence indicator signal along with a special member indication appearing on that one remaining of said pair of outputs, or whether a peak and polarity indication for one polarity should appear on one of said pair of outputs if a special member value of one polarity is indicated in said occurrence indicator signal along with a peak and polarity indication for that other polarity appearing on that one remaining in said pair of outputs if a special member value of another polarity is indicated in said occurrence indicator signal, said notifier comprising: a first pulse delayer having inputs coupled to said occurrence and polarity inputs and an output, said first pulse delayer being capable of storing therein a signal pulse provided on a said input thereof and providing a representation on said output thereof of said stored pulse after a delay following said storing; a second pulse delayer having inputs coupled to said occurrence and polarity inputs and an output, said second pulse delayer being capable of storing therein a signal pulse provided on a said input thereof and providing a representation on said output thereof of said stored pulse after a delay following said storing; a first signal selector having a pair of signal inputs each coupled to a corresponding one of said first and second pulse delayer outputs, a selection control input coupled to said format input, and an output, said first signal selector being capable of providing representations at said output thereof of signals appearing at a selected one of said signal inputs thereof as selected by control signals appearing on said selection control input thereof, said first signal selector output being coupled to a said notifier output; a third pulse delayer having an input and an output, said third pulse delayer being capable of storing therein a signal pulse provided on said input thereof and providing a representation on said output thereof of said stored pulse after a delay following said storing, said third pulse delayer output being coupled to a said notifier output; and a second signal selector having a pair of signal inputs coupled to said occurrence and polarity inputs, a selection control input coupled to said format input, and an output coupled to said third pulse delayer input, said second signal selector being capable of providing representations at said output thereof of signals appearing at a selected one of said signal inputs thereof as selected by control signals appearing on said selection control input thereof.

28. The apparatus of claim 27 wherein said second pulse delayer has a plurality of delay units connected in series between said inputs and said output thereof so that a signal pulse provided on a said input thereof is after a delayed following said storing thereof by a time duration equal to a sum of those delays provided by each of said delay units before a representation^* thereof is provided on said output thereof, wherein controls signals on said format input thereof further direct whether at least one of said delay units should be bypassed by a representation of said signal pulse before a said representation is provided on said output so said delay thereof is omitted from said sum.

29. The apparatus of claim 27 wherein said digitized values sequence is obtained from an information retrieval signal based on a signal generated by a magnetic field sensor positioned adjacent to magnetic material supported on a disk in a magnetic data storage and retrieval system.