WO1999014800A1

WO1999014800A1 - Method and apparatus for high-performance integrated circuit interconnect fabrication

Info

Publication number: WO1999014800A1
Application number: PCT/US1998/019367
Authority: WO
Inventors: Mehrdad M. Moslehi
Original assignee: CVC Products Inc
Current assignee: CVC Products Inc
Priority date: 1997-09-18
Filing date: 1998-09-17
Publication date: 1999-03-25
Anticipated expiration: 2000-03-18
Also published as: EP1018149A1; KR20010024096A; JP2001516970A; TW426983B

Abstract

A method and apparatus for multi-level interconnection fabrication on an integrated circuit are disclosed. A liner/barrier layer (172) and a conductive layer (174) are deposited to fill the trenches and holes in an insulating layer. A globally planarized disposable layer (176) is then formed on the conductive layer (174). The layers are removed at substantially similar rates of material removal, and the removal is stopped when both layers have been removed except for material from the conductive layer filling the trenches and holes. In one implementation, the conductive layer (174) is a copper layer and the globally planarized disposable layer (176) is a tin or tin alloy layer and its formation includes deposition, melting, and resolidification. Further, the removal can be accomplished by an ion-beam etch which is stopped based on in-situ real-time measurement of the wafer surface reflectance. The method employs a cluster tool apparatus.

Description

METHOD AND APPARATUS FOR HIGH-PERFORMANCE INTEGRATED CIRCUIT INTERCONNECT FABRICATION

TECHNICAL FIELD OF THE INVENTION

This invention relates in general to the field of semiconductor integrated circuit fabrication, and more particularly to a method and apparatus for multi-level interconnect fabrication for high performance semiconductor chips.

BACKGROUND OF THE INVENTION

Integrated circuits fabricated on semiconductor substrates, such as silicon wafers, typically have multiple metal layers, interconnected by contact or via plugs and separated by insulator layers, that provide electrical connections among devices formed on a silicon (or other semiconductor material such as GaAs) substrate. These on-chip interconnects thereby provide signal communication paths among the transistors and/or other active/passive devices fabricated on the monolithic integrated circuit chip. The multilevel on- chip interconnects, in state-of-the-art silicon integrated circuits, typically use aluminum (or aluminum alloys such as Al/0.5% Cu) as the electrical conductor and silicon dioxide or an alternative lower permitivity dielectric materials (e.g., an organic low-k material or an inorganic low-k material, such as fluorinated silicon oxide or Si_xO_yF_z) as the interlevel/inter-metal insulator. Typically, the process flow for multilevel interconnect fabrication starts after completion of the transistor fabrication process flow (often called Front- End-of-the-Line or FEOL) . State-of-the-art silicon integrated circuits (ICs) often employ either tungsten plugs or aluminum plugs to form the conductive via plugs for making electrical contacts between different levels of metal interconnects in conjunction with aluminum (or an aluminum alloy such as Al/0.5% Cu) metal interconnect lines . SUMMARY OF THE INVENTION

In accordance with the present invention, an improved method and apparatus for high-performance interconnect fabrication is disclosed that provides advantages over conventional interconnect fabrication process flows.

According to one aspect of the present invention, a method is provided for interconnect fabrication on a semiconductor integrate circuit. Trenches are formed in an insulator layer for conductive lines, and holes are formed in the insulator layer for plugs to connect to an underlying conductive metallization layer. A first conductive layer is then formed above the insulating layer (or a glue/barrier layer deposited over the insulating layer) and filling the trenches and the vias . Next, a globally planarized layer is formed above the first conductive layer. The globally planarized layer and at least a portion of the first conductive layer are then removed, and the removing is stopped when both layers have been removed except for material from the first conductive layer filling the trenches and the holes. In one implementation, the first conductive layer is a copper layer, and the globally planarized layer is either a tin layer or an alloy containing tin. Further, in one implementation, the removing process is accomplished by an ion-beam etch process which is stopped based upon a real-time measured reflectance of the surface of the integrated circuit. According to another aspect of the present invention, a method is disclosed for removing conductive layers from an integrated circuit in order to form either single-damascene or dual-damascene structures. The method includes removing conductive layers from a surface of a wafer being processed and producing a globally planarized surface with embedded patterned interconnect lines and plugs. A reflectance of the surface of the wafer is measured while the globally planarized disposable layer and the conductive layer are being removed. The removal of the disposable and the conductive layers is then stopped when the surface reflectance goes through certain transitions and matches an expected end-point value. In one implementation, the expected end-point value is observed after going through a number of expected transitions between various surface reflectance values.

According to a further aspect of the invention, an apparatus is disclosed for high-performance interconnect fabrication on an integrate circuit. The apparatus includes a cluster tool central wafer handler, a vacuum load lock chamber, and preferably a cleaning process module. The apparatus also includes a second deposition process module for depositing a conductive liner/barrier layer, a third deposition process module for depositing a conductive interconnect metal layer, and a fourth deposition process module for depositing a globally planarized disposable material layer. The apparatus further includes an etch process module for removing the disposable material layer and at least a portion of the conductive interconnect metal layer. In one implementation, the load lock chamber and all of the process modules are mounted on a cluster tool platform. Other implementations such as multiple cluster tools or multiple stand-alone tools are also possible options. A technical advantage of the present invention is the formation of embedded high-performance interconnects (such as with copper) using a clusterable process flow without a need for metal chemical-mechanical polishing (CMP) . Moreover, the methodology and process flow of the present invention results in formation of a globally planarized integrated circuit surface without a need for a relatively expensive CMP process. A globally planarized chip surface is an essential requirement for enhanced manufacturing yield of advanced integrated circuits (particularly due to the relatively stringent depth-of-focus requirements of advanced optical lithography tools) .

Another technical advantage of the present invention, by not employing wet processing, is the elimination of the significant waste generation and disposal problems associated with the CMP process of conventional copper interconnect fabrication processes. This can result in improved environmental impact and reduced cost of ownership for the metallization process flow.

Moreover, another technical advantage of the present invention is reduced manufacturing cycle time due to the cluster tool implementation of the interconnect process flow.

Additional technical advantages should be apparent from the following description, the drawings, and the claims .

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the present invention and the advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features, and wherein:

FIGURE 1 is a flowchart of a conventional prior art process flow for fabrication of multilevel aluminum interconnects using tungsten plugs (current mainstream technology) ;

FIGURE 2 is a flowchart of a conventional prior art process flow for a dual-damascene multilevel copper interconnect structure; FIGURES 3A, 3B, 3C and 3D are cross sections of a portion of an integrated circuit interconnect structure after steps in the process flow of FIGURE 2;

FIGURE 4 is a block diagram of one embodiment of a cluster tool implementation for interconnect fabrication according to the present invention;

FIGURES 5A and 5B provide a block diagram of an alternate cluster tool implementation for interconnect fabrication according to the present invention;

FIGURE 6 is a cross section of a portion of an integrated circuit after the deposition of a globally planarized tin (or an alloy containing tin) layer according to the present invention;

FIGURE 7 is a diagram of real-time optical reflectance measured during the ion-beam etch processing of the integrated circuit of FIGURE 6 used for the purpose of real-time etch process end-pointing; and

FIGURE 8 is a flowchart of a process flow for fabrication of a multilevel copper interconnect structure according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION Conventional Formation of Multilevel Interconnects

FIGURE 1 is a flowchart of a conventional prior art process flow for fabrication of multilevel aluminum interconnects using tungsten plugs on silicon integrated circuitry. As shown, in step 10, the transistor (and other device) fabrication process is completed (Front- End-of-the-Line (FEOL)) on the silicon wafer. In step 12, interlevel dielectric (ILD) material is deposited, usually using a plasma-enhanced chemical-vapor deposition (PECVD) or a thermal chemical-vapor deposition (CVD) process. Using chemical-mechanical polishing (CMP), in step 14, the dielectric layer is globally planarized. Additional interlevel dielectric (ILD) is then deposited (by thermal CVD or PECVD) in step 16 to establish the desired thickness. In step 18, the interconnect contact holes are formed by microlithography patterning and anisotropic etch such as reactive ion etch (RIE) . A liner/barrier layer is then deposited in step 20 by, for instance, a collimated physical-vapor deposition (PVD) process. This layer may serve both as a diffusion barrier and an adhesion layer.

In step 22, tungsten contact plugs (i.e., for contacts between the metal-1 and the integrated circuit devices such as the transistor gate and source/drain junctions) are formed by chemical-vapor deposition (CVD) of tungsten and subsequent chemical-mechanical polishing (CMP) . A first metal layer is then deposited in step 24 by sputter deposition of an aluminum alloy (e.g., Al/0.5% Cu) . The metal interconnect lines are formed in step 26 by microlithography and metal etch such as an RIE process. In step 28, an interlevel (or intermetal) dielectric (ILD) is deposited by a suitable deposition process such as plasma enhanced CVD (PECVD) or spin-on dielectric formation. This dielectric layer is then globally planarized in step 30 using dielectric chemical-mechanical polishing (CMP) followed by post-CMP clean. Subsequently, an additional dielectric layer may be deposited in step 32 to establish the desired ILD thickness .

In step 34, a microlithography patterning step and a reactive-ion etch (RIE) step are performed for formation of via holes (for connections between the first metal layer and a second metal layer) . In step 36, a liner/barrier layer is deposited by either a collimated PVD process or an MOCVD process, and, in step 38, tungsten plugs for the vias are formed by chemical- vapor deposition (CVD) of tungsten and subsequent metal chemical-mechanical polishing. The second metal layer is then deposited, in step 40, by sputter deposition of an aluminum alloy (e.g., Al/0.5% Cu) . The metal interconnects are formed, in step 42, by microlithography patterning and metal reactive-ion etch (RIE). According to step 44, if more metal interconnect levels are needed, the process flow is repeated starting at step 28. If not, then the process continues at step 46 with deposition of a passivation overlayer by plasma- enhanced chemical-vapor deposition (PECVD) . Then, in step 48, bonding pad openings are formed by microlithography patterning and dielectric etch. Chip packaging is then accomplished in step 50 to form the final integrated circuit product.

The interconnect process flow of FIGURE 1 employs dielectric chemical-mechanical polishing (CMP) to form a globally planarized interlevel/intermetal dielectric surface prior to formation of the subsequent plugs and interconnect level. A globally planar surface facilitates the microlithography patterning process control and is essentially a requirement for 0.25_m technologies and beyond. Moreover, a global planarization process typically improves the overall chip manufacturing yield and enables fabrication of multi-level interconnects with increased number of interconnect levels.

In contrast to FIGURE 1, some semiconductor fabrication technologies employ aluminum (or an alloy of Al such as Al/0.5% Cu) , instead of tungsten, to form the conductive interlevel/intermetal plugs (for contacts and vias) . This approach would employ an aluminum reflow sputtering process or PVD reflow and would result in a less complex interconnect fabrication process flow, improved interconnect reliability, improved interconnect performance (due to lower resistance plugs) , and improved fabrication yield. The reflow sputtering

(physical-vapor-deposition reflow or PVD reflow) process combines the multiple process steps of plug and interconnect formation (tungsten deposition, CMP of tungsten, post-CMP clean, liner/barrier layer deposition, and aluminum or aluminum alloy metal deposition) into a single metal deposition step by PVD reflow, thus, resulting in a significant process simplification. An alternative approach would be to form the Al plug by metal-organic chemical-vapor deposition (MOCVD) of Al followed by PVD and Al/0.5% Cu to form the interconnect lines.

Conventional Method of Copper Interconnect Formation Beyond the 0.35 _m technology mode, the speed performance of advanced high-performance logic chips, such as microprocessors, can be limited by the constraints of the conventional interconnect system (i.e., interconnect "RC" propagation delays, cross-talk noise, and/or signal dispersion) . Thus, there has been significant interest in alternative low-resistivity metal and low-permitivity dielectric materials to replace the mainstream aluminum/silicon dioxide interconnect material system. Copper is a primary material of interest to replace aluminum and aluminum alloys. This is due to the fact that copper has a lower electrical resistivity than aluminum (bulk resistivity of copper is C 1.78 _3 • cm vs . C 2.7 _3 ^• cm for aluminum) and properly textured copper exhibits significantly longer electromigration lifetime compared to aluminum. There has also been a lot of research work to develop alternate interlevel/intermetal dielectric materials, with reduced permitivity values (low-k dielectrics), to replace silicon dioxide. While silicon dioxide has a "k" value of 3.9 or larger, the low-k dielectric materials of interest, such as organic low-k materials, can have k values in the range of 1.5 to 3.0 and below. The combination of copper metallization with low-k interlevel/intermetal dielectrics enables enhanced chip performance, improved interconnect reliability, and reduced chip manufacturing cost (due to the reduced number of metal interconnect levels required with Cu/low-K compared to the Al/Si0₂ interconnect material system) for a given chip performance.

While copper has many advantages over aluminum from interconnect performance and reliability standpoint, the copper interconnect fabrication process is generally more complex and less mature than that for aluminum. While aluminum can be easily etched and patterned by plasma-assisted reactive ion etch (RIE) methods in chlorine-containing chemistries, there is no analogous well-developed and manufacturable etch process for copper pattering using photoresist mask. Thus, alternative methods have been proposed for fabrication of copper patterned interconnects which are based on the use of copper chemical-mechanical polishing (CMP) to form embedded copper interconnects without any need for a copper dry etch process. The damascene and dual-damascene techniques are the preferred and proven methods for fabrication of copper interconnects. FIGURE 2 is a flowchart of a conventional process flow for a dual-damascene multilevel copper interconnect structure fabrication. As shown, in step 52, the transistor (and other device) fabrication process is first completed (FEOL) . In step 54, the interlevel dielectric (ILD) material (e.g., silicon dioxide or a suitable low-k material) is deposited. The dielectric is then planarized, in step

56, by chemical-mechanical polishing (CMP) followed by a post-CMP clean process. In step 58, additional interlevel dielectric is deposited by PECVD or CVD to establish the desired thickness. Contact holes are formed, in step 60, by microlithography patterning and reactive ion etch (RIE) . A thin liner/barrier layer is then deposited, in step 62, by collimated physical-vapor deposition (PVD) or metal-organic chemical-vapor deposition (MOCVD) . In step 64, a copper layer is deposited using, for example, metal-organic chemical-vapor deposition (MOCVD) , physical-vapor deposition (PVD) or plating (or a combination of these methods) . The copper layer is planarized, in step 66, by metal chemical-mechanical polishing (CMP) followed by a post-CMP clean process. Multilayer interlevel (intermetal) dielectric is then deposited in step 68 (e.g., SiN/Si0₂/SiN/Si0₂) . In this example, the SiN layers will be used as etch stop layers during formation of the metal trenches and via holes. In step 70, microlithography patterning and an anisotropic dielectric etch are performed to form trenches for embedded metal lines of the first metal layer. Subsequently, in step 72, microlithography patterning and another anisotropic dielectric etch are performed to form via holes. In step 74, a thin liner/barrier layer is deposited using, for example, collimated physical-vapor deposition (PVD) or metal- organic chemical-vapor deposition (MOCVD) . Then, in step 76, a copper layer is deposited using, for example, metal-organic chemical-vapor deposition (MOCVD) , physical-vapor deposition (PVD) or plating (or a combination of any two methods) . The copper layer is planarized, in step 78, by chemical-mechanical polishing (CMP) followed by post-CMP clean, resulting in embedded patterned copper interconnect lines and plugs. The CMP process removes both the exposed copper and underlying thin glue/barrier layers from the flat top surfaces of the interlevel/intermetal dielectric, leaving embedded copper and glue/barrier materials in the interconnect line and plug trenches.

In step 80, it is determined whether or not more interconnect levels are needed. If not, the process continues at step 82 and a passivation overlayer is deposited by plasma-enhanced chemical-vapor deposition (PECVD). Bonding pad openings are formed, in step 84, by microlithography patterning and dielectric etch, and final chip packaging is accomplished in step 86.

If, in step 80, it is decided that more interconnect levels are needed, the process continues at step 68 with the deposition of multilayer interlevel dielectric. FIGURE 3A is a cross section of a portion of an integrated circuit interconnect structure after this step 68 in the process flow. FIGURE 3A shows a lower level of copper interconnect line 88 in conjunction with a copper via plug 89. A conductive liner/barrier layer 90 separates copper interconnect lines 88 and plugs 89 from adjacent interlevel dielectric layers 92 and 94 (e.g., Si0₂ and SiN, respectively) . The subsequently deposited multilevel dielectric layers 96 (e.g., SiN) and 98 (e.g., Si0₂) are also shown within the stacked dielectric structure (e.g., SiN/Si0₂/SiN/Si0₂) .

FIGURE 3B is a cross section of the integrated circuit interconnect structure of FIGURE 3A following the microlithography patterning and dielectric etch process steps of 70 and 72 in FIGURE 2. As shown in FIGURE 3B, metal line trenches 99 and via holes 100 have been formed in the dielectric layers 96 and 98 (which are now planarized layers as deposited) . FIGURE 3C shows a cross section of the integrated circuit interconnect structure after deposition of liner/barrier and copper layers (after steps 74 and 76 in FIGURE 2) . As shown, a thin conductive liner/barrier layer 102 and a new copper layer 104 have been deposited above the existing interconnect levels. Lastly, FIGURE 3D is a cross section of the integrated circuit interconnect structure after step 78 in which copper layer 104 was planarized and both copper and liner/barrier layers were removed from the top surface of dielectric layer 98.

This CMP process for removal of copper and liner/barrier from top (and for global planarization) is followed by a post-CMP clean process. The result is a new level of copper interconnect lines 104 and via plugs 105 which are fully planarized and embedded in the interlevel dielectric structure.

One significant advantage of a dual-damascene interconnect process is that both the interlevel conductive plugs (contacts/vias) and the metal lines are formed by a single copper deposition process step (or a single multi-step deposition process sequence) . Another advantage of the dual damascene copper interconnect structure and process flow is that, beyond the first interlevel dielectric layer, the subsequent intermetal dielectric layers are deposited on globally planarized surfaces and remain globally planarized in the as- deposited condition. Thus, the intermetal dielectric deposition steps do not require any CMP dielectric polishing steps, resulting in process simplification. Moreover, there is no gap-fill requirement for the interlevel dielectric deposition process.

However, the conventional damascene or dual- damascene copper interconnect processes described above suffer from problems and relatively high fabrication cost due to the requirement to use chemical-mechanical polishing (CMP) of the copper to form the embedded copper metal interconnect lines and plugs. The CMP process is a relatively complex and expensive process which requires a significant amount of consumables such as polishing pads and slurry. Moreover, the CMP process is a stand-alone wet process and cannot be easily integrated on a cluster tool with the preceding or subsequent process steps. In addition, CMP can cause device damage and wafer contamination, and requires effective post-CMP cleaning. Therefore, it would be highly desirable if a process flow could be developed that would enable formation of globally planarized embedded copper interconnects using single or dual damascene approach without a need for copper CMP.

Improved Apparatus and Method for Formation of Copper Interconnects According to the present invention, a method and apparatus are disclosed that allow formation of embedded copper interconnects (lines and plugs) using a clusterable process flow without a need for copper CMP. Moreover, the process flow of the present invention results in formation of a globally planarized surface without a need for CMP. The process flow does not employ wet processing and eliminates the significant waste generation and disposal problems associated with the current CMP processes. For instance, a typical CMP process with a slurry flow rate of 300 cc/min. and a process time of 3 min. /wafer consumes 900 cc/wafer of slurry. With a throughput rate of 20 wafers/hour and a slurry to deionized water dilution ratio of 1:2, the total slurry consumption per month is on the order of 4,366 liters or 1,310 kg. This amounts to as much as 52,390 liters or 15,717 kg of slurry waste generation and disposal requirement per year. Clearly, an alternative, zero-emission and waste-free process flow is highly desirable from the environmental protection and safety standpoints. FIGURE 4 is a block diagram of one embodiment of a cluster tool implementation of the present invention. It should be apparent that various other implementations are possible within the teachings of the present invention. As shown, a cluster tool, indicated generally at 110, includes a cluster tool platform or central wafer handler 112. Vacuum load lock modules 114 and 116 provide a means for loading and unloading wafers through wafer cassettes. In the embodiment of FIGURE 4, cluster tool 110 has six process modules connected to the central wafer handler for processing the wafers. These include a soft plasma cleaning module 118 (such as an inductively-coupled plasma or ICP module) , a metal-organic chemical- vapor deposition (MOCVD) module 120 for conformal deposition of a thin liner/barrier layer (such as TiN or TaN) , and another MOCVD module 122 to deposit copper. The modules also include a physical-vapor deposition (PVD) module 124 for sputter deposition of a suitable low melting point/high boiling point (or extremely low vapor pressure in the molten state above or near the melting point) elemental or compound material (such as tin, indium, or bismuth, or their alloys) . Further, the modules include two ion- beam etch (IBE) (also called ion milling) modules 126 and 128.

Although the description of the illustrated embodiment is presented for a process flow utilizing metal-organic chemical-vapor deposition (MOCVD) for formation of the liner/barrier layer (TiN, TaN, TiSiN, TaSiN, or another suitable barrier (e.g., WN, Ta) ) and copper, the concepts of this invention are generically applicable to other interconnect process flows and materials. For example, the invention is applicable where the liner/barrier is formed by physical-vapor deposition (PVC) instead of MOCVD, is also applicable where copper is deposited by a PVD and/or plating process or a hybrid MOCVD/plating or PVD/plating process or MOCVD/PVD process, and is further applicable where another interconnect metal material such as gold, aluminum or silver is used instead of copper.

As shown in FIGURE 4, this embodiment of the present invention can be implemented on a single vacuum- integrated cluster tool 110 such as the one shown. After the dielectric trenches and via holes are defined (for subsequent insertion of the embedded copper metal lines and copper plugs) , as shown in FIGURE 3B, the wafers can be then loaded into one of the vacuum load lock chambers 114 or 116 (LL₂ or LL₂) attached to the vacuum-integrated cluster tool 110. In addition to the dual vacuum load lock chambers 114 and 116, this cluster tool 110 has six single-wafer or mini-batch process modules 118 through 128 { Ε>M₁ through PM₆) as described above . FIGURES 5A and 5B provide a block diagram of an alternate cluster tool implementation of the present invention. This implementation uses two six-sided vacuum-integrated cluster tools, shown generally at 130 and 132 which are functionally equivalent to the eight- sided cluster tool 110 of FIGURE 4. As shown, cluster tool 130 has a platform 134 and two vacuum load lock chambers 136 and 138. Cluster tool 130 includes four process modules: an ICP soft clean module 140, MOCVD liner/barrier layer module 142, and MOCVD copper deposition modules 144 and 146. Cluster tool 132 similarly has a platform 148 and vacuum load lock chambers 150 and 152. The four process modules of cluster tool 132 are: a PVD tin (or a tin alloy) deposition module 154, and three IBE modules 156, 158 and 160. While the dual six-sided cluster tool implementation of FIGURES 5A and 5B is functionally equivalent to the single eight-sided cluster tool implementation of FIGURE 4, the former can provide a higher fabrication throughput due to the use of multiple MOCVD copper deposition modules 144 and 146 and the IBE modules 156, 158 and 160, which perform the slower process steps (copper deposition and ion milling) of the interconnect process flow. Although, the subsequent description and discussion is presented in reference to the eight-sided cluster tool implementation of FIGURE 4, it is applicable to the implementation of FIGURES 5A and 5B as well as alternate implementations within the scope of the present invention.

Before arriving at cluster tool 110 of FIGURE 4, each wafer contains the dual-damascene dielectric trench and contact/via hole structure such as that shown in FIGURE 3B. In cluster tool 110, each wafer is first processed in the ICP soft clean module 118 in order to remove any etch-induced contaminants and any native oxide on any underlying exposed copper surfaces and dielectric trench surfaces. The wafer is then transferred into the MOCVD liner/barrier module 120 in order to deposit a suitable thin liner/barrier layer such as TiN, Ta, or TaN (the layer thickness may be 100 __ to 300 _) . For this step, a collimated PVD or directional ionized PVD module may alternatively be used instead of the MOCVD module, although MOCVD provides a superior process conformality and sidewall/bottom coverage compared to PVD. The wafer is then moved into the MOCVD copper process module 122 in order to deposit a blanket layer of copper. This fills up the dielectric trenches formed for embedded copper metal lines as well as the contact or via holes reserved for interlevel or intermetal conductive copper plugs. The copper layer is thick enough so that the lowest point on the final copper layer surface is above the globally planarized dielectric surface by a comfortable margin. A conformal copper deposition process, such as with MOCVD, ensures void-free filling of the high-aspect-ratio trenches and holes. While the illustrated embodiment of this invention is shown using an MOCVD process to form the copper interconnect regions, the process flow of this invention is also applicable to interconnect formation using alternative methods of copper deposition, such as a combination of MOCVD copper seed layer or PVD copper seed layer formation followed by plating, or complete formation of copper lines/plugs by a PVD reflow process (or combination of an MOCVD copper seed layer followed by a PVD copper reflow process) . After copper deposition, the wafer is then moved into the PVD tin (PVD-Sn) process module 124 in order to deposit a relatively thick layer of tin (or any metallic element or alloy with a low melting point and preferably a relatively high boiling point) and then globally planarize the tin layer in situ. For instance, the tin layer thickness can be on the order of 5,000 Angstroms to over 2 _m such that it is made significantly (e.g. several times) larger than the peak-to-peak height variation on the surface of deposited copper layer. Deposition of tin can be performed either at room temperature (or near room temperature) or at a temperature above the melting point of tin (e.g., 232^' C) . If the deposition is performed at room temperature (or at any wafer temperature below the melting point of tin which is 232^' C) , the wafer is then heated (preferably in situ in the PVD-Sn module 124) to a temperature slightly over the melting point of tin (e.g., to 250^* C or as 350^* C) for a short period of time (e.g., for 1 to 60 seconds). Once tin melts, it is converted to a liquid medium with a very low viscosity (comparable to alcohol) and a relatively high surface tension on the liquid metal melt surface. Thus, the liquid tin medium becomes globally planarized immediately upon melting due to its high liquid-state surface tension and very low viscosity, and the tendency of the liquid metal medium to achieve minimum surface energy. The wafer is then cooled (preferably rapidly) back to a temperature below the melting point of tin (e.g., as 150^* C) , for instance by rapid chuck cooling, prior to removal of the wafer from the PVD-Sn module 124. As indicated, the tin deposition process may also be performed while the wafer temperature is kept at above the melting point of tin which is 232^" C (e.g., at a temperature between 250^' C and 350° C) . This results in a globally planarized liquid tin layer over the copper surface by the time the deposition process is completed. Again, the wafer is then rapidly cooled down to below the melting point of tin (e.g., to as 150^' C) to resolidify the globally planarized liquid tin layer before it is removed from the tin module 124. Any suitable metal or metallic alloy with a relatively low melting point (preferably below 350° C) and preferably a relatively high boiling point may be used instead of tin. These include indium, bismuth, any binary or tertiary alloys containing tin and/or indium and/or bismuth, and any suitable alloys of tin or indium or bismuth containing lead. The wafer with deposited copper and globally planarized tin layer is then loaded into one of the ion- beam etch (IBE) modules 126 or 128. The cluster tool 110 of FIGURE 4 has two IBE modules 126 and 128 for increased fabrication throughput. Each IBE module 126 and 128 preferably has an optical endpoint detection sensor, such as an optical reflectance sensor, which can recognize the reflectance changes and transitions between the surface of tin and the underlying copper and the surface of the underlying interlevel insulator with embedded copper lines and plugs. The IBE module 126 or 128 performs a blanket physical etch process over the entire wafer surface with a good etch uniformity (e.g., 1& non- uniformity as 3% over 200mm wafer area) . The etch conditions are set such that the etch rates or removal rates of tin and copper are essentially equal. FIGURE 6 is a cross section of a portion of an integrated circuit interconnect structure after the deposition of a globally planarized tin (or a low- melting-point alloy containing tin, indium, and/or bismuth) layer according to the present invention. As shown, a lower copper interconnect line 162 and copper plug 163 have adjacent liner/barrier layer 164 (e.g., TiN, Ta, TaN, WN_X, or a ternary liner/barrier such as TiN or TaSiN) separated by an interlayer dielectric 166 (e.g, Si0₂) . A multilayer dielectric (e.g.,

SiN/Si0₂/SiN/Si0₂) is formed by layers 168 and 170, and a subsequent liner/ barrier layer 172 (e.g., TiN, Ta, TaN, WN_X, or a ternary liner/barrier such as TiSiN or TaSiN) is formed above the multilayer dielectric layers 168 and 170. A copper layer 174 is subsequently formed above liner/barrier layer 172, and a globally planarized tin (or a low-melting-point alloy containing tin, indium, and/or bismuth) layer 176 is formed above copper layer 174. FIGURE 7 is a diagram of an optical reflectance signal during the ion-beam etch processing of the integrated circuit interconnect structure of FIGURE 6. The laser or optical reflectance sensor of the IBE module 126 or 128 first measures the surface reflectance of blanket metallic tin layer (R_x) . This reflectance remains the same until the ion milling process begins to break through the tin layer 176 at the thinnest regions of tin (corresponding to the peak copper heights) . This transition from tin to copper results in a transition in the optical reflectance measurement (for instance, from an R_x value to a higher R₂ value) . When the IBE process breaks through the thickest regions of the tin layer 176 to reach an all-copper (globally planarized) surface within copper layer 174, the surface optical reflectance changes to that of copper (R₂) . This is detected as a first signal transition (transition #1) from a reflectance of R_x to R₂. As the IBE process continues into the all-copper region of layer 174, the globally planarized copper surface is removed downward until the etch process reaches the surface of the liner/barrier layer 172 over the globally planarized interlayer dielectric (ILD) surface of layer 170. This is detected as a second transition (transition #2) from a reflectance of R₂ to R₃. The IBE process is then continued until the liner/barrier layer 172 is cleared from the ILD top surface of layer 170. This corresponds to a third transition (transition #3) from a reflectance of R₃ to R₄. This third transition signals the endpoint of the sensor-based IBE process. At the end of this IBE process, the wafer has embedded copper lines and plugs with a globally planarized surface where the patterned interconnect formation and global surface planarization have been accomplished in a vacuum-integrated cluster tool environment without a need for CMP. If desired, the wafers can be directly transferred to another cluster tool for deposition of the subsequent ILD stack.

FIGURE 8 is a flowchart of a process flow for fabrication of a multilevel copper interconnect structure according to the present invention. In step 170, the transistor (and other front-end device) fabrication process flow has been completed (FEOL) . In step 172, interlevel dielectric material (IDL) is deposited, and, in step 174, the dielectric is planarized by physical-vapor deposition (PVD of tin (Sn) and ion-beam etch (IBE) ) . Additional interlayer dielectric (ILD) is deposited in step 176 to establish the desired thickness. In step 178, contact holes are formed by microlithography patterning and reactive-ion etch. A liner/barrier layer is deposited, in step 180, by MOCVD or PVD, and a copper layer is deposited, in step 182, by MOCVD, PVD and/or plating.

In step 184, a tin (or a low-melting-point alloy containing tin, indium, and/or bismuth) layer is deposited using physical-vapor deposition (or another deposition method) and is melted and solidified in situ. This step forms a globally planarized tin (or metallic alloy) layer. In step 186, the tin layer is processed and removed along with removal of a fraction of the copper and liner/barrier layer by an ion-beam etch (IBE) to leave a globally planarized surface and to produce the patterned and embedded copper interconnect lines and plugs. A multilayer intermetal dielectric is deposited in step 188 comprising, for example, alternating SiN and Si0₂ layers. In step 190, trenches for embedded metal lines are formed by microlithography patterning and dielectric anisotropic (e.g., RIE) etch, and, in step 192, via holes also are formed by microlithography patterning and dielectric (e.g., RIE) etch. Then, in step 194, a liner/barrier layer is deposited by MOCVD or PVD followed by deposition, in step 196, of a copper layer by, for example, MOCVD, PVD and or plating. In step 198, a tin (or a low-melting-point element or alloy consisting of tin, indium, and/or bismuth) layer is deposited by PVD and melted and solidified in situ to create a globally planarized tin (or another metallic) layer. In step 200, the tin layer and at least a fraction of copper and liner/barrier layers are removed by ion-beam etch as described above to leave a planarized surface with the embedded and patterned copper lines and via plugs.

In step 202, it is determined whether more interconnect levels are needed. If so, the process flow returns and continues at step 188. If not, the process flow continues with step 204 and a passivation overlayer is deposited. In step 206, bonding pad openings are formed by microlithography patterning and dielectric etch, and the chip is packaged in step 208. While the description of the above embodiment of the present invention was based on the use of tin as the global planarization layer, other materials can be used, such as indium, bismuth, or any suitable low melting point (e.g., below 350^' C) alloys of tin, indium, bismuth, lead, or other suitable elements. Moreover, reactive ion etch (RIE) process module may be used instead of the IBE process modules in various embodiments of this invention. The etch requirement (for IBE or RIE) is that the etch rates of copper and tin (or other disposable material used for the global planarization layer) should be made essentially equal. Further, while the above embodiment of the present invention has been described as a cluster tool implementation, other implementations are possible such as an implementation based on stand-alone equipment.

Although the present invention has been described in detail for select embodiments, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

WHAT IS CLAIMED IS:

1. A method for interconnect fabrication on a semiconductor integrated circuit, comprising: forming trenches in an insulator layer for filling with conductive lines; forming holes in the insulator layer for filling with conductive plugs to connect to an underlying conductive layer; depositing a conductive layer above the insulating layer and filling the trenches and the vias; forming a globally planarized disposable layer above the conductive layer; removing the globally planarized disposable layer and at least a portion of the conductive layer using an etch process; stopping the etch process when both the globally planarized disposable layer and the portion of the conductive layer have been removed except for material from the conductive layer filling the trenches and the holes.

2. The method of Claim 1, wherein the etch process results in formation of embedded conductive lines and plugs with a globally planarized integrated circuit surface.

3. The method of Claim 1, wherein the conductive plugs comprise via plugs connecting to an underlying interconnect metal layer.

4. The method of Claim 1, wherein the conductive plugs comprise contact plugs connecting to underlying electronic devices.

5. The method of Claim 1, wherein said conductive layer is a silver layer.

6. The method of Claim 1, wherein said conductive layer is a gold layer.

7. The method of Claim 1, wherein said conductive layer is a superconducting layer.

8. The method of Claim 1, wherein said conductive layer is a copper layer.

9. The method of Claim 8, wherein forming the copper layer is accomplished by a metal-organic chemical- vapor deposition (MOCVD) process.

10. The method of Claim 8, wherein forming the copper layer is accomplished by a physical-vapor deposition (PVD) process.

11. The method of Claim 8, wherein forming the copper layer is accomplished by a plating process.

12. The method of Claim 1, further comprising, prior to depositing the conductive layer, forming a thin liner/barrier layer on the insulating layer and the exposed surfaces of trenches and via holes.

13. The method of Claim 1, wherein the globally planarized disposable layer comprises tin.

14. The method of Claim 1, wherein the globally planarized disposable layer comprises indium.

15. The method of Claim 1, wherein the globally planarized disposable layer comprises bismuth.

16. The method of Claim 1, wherein globally planarized disposable layer comprises an alloy with a melting point of less than 350° C.

17. The method of Claim 16, wherein said alloy comprises tin.

18. The method of Claim 16, wherein said alloy comprises indium.

19. The method of Claim 16, wherein said alloy comprises bismuth.

20. The method of Claim 16, wherein said alloy comprises lead.

21. The method of Claim 13, wherein the tin layer is formed by physical-vapor deposition and melting and resolidification of the tin layer.

22. The method of Claim 13, wherein the tin layer is formed by chemical-vapor deposition and melting and resolidification of the tin layer.

23. The method of Claim 13, wherein the tin layer is formed by plating and melting and resolidification of the tin layer.

24. The method of Claim 1, wherein said globally planarized disposable layer is formed by a combination of material deposition, material melting, and material resolidification.

25. The method of Claim 21, wherein the tin layer is melted at a temperature above the melting point of tin.

26. The method of Claim 1, wherein removing the globally planarized disposable layer and at least a portion of the conductive layer is accomplished by an ion-beam etch process.

27. The method of Claim 26, wherein the ion-beam etch removes the conductive layer and the globally planarized disposable layer at substantially the same etch rate.

28. The method of Claim 26, wherein stopping the removing of the globally planarized conductive layer and at least a portion of the conductive layer is based upon a real-time measurement of reflectance of the surface of the semiconductor integrated circuit.

29. A method for copper interconnect fabrication on a semiconductor integrated circuit, comprising: forming holes in an interlevel dielectric by microlithography and etch, the contact holes for making electrical connections to underlying devices; depositing a liner/barrier layer above the interlevel dielectric and contact holes; depositing a copper layer above the liner/barrier layer, the copper layer filling the holes; depositing a tin-containing layer above the copper layer; melting and resolidifying the tin-containing layer to form a globally planarized surface; removing the tin-containing layer and the copper layer using a blanket etch process until both layers have been removed except for portions of the copper layer filling the holes.

30. The method of Claim 29, wherein the blanket etch process is stopped based upon a real-time measurement of reflectance of the surface of the semiconductor integrated circuit.

31. The method of Claim 29, further comprising: depositing a multilayer intermetal dielectric after the step of blanket etch process; forming trenches in the intermetal dielectric by microlithography patterning and anisotropic dielectric etch, the trenches for embedding metal lines; forming via holes in the intermetal dielectric by microlithography patterning and anisotropic dielectric etch, the via holes for making electrical connecting to the underlying interconnect metal regions; depositing a liner/barrier layer above the intermetal dielectric, as well as exposed surfaces of trenches and via holes; depositing a copper layer above the liner/barrier layer, the copper layer filling the dielectric trenches and via holes; depositing a tin-containing layer above the copper layer; melting and resolidifying the tin-containing layer to form a globally planarized surface; removing the tin-containing layer and the at least a portion of the copper layer using a blanket etch until both layers have been removed except for portions of the copper layer filling the dielectric trenches and via holes.

32. The method of Claim 31, wherein removing the tin-containing layer and the copper layer is stopped based upon a real-time measurement of reflectance of the surface of the semiconductor integrated circuit.

33. A method for formation of a globally planarized integrated circuit interconnect structure, comprising: depositing a conductive layer and a globally planarized disposable layer above the semiconductor integrated circuit; removing the globally planarized disposable layer and a portion of the conductive layer from a surface of a wafer being processed; measuring in real time a reflectance of the surface of the wafer while the material layers are being removed; stopping the removal of material layers when the surface reflectance matches an expected measurement.

34. The method of Claim 33, wherein the material layers are a globally planarized tin layer above a copper layer, the copper layer used for metal interconnects .

35. The method of Claim 33, wherein the material removing is accomplished by an ion-beam etch process.

36. The method of Claim 33, wherein the expected measurement is a value for the surface reflectance after some reflectance transitions.

37. The method of Claim 33, wherein the expected measurement is observed after some changes of the value of the surface reflectance.

38. The method of Claim 37, wherein the changes comprise a number of expected transitions from one reflectance value to another.

39. An apparatus for interconnect fabrication on an integrated circuit interconnect feature using a cluster tool comprising: a central wafer handler; a vacuum load lock chamber; a first deposition process module for depositing a liner/barrier layer; a second deposition process module for depositing an interconnect metal layer; a third deposition process module for depositing a globally planarized disposable layer; and an etch process module for removing the globally planarized disposable layer and at least a portion of the interconnect metal layer.

40. The apparatus of Claim 39 further comprising a cleaning process module.

41. The apparatus of Claim 40, wherein the cleaning process module is an inductively-coupled plasma cleaning module.

42. The apparatus of Claim 39, wherein the first deposition process module is a metal-organic chemical- vapor deposition (MOCVD) module for depositing the liner/barrier layer.

43. The apparatus of Claim 39, wherein the first deposition process module is a physical-vapor deposition

(PVD) module module for depositing the liner/barrier layer .

44. The apparatus of Claim 39, wherein the second deposition process module is an MOCVD module for depositing a copper layer.

45. The apparatus of Claim 39, wherein the second deposition process module is a PVD module for depositing a copper layer.

46. The apparatus of Claim 39, wherein the third deposition process module is a physical-vapor deposition module (PVD) for depositing a tin-containing layer and for melting and resolidifying the tin layer to globally planarize the tin layer.

47. The apparatus of Claim 39, wherein the etch process module is an ion-beam etch module and is operable to stop removal of the globally planarized disposable layer and at least a portion of the interconnect layer based upon a real-time measurement of reflectance of the surface of a wafer being processed.

48. The apparatus of Claim 39, wherein the load lock chamber and all of the process modules are mounted on a single cluster tool platform.

49. The apparatus of Claim 39, wherein the load lock chamber and all of the process modules are mounted on multiple cluster tool platforms.