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WO1999009599A3 - Procede d'interconnexion verticale pour segments en silicium avec isolation dielectrique - Google Patents

Procede d'interconnexion verticale pour segments en silicium avec isolation dielectrique Download PDF

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Publication number
WO1999009599A3
WO1999009599A3 PCT/US1998/016900 US9816900W WO9909599A3 WO 1999009599 A3 WO1999009599 A3 WO 1999009599A3 US 9816900 W US9816900 W US 9816900W WO 9909599 A3 WO9909599 A3 WO 9909599A3
Authority
WO
WIPO (PCT)
Prior art keywords
segments
segment
die
stack
interconnected
Prior art date
Application number
PCT/US1998/016900
Other languages
English (en)
Other versions
WO1999009599A2 (fr
Inventor
Alfons Vindasius
Kenneth M Sautter
Original Assignee
Cubic Memory Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/915,620 external-priority patent/US6255726B1/en
Priority claimed from US08/920,273 external-priority patent/US6080596A/en
Application filed by Cubic Memory Inc filed Critical Cubic Memory Inc
Priority to KR1020007001498A priority Critical patent/KR100593567B1/ko
Priority to EP98944438A priority patent/EP1029360A4/fr
Priority to JP2000510170A priority patent/JP2001516148A/ja
Priority to AU91976/98A priority patent/AU9197698A/en
Publication of WO1999009599A2 publication Critical patent/WO1999009599A2/fr
Publication of WO1999009599A3 publication Critical patent/WO1999009599A3/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06551—Conductive connections on the side of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06593—Mounting aids permanently on device; arrangements for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01033—Arsenic [As]
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

La présente invention concerne un appareil permettant d'interconnecter verticalement des piles de segments en silicium. Chaque segment comprend une pluralité de dés adjacents sur une tranche de semiconducteur. La pluralité de dés sur un segment sont interconnectés sur le segment en utilisant une ou plusieurs couches d'interconnexions métalliques s'étendant sur les quatre coins du segment, de manière à former des plots de connexion de bord pour les points de connexion électriques externes. Après interconnexion des dés, le découpage de chaque segment s'effectue depuis l'envers de la tranche au moyen d'une coupure en biseau, afin d'obtenir quatre parois de bords inclinées vers l'intérieur sur chacun des segments. Après découpage des segments de la tranche, ils sont disposés les uns sur les autres de façon à former une pile. Les segments verticalement adjacents de la pile sont électriquement connectés en appliquant une époxy électroconductrice sur un ou plusieurs côtés de la pile. Les parois de bords inclinées vers l'intérieur de chaque segment de la pile forment un évidement qui permet à l'époxy d'accéder au plots de connexion de bord et aux circuits latéraux sur chaque segment, une fois les segments empilés. On applique un revêtement diélectrique sur les dés pour réaliser un revêtement conforme permettant de protéger et d'isoler le dés, et on utilise un laser pour pratiquer l'ablation de la surface au-dessus des plots de connexion, de manière à retirer le revêtement diélectrique et former ainsi des connexions électriques pour les plots de connexion.
PCT/US1998/016900 1997-08-21 1998-08-14 Procede d'interconnexion verticale pour segments en silicium avec isolation dielectrique WO1999009599A2 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020007001498A KR100593567B1 (ko) 1997-08-21 1998-08-14 유전체 절연부를 갖는 실리콘 세그먼트용 수직 상호접속 프로세스
EP98944438A EP1029360A4 (fr) 1997-08-21 1998-08-14 Procede d'interconnexion verticale pour segments en silicium avec isolation dielectrique
JP2000510170A JP2001516148A (ja) 1997-08-21 1998-08-14 誘電性絶縁を備えるシリコンセグメントを垂直に相互接続する方法
AU91976/98A AU9197698A (en) 1997-08-21 1998-08-14 Vertical interconnect process for silicon segments with dielectric isolation

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US08/915,620 US6255726B1 (en) 1994-06-23 1997-08-21 Vertical interconnect process for silicon segments with dielectric isolation
US08/915,620 1997-08-21
US08/920,273 1997-08-22
US08/920,273 US6080596A (en) 1994-06-23 1997-08-22 Method for forming vertical interconnect process for silicon segments with dielectric isolation

Publications (2)

Publication Number Publication Date
WO1999009599A2 WO1999009599A2 (fr) 1999-02-25
WO1999009599A3 true WO1999009599A3 (fr) 1999-04-15

Family

ID=27129674

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1998/016900 WO1999009599A2 (fr) 1997-08-21 1998-08-14 Procede d'interconnexion verticale pour segments en silicium avec isolation dielectrique

Country Status (5)

Country Link
EP (1) EP1029360A4 (fr)
JP (1) JP2001516148A (fr)
KR (1) KR100593567B1 (fr)
AU (1) AU9197698A (fr)
WO (1) WO1999009599A2 (fr)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001514449A (ja) * 1997-08-22 2001-09-11 キュービック・メモリー・インコーポレーテッド 熱伝導性エポキシプリフォームによるシリコンセグメントの垂直相互接続方法
US7215018B2 (en) 2004-04-13 2007-05-08 Vertical Circuits, Inc. Stacked die BGA or LGA component assembly
US7705432B2 (en) * 2004-04-13 2010-04-27 Vertical Circuits, Inc. Three dimensional six surface conformal die coating
US7245021B2 (en) 2004-04-13 2007-07-17 Vertical Circuits, Inc. Micropede stacked die component assembly
US8723332B2 (en) 2007-06-11 2014-05-13 Invensas Corporation Electrically interconnected stacked die assemblies
WO2009035849A2 (fr) 2007-09-10 2009-03-19 Vertical Circuits, Inc. Montage de puce semiconductrice au moyen d'un revetement enrobant
CN101999167B (zh) 2008-03-12 2013-07-17 伊文萨思公司 支撑安装的电互连管芯组件
US7863159B2 (en) 2008-06-19 2011-01-04 Vertical Circuits, Inc. Semiconductor die separation method
US9153517B2 (en) 2008-05-20 2015-10-06 Invensas Corporation Electrical connector between die pad and z-interconnect for stacked die assemblies
WO2010151578A2 (fr) 2009-06-26 2010-12-29 Vertical Circuits, Inc. Interconnexion électrique pour puce empilée dans une configuration en zigzag
WO2011056668A2 (fr) 2009-10-27 2011-05-12 Vertical Circuits, Inc. Procédé additif à isolation électrique de puce sélectif
TWI544604B (zh) 2009-11-04 2016-08-01 英維瑟斯公司 具有降低應力電互連的堆疊晶粒總成
KR101887084B1 (ko) 2011-09-22 2018-08-10 삼성전자주식회사 멀티-칩 반도체 패키지 및 그 형성 방법
US9871019B2 (en) 2015-07-17 2018-01-16 Invensas Corporation Flipped die stack assemblies with leadframe interconnects
US9825002B2 (en) 2015-07-17 2017-11-21 Invensas Corporation Flipped die stack
US9490195B1 (en) 2015-07-17 2016-11-08 Invensas Corporation Wafer-level flipped die stacks with leadframes or metal foil interconnects
US9508691B1 (en) 2015-12-16 2016-11-29 Invensas Corporation Flipped die stacks with multiple rows of leadframe interconnects
US10566310B2 (en) 2016-04-11 2020-02-18 Invensas Corporation Microelectronic packages having stacked die and wire bond interconnects
US9595511B1 (en) 2016-05-12 2017-03-14 Invensas Corporation Microelectronic packages and assemblies with improved flyby signaling operation
US9728524B1 (en) 2016-06-30 2017-08-08 Invensas Corporation Enhanced density assembly having microelectronic packages mounted at substantial angle to board

Citations (2)

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Publication number Priority date Publication date Assignee Title
US4835593A (en) * 1986-05-07 1989-05-30 International Business Machines Corporation Multilayer thin film metallurgy for pin brazing
US5445994A (en) * 1994-04-11 1995-08-29 Micron Technology, Inc. Method for forming custom planar metal bonding pad connectors for semiconductor dice

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4877752A (en) * 1988-10-31 1989-10-31 The United States Of America As Represented By The Secretary Of The Army 3-D packaging of focal plane assemblies
US5657206A (en) * 1994-06-23 1997-08-12 Cubic Memory, Inc. Conductive epoxy flip-chip package and method
US5675180A (en) * 1994-06-23 1997-10-07 Cubic Memory, Inc. Vertical interconnect process for silicon segments
US5653019A (en) * 1995-08-31 1997-08-05 Regents Of The University Of California Repairable chip bonding/interconnect process

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4835593A (en) * 1986-05-07 1989-05-30 International Business Machines Corporation Multilayer thin film metallurgy for pin brazing
US5445994A (en) * 1994-04-11 1995-08-29 Micron Technology, Inc. Method for forming custom planar metal bonding pad connectors for semiconductor dice

Also Published As

Publication number Publication date
WO1999009599A2 (fr) 1999-02-25
AU9197698A (en) 1999-03-08
JP2001516148A (ja) 2001-09-25
EP1029360A2 (fr) 2000-08-23
KR20010022894A (ko) 2001-03-26
KR100593567B1 (ko) 2006-06-28
EP1029360A4 (fr) 2006-04-12

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