WO1999000904A8 - Interleaved differential analog-to-digital converter - Google Patents
Interleaved differential analog-to-digital converterInfo
- Publication number
- WO1999000904A8 WO1999000904A8 PCT/US1998/010835 US9810835W WO9900904A8 WO 1999000904 A8 WO1999000904 A8 WO 1999000904A8 US 9810835 W US9810835 W US 9810835W WO 9900904 A8 WO9900904 A8 WO 9900904A8
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- circuit
- converted
- analog
- conversion
- segment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
- H03M1/122—Shared using a single converter or a part thereof for multiple channels, e.g. a residue amplifier for multiple stages
- H03M1/1225—Shared using a single converter or a part thereof for multiple channels, e.g. a residue amplifier for multiple stages using time-division multiplexing
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
An interleaved differential analog-to-digital converter which allows differential analog-to-digital conversion of interleaved segments of two or more analog signals to be converted without loss of partial bits at the end of each conversion segment. The converter utilizes a separate feedback capacitor for each analog signal to be converted, together with a switch for switching the feedback capacitor into the circuit when the respective analog input is to be converted and for switching the respective capacitor out of the circuit when the respective analog input signal is not being converted. Thus, each feedback capacitor, when switched out of the circuit, will retain a charge representing whatever fraction of a bit remained thereon when switched out of the circuit, so that when switched back into the circuit, the conversion of the next respective analog signal segment may begin from that value of charge. Thus, loss of fractional bits at the end of the conversion of each segment is prevented. Various embodiments are described.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US88559097A | 1997-06-30 | 1997-06-30 | |
| US08/885,590 | 1997-06-30 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| WO1999000904A1 WO1999000904A1 (en) | 1999-01-07 |
| WO1999000904A8 true WO1999000904A8 (en) | 1999-04-15 |
| WO1999000904A9 WO1999000904A9 (en) | 1999-05-14 |
Family
ID=25387268
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US1998/010835 Ceased WO1999000904A1 (en) | 1997-06-30 | 1998-05-28 | Interleaved differential analog-to-digital converter |
Country Status (1)
| Country | Link |
|---|---|
| WO (1) | WO1999000904A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6261291B1 (en) | 1999-07-08 | 2001-07-17 | David J. Talaber | Orthopedic implant assembly |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07249989A (en) * | 1994-03-11 | 1995-09-26 | Yamaha Corp | Analog/digital converter |
| US5949360A (en) * | 1995-09-06 | 1999-09-07 | Yamaha Corporation | Analog/digital converter utilizing time-shared integrating circuitry |
-
1998
- 1998-05-28 WO PCT/US1998/010835 patent/WO1999000904A1/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| WO1999000904A1 (en) | 1999-01-07 |
| WO1999000904A9 (en) | 1999-05-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0571075A3 (en) | Analog to digital converter with autoranging offset. | |
| EP1006664A3 (en) | Digital analog converter and electronic device using the same | |
| DE3854484D1 (en) | Oversampling AD converter with an additional capacitor, switched synchronously with the switching of an input capacitor. | |
| WO2003023968A3 (en) | Low power cyclic a/d converter | |
| WO2001091303A3 (en) | Method and apparatus for use in switched capacitor systems | |
| ATE115341T1 (en) | DIGITAL TO ANALOG CONVERSION. | |
| MY114831A (en) | Receiver with sigma-delta analog-to-digital converter | |
| EP0351788A3 (en) | Analog-to-digital converting system | |
| EP0620652A3 (en) | Improved multiple slope analog-to-digital converter. | |
| WO2000035096A3 (en) | Analog-digital converter | |
| WO2001011787A3 (en) | Sigma-delta a/d converter | |
| WO1999048202A3 (en) | Converter with programmable gain control | |
| WO2001050744A8 (en) | Hdtv receiver having fast digital if agc and analog rf agc | |
| WO2006051212A3 (en) | Symmetrical time/voltage conversion circuit | |
| CA2092482A1 (en) | Multistage switching facility for optical signals | |
| WO1999000904A8 (en) | Interleaved differential analog-to-digital converter | |
| WO1997009788A3 (en) | A/d conversion with folding and interpolation | |
| KR950035459A (en) | Dual Input Analog-to-Digital Converter Using Single Converter Module | |
| AU3782095A (en) | An analog to digital converter circuit | |
| EP0516025A3 (en) | Low voltage d.c. to d.c. converter | |
| AU7181898A (en) | Multi-anode time to digital converter | |
| WO2002047273A3 (en) | Analog-to-digital converter and method for converting an analog signal into a digital signal | |
| WO1987006080A3 (en) | Analog/digital converter apparatus for quantizing transmittance voltage signals | |
| JPS5563124A (en) | D-a converter circuit | |
| EP0195502A3 (en) | A/d converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| AK | Designated states |
Kind code of ref document: A1 Designated state(s): JP KR |
|
| AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
| DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
| AK | Designated states |
Kind code of ref document: C1 Designated state(s): JP KR |
|
| AL | Designated countries for regional patents |
Kind code of ref document: C1 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
| CFP | Corrected version of a pamphlet front page | ||
| CR1 | Correction of entry in section i |
Free format text: PAT. BUL. 01/99 UNDER (54) THE TITLE IN ENGLISH SHOULD READ "INTERLEAVED DIFFERENTIAL ANALOG-TO-DIGITAL CONVERTER" |
|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
| AK | Designated states |
Kind code of ref document: C2 Designated state(s): JP KR |
|
| AL | Designated countries for regional patents |
Kind code of ref document: C2 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
| COP | Corrected version of pamphlet |
Free format text: PAGES 1/4-4/4, DRAWINGS, REPLACED BY NEW PAGES 1/4-4/4; DUE TO LATE TRANSMITTAL BY THE RECEIVING OFFICE |
|
| NENP | Non-entry into the national phase in: |
Ref country code: JP Ref document number: 1999509793 Format of ref document f/p: F |
|
| 122 | Ep: pct application non-entry in european phase |