WO1999000828A1 - Method of manufacturing semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device, comprising the photolithographic step wherein an exposure distortion measurement mark comprising a pattern which produces approximately the same misalignment as that produced by a pattern formed by an optical reduction projection aligner is formed on a sample by the optical reduction projection aligner and, by using the exposure distortion measurement mark, the distortion produced by the optical reduction projection aligner is determined and, when the pattern is exposed by an electron beam lithographic system, the distortion is corrected.

Description

Description ^: Semiconductor device manufacturing method

 The present invention relates to a technique for forming a pattern using a lithography technique in a semiconductor device manufacturing process. Background art

 When a desired pattern is formed on a semiconductor wafer, a method has been known in which an optical reduction projection exposure apparatus and an electron beam lithography apparatus are used in combination. In order to achieve ultra-fine pattern formation, for example, gate electrodes, contact holes, and the like of each semiconductor element are drawn by an electron beam drawing apparatus, and the other portions are exposed by a light reduction projection exposure apparatus.

 In this case, since exposure by the light reduction projection exposure apparatus cannot avoid image distortion caused by the lens, it is necessary to perform drawing by the electron beam lithography apparatus after performing correction in accordance with the image distortion. -More specifically, a plurality of exposure distortion marks are formed on a sample using a light reduction projection exposure apparatus, and the amount of exposure distortion is determined in advance by measuring the position of the exposure distortion measurement mark using an electron beam lithography apparatus. In addition, when a desired pattern is drawn by an electron beam drawing apparatus, correction according to the exposure distortion is performed.

This type of technology is disclosed in, for example, Japanese Patent Application Laid-Open Nos. Sho 62-58621, Sho 62-129129, and Hei 11-191416. Description Have been.

 However, it has been pointed out that in the above-mentioned pattern forming method, the adverse effects due to the coma (Coma) aberration of the lens cannot be ignored with the recent trend toward further ultrafine patterning.

 That is, the present inventors have found that the lens aberration has a pattern dependency, and the pattern of wiring and the like in the semiconductor element formed by the optical reduction projection exposure apparatus (hereinafter referred to as the actual element pattern as necessary). It is confirmed that the actual element pattern itself and the alignment mark (chip mark) formed near the actual element pattern are relatively displaced by the influence of coma aberration. Was done.

 In such a case, it is inevitable that the actual element pattern itself will be distorted, and even if the actual elements are aligned based on the information of the alignment marks, the alignment will be shifted.

 The present invention has been made in view of such circumstances, and an object of the present invention is to provide a fine pattern forming method capable of performing accurate alignment without being affected by lens aberration. DISCLOSURE OF THE INVENTION-Among the inventions disclosed in the present application, typical ones are briefly described as follows.

A plurality of exposure distortion measurement marks are formed on a sample by a light reduction projection exposure apparatus, the positions of the exposure distortion measurement marks are measured, and the amount of exposure distortion by the light reduction projection exposure apparatus is determined in advance. In the fine pattern forming method for correcting the above-described calculated exposure distortion when drawing a desired pattern on a semiconductor wafer by using an electron beam lithography apparatus, the exposure distortion measurement may be performed. The use mark is formed in a pattern substantially the same as the actual element pattern formed by the optical reduction projection exposure apparatus.

 In the fine pattern forming method configured as described above, when the amount of exposure distortion is obtained based on the exposure distortion measurement mark, the same effect as the lens aberration received by the actual element pattern is obtained. This is because lens aberration has a pattern dependency, and similar distortion occurs when the patterns are almost the same.

 Therefore, since the measured exposure distortion amount reflects the effect of the lens aberration on the actual element pattern, the correction based on the exposure distortion amount can be corrected without being affected by the lens aberration.

 Further, the present invention provides that, in the electron beam drawing step, a chip mark for drawing by an electron beam drawing apparatus is formed in a pattern substantially the same as an actual element pattern formed by the optical reduction projection exposure apparatus. It is a characteristic.

In such a fine pattern forming method, the chip mark is affected by the lens aberration as in the actual element pattern. In other words, the deviation between the actual element pattern and the chip mark becomes almost the same, and when the electron beam lithography apparatus is used to draw on the actual element pattern based on the chip mark, it is possible to draw at an accurate position. become able to. A step of forming a first pattern on a semiconductor substrate by using a light reduction projection exposure apparatus; and forming a second pattern by using an electron beam lithography apparatus on the semiconductor substrate on which the first pattern is formed. Forming a third pattern on the semiconductor substrate on which the second pattern is formed, using a light reduction projection exposure apparatus; and forming a third pattern on the semiconductor substrate on which the third pattern is formed. A method of manufacturing a semiconductor device, comprising: forming a fourth pattern using an electron beam lithography apparatus, wherein the step of forming the second pattern comprises: When the first pattern is formed, the amount of misregistration generated in the first pattern due to the light reduction projection exposure apparatus is corrected, and when the fourth pattern is formed, the third pattern is corrected. When forming a pattern, the pattern is corrected so as to correct a position shift amount different from the position shift amount generated in the first pattern caused in the third pattern due to the light reduction projection exposure apparatus. A method for manufacturing a semiconductor device characterized by drawing.

 In the semiconductor device manufactured in such a process, the pattern displacement caused by the optical reduction projection exposure apparatus is appropriately corrected in the electron beam drawing process, so that a pattern with good accuracy can be formed. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a view showing an example of an exposure distortion measurement mark of the optical reduction projection exposure apparatus, FIG. 2 is a flowchart showing an example of measurement of exposure distortion of the optical reduction projection exposure apparatus, and FIG. FIG. 4 is a plan view showing an embodiment of a mask used for measuring the exposure distortion of the optical reduction projection exposure apparatus. FIG. 4 shows that the distortion of the mask used for measuring the exposure distortion of the optical reduction projection exposure apparatus is measured. Fig. 5 is an explanatory diagram showing various light sources in the optical reduction projection exposure apparatus, and Fig. 6 shows that the pattern misalignment differs depending on the various light sources in the optical reduction projection exposure apparatus. FIG. 7, FIG. 7 is an explanatory view showing an embodiment of exposure in a light reduction projection exposure apparatus, FIG. 8 is a flowchart showing an embodiment of a drawing process by an electron beam lithography apparatus, and FIG. Explanatory drawing of a specific example of an actual element pattern, FIG. FIG. 11 is an explanatory view of another specific example of a child pattern. FIG. 11 is an explanatory view of an embodiment showing a relationship between an actual element pattern and a get mark. Best Mode for Carrying Out the Invention Hereinafter, an embodiment of a lithography process in a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.

 The lithographic process of the present invention comprises the steps of exposure by a light reduction projection exposure apparatus and drawing by an electron beam lithography apparatus, and these steps will be sequentially described below.

 Measurement of exposure distortion of light reduction projection exposure equipment

 As shown in the flow chart shown in FIG. 2, first, a target mark (exposure distortion measurement mark) in which a plurality of transfer position measurement patterns are arranged within one shot of exposure is transferred to a wafer (step 1).

 That is, FIG. 3 shows a mask 33 on which the evening get mark 31 has been drawn. This mask 33 is, for example, (:: one semiconductor chip (usually, two to three chips for one exposure shot). The chip pattern is transferred).

 The evening get masks 31 are formed scattered on the surface of the mask, and their outer contours are formed, for example, in a cross shape, and extend in a vertical direction, for example, as shown in FIG. It is composed of a set of line segments arranged in the horizontal direction;

 In this case, each line segment has the same (or substantially the same) pattern and pitch interval as the pattern of the wiring layer group of the semiconductor device to be formed later using the same optical reduction exposure apparatus.

From this fact, when there is a group of wiring layers extending in the horizontal direction and arranged in the vertical direction in the semiconductor device to be formed later using the same optical reduction projection exposure apparatus, the target is used. The mark has the same (or substantially the same) pitch interval as that of the wiring layer group in which each line segment constituting the mark extends in the horizontal direction and extends in the vertical direction. In short, when forming various wiring layers in a semiconductor device, the patterns (directions, widths, and pitches) vary, so it is necessary to correct the coma caused by each pattern. In such a case, the above-described mask corresponding to those patterns is required.

 In this case, it goes without saying that separate masks may be formed in accordance with the evening get marks of various patterns, and it is also possible that the evening get marks composed of various patterns may be present in one mask. Of course. In the latter case, if the position of the evening mark of each pattern is previously confirmed, the exposure distortion of the evening mark of the same pattern can be determined particularly.

 Then, the image transferred to the wafer via such a mask 33 is distorted by the lens aberration of the optically-attenuated projection exposure apparatus, and in response to this distortion, each target mark is changed as shown in FIG. The design position (indicated by the solid line 41) or the squeeze shape (indicated by the solid line 45) is misaligned and transferred.

 In this case, since the deviation due to coma among the distortions has the pattern dependence as described above, each evening get mark 31 has its pattern (the direction and width of the line segment). , And pitch), the image is transferred.

 Then, as shown in step 2 of FIG. 2, the position (center) of the transferred target mark is measured using a position coordinate measuring device or an electron beam drawing device, and the position information is Store it in the evening position distortion database as shown in step 3.

Here, the obtained information has a characteristic that it includes distortion due to coma aberration according to the pattern of the transferred target mark. Therefore, it is used later as correction information when drawing using an electron beam drawing apparatus.

 It should be noted that, even if only one light reduction projection exposure apparatus is used, the light reduction projection exposure apparatus is generally configured to be able to switch a plurality of light sources in accordance with the resolution. FIGS. 5 (a), (b), and (c) show various light sources, where 51 is a light-shielding portion, and 53 is an illumination light emitting portion.

 In this case, it has been confirmed that the degree of coma aberration differs for each light source, and the shift of the turn position differs. FIG. 6 is a graph showing the situation, and FIG. 6 (a) shows the case of an isolated pattern, and FIG. 6 (b) shows the case of a line / space pattern. The lighting shapes a, b, c

These correspond to (a), (b) and (c) in Fig. 5, respectively.

 From this fact, while confirming what the light source is when forming an actual element pattern to be subjected to coma aberration correction at the time of writing by the electron beam lithography apparatus, the light source was determined according to the light source (ie, using the same light source). ) It is necessary to secure the above information.

 Exposure by light reduction projection exposure equipment

 The actual device pattern is transferred to the wafer. In this case, the actual element pattern is sequentially formed for each layer, but here, the actual element pattern transferred together with the chip mark which needs to be detected in the subsequent process when drawing by the electron beam lithography apparatus will be described. I do.

 FIG. 7 (a) shows the actual element patterns 73 transferred to the wafer 71, and FIG. 7 (b) shows details of each actual element pattern # 3.

This real element pattern 73 has a memory cell part 73 A at the center and a peripheral circuit part 73 B around it, and one of the wiring layers formed on it is dense and the other is sparse. Are formed in different patterns. Then, two chip marks 75 A and 75 B are formed at, for example, four corners around the actual element pattern 73.

 Each of these chip marks 75A and 75B is formed by a set of line segments as shown in Fig. 1, and one of the two chip marks at each corner 75A is The direction, width, and pitch are the same (or substantially the same) as the wiring layer group of the memory cell portion 73A, and the other chip mark 75B is the same as the wiring layer group of the peripheral circuit portion 73B. The directions, widths, and pitches are the same (or substantially the same).

 A wafer mark 77 is formed around the wafer 71 on which such actual element patterns 73 are formed. The wafer mark 77 is, for example, as shown in FIG. Instead of a pattern composed of such a collection of line segments, a conventional thick pattern may be used.

 Drawing by electron beam drawing equipment

 As shown in FIG. 8, first, the wafer is positioned with respect to an electron beam lithography apparatus (step 1).

 That is, the wafer mark 77 of the wafer 71 mounted on the X-y stage is detected, and based on the position of the detected wafer mark 77, the wafer mark 77 is moved in each of the x, y, and 方向 directions of the X-y stage. The wafer 71 is moved to a proper position by moving the wafer 71 by a predetermined amount.

 Next, the position (center) is detected by detecting the chip marks 75A and 75B using a position coordinate measuring device or an electron beam drawing device (Step 2).

Then, distortion-correction drawing data is obtained based on the positions of the detected chip marks 75A and 75B (step 3). However, the distortion-correction drawing data is obtained as shown in FIG. The pattern position pattern obtained in step 3 The information is created from the information stored in the foot database (step 4) and the drawing patterns prepared beforehand (step 5).

 In this case, the information stored in the pattern position shift base is information including coma having pattern dependence as described above. From this, the distortion correction data obtained through the mask on which the target mark of the actual element pattern 73, for example, the same (or substantially the same) as the pattern of the memory cell portion 73A is drawn, is selected. By creating the corrected drawing data, it is possible to obtain a corrected drawing data in which the influence of coma is not seen at all.

 The reason is that in the pattern of FIG. 7 (b), even if the position of the memory cell portion 73A is misaligned due to coma aberration, the chip mark 75A formed in the same pattern This is because the position shift of the memory cell portion 73A is considered not to be shifted from the reference chip mark 75A because the position shift is completely the same.

 The distortion due to the coma of the pattern of the memory cell portion 73A itself is obtained by measuring the amount of distortion obtained through a mask on which the same target mask is drawn (or substantially the same) as the pattern. This is because the correction can be made. 'Thereafter, pattern drawing is performed by an electron beam drawing device based on the corrected drawing data (step 6). It goes without saying that a pattern can be accurately drawn at a predetermined position in the memory cell portion without being affected by distortion due to coma aberration.

The above-described embodiment shows a case in which the coma aberration due to the pattern mainly composed of the wiring layer is corrected. However, it is needless to say that the present invention is not limited to the wiring layer group. For example, if the actual element pattern includes a pattern as shown in Fig. 11 (a), the evening target mark 31 or chip mark 75A (or 7 5B) may be used.

 That is, in the pattern shown in FIG. 3A, a plurality of cells 110 arranged in a matrix are arranged such that their centers are spaced apart by a in the horizontal direction and b in the vertical direction. On the other hand, in the mark shown in Fig. 2 (b), the outer contour has a cross shape, and the line segments extending in the vertical direction are arranged at intervals of a, and the line segments extending in the horizontal direction are s. Are arranged at intervals of b.

 In such a mark, the distortion caused by the coma aberration in the horizontal direction (a) can be read by scanning the electron beam in the horizontal direction, and the mark in the vertical direction (b) can be read by scanning the electron beam in the vertical direction. The distortion due to coma can be read.

 From this, it is apparent that the pattern of the evening get mark 31 or the chip mark 75A (or 75B) does not necessarily have to be almost the same as the actual element pattern.

 The point is that the pattern of the target mark 31 is shifted such that the positional shift caused by the coma of the lens of the optical reduction projection exposure apparatus is almost the same as the actual element pattern formed by the optical reduction projection exposure apparatus. Thus, the effect of the present invention can be sufficiently achieved.

 Similarly, the position of the chip mark pattern at the time of drawing by the electron beam lithography apparatus is substantially the same as the position shift of the actual element pattern formed at that time due to the positional deviation caused by the coma of the lens of the optical reduction projection exposure apparatus. With such a configuration, the coin of the present invention can be sufficiently achieved.

Similarly, the pattern of the chip mark at the time of drawing by the electron beam drawing apparatus is displaced by the positional deviation caused by the coma aberration of the lens of the optical reduction projection exposure apparatus. The effect of the present invention can be sufficiently achieved by configuring so as to be substantially the same as the displacement of the actual element pattern formed in the above.

 Similarly, the position of the chip mark pattern at the time of drawing by the electron beam lithography apparatus is substantially the same as the position shift of the actual element pattern formed at that time due to the positional deviation caused by the coma of the lens of the optical reduction projection exposure apparatus. Thus, the effect of the present invention can be sufficiently achieved.

 Specific example of actual device pattern and explanation of evening get pattern

 FIG. 9 is a diagram showing a planar shape of a pattern of a memory cell group in which a plurality of memory cells are arranged in a dynamic RAM.

 In the figure, the word line 92 is arranged in the Y direction and the data line 93 is arranged in the X direction. The lower electrode 94 of the crown-shaped capacitor is formed above the word line and the data line. Have been.

 On the active region 90 in the gap between the lead wires 92, a plug electrode 94 whose longitudinal direction is the y direction is in contact with the active region 90 and extends to a region other than the active region. The data line 93 is arranged so as to partially overlap the plug electrode 94.

 Further, an opening 95 is formed on the active region 90, and the lower electrode 94 of the capacity is connected through the opening. Here, an electron beam lithography apparatus was used for forming the openings 95, and a light reduction projection exposure apparatus was used for the other layers. The openings 95 were aligned with a chip mark formed of the word line 92 layer.

 Specifically, the chip mark was formed by a pattern group including the information of the guide line pattern as shown in FIG.

In this case, since the word line has a pattern width of 0.35 micron and a pattern pitch of 0.7 micron, the pattern is arranged under the same conditions. For the lines, the pattern width was 0.35 microns, the pattern interval was 0.35 microns, and seven lines were used, and the pattern group width 11 was 4.55 microns. The patterns were arranged such that the center position of the pattern group was at a predetermined position. The horizontal lines of the crosshairs consisted of vertical lines with a 0.35 micron pattern, and the width 12 was 4.6 microns.

 The pattern position was detected by scanning and irradiating an electron beam and detecting the reflected locality in a digital display to recognize the position. In this case, the scanning width of the electron beam scanning may be arbitrarily set in the X direction, but must be set as large as possible in the y direction so that information of a plurality of line segments can be recognized.

 The misalignment caused by the coma aberration of the evening get mark showed almost the same tendency as that of the guide line pattern, and the misalignment was greatly improved.

 FIG. 10 (a) is a plan layout diagram of a circuit according to another embodiment. The circuit diagram is shown in FIG.

 The source / drain regions of Ql and Q7 of the n-type transistor (NMOS) are connected to each other and connected to the input of the CMOS amplifier (complementary MOS circuit) as an output amplifier.

 The gate of Q1 is connected to the control signal input terminal C, and the gate of Q7 is connected to the inverted signal from terminal C through the entire circuit.

 After one of the-signals input to the input terminals X and Y of the source / drain regions of Q 1 and Q 7 is selected by the control signal input to the terminal C and inverted and output amplified by the receiver overnight, The signal is output to the OUT terminal. It is known that a logic circuit combining the basic gate of the pass transistor has a smaller area and operates at a higher speed than a logic circuit combining a normal CMOS NAND or the like.

As shown in the figure (a), the layout of each function pattern is as follows: 101 is an element isolation region, 102 is an n (+) source / drain region, and 103 is a p (+) source / drain. A rain region, 104 indicates a gate electrode, 105 indicates a contact hole, and 106 indicates a first-layer metal wiring.

 In this case, the element isolation region, n (+) source / drain region and p (+) source / drain region, contact hole, and first-layer metal wiring were formed by using a light reduction projection exposure apparatus.

 An electron beam lithography apparatus was used to form the gate electrode. This is because the dimensions of the gate electrode pattern are finer than other patterns, and it is difficult to form them by the reduced projection exposure method.

 The chip mark used for forming the gate electrode was formed simultaneously with the n (+) source / drain region and the p (+) source / drain region.

 As a result, the alignment between the source / drain regions and the gate electrode was successfully performed, and the alignment with other patterns was also excellent.

 In the above-described embodiment, the target mark and the chip mark have a cross-shaped outer contour, but are not necessarily limited to such shapes. For example, it is needless to say that the center of the electron beam can be specified by scanning the electron beam in the X and y directions.

 Further, the above-described embodiment describes that the electron beam lithography can be accurately performed at a predetermined position when the optical reduction projection exposure apparatus and the electron beam lithography apparatus are used in combination.

However, even if an electron beam lithography apparatus is not used, even in mask alignment in a light reduction projection exposure apparatus, the present invention can be applied to accurate alignment without adverse effects of coma aberration. Needless to say. Industrial applicability

 INDUSTRIAL APPLICABILITY The present invention enables accurate alignment without being affected by coma, and can be used for manufacturing a semiconductor device that forms a fine pattern.

Claims

The scope of the claims 1. exposing the first pattern formed on the mask using a light reduction projection exposure apparatus to transfer the pattern onto a semiconductor substrate; and applying an electron beam lithography apparatus to the semiconductor substrate onto which the first pattern has been transferred. A method of manufacturing a semiconductor device including a step of forming a second pattern by using  The optical reduction projection is performed by transferring an exposure distortion measurement mark on the sample using the optical reduction projection exposure apparatus so as to cause a positional shift substantially equal to the positional shift amount generated when the first pattern is transferred. A method of manufacturing a semiconductor device, comprising: determining an amount of exposure distortion caused by an exposure device; and correcting the amount of exposure distortion when writing the second pattern.  2. The first pattern includes a line-and-space pattern, and the exposure distortion measurement mark is a set of line segments having substantially the same direction, width, and pitch as the pattern constituting the line-and-space pattern. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device includes a body. 3. In the step of forming the first pattern, the alignment mark used for forming a pattern on the semiconductor substrate after the formation of the first pattern is generated in the first pattern due to the light reduction projection exposure apparatus. 2. The method for manufacturing a semiconductor device according to claim 1, wherein a mark is formed such that the position shift is substantially the same as the position shift.  4. The method of manufacturing a semiconductor device according to claim 1, wherein a chip mark at the time of writing by the electron beam writing apparatus is formed in a pattern having a pitch substantially equal to the first pattern. 5. a step of forming a first pattern on the semiconductor substrate using an optical reduction projection exposure apparatus, and an electron beam drawing on the semiconductor substrate on which the first pattern has been formed. Forming a second pattern using an image forming apparatus, forming a third pattern using a light reduction projection exposure apparatus on the semiconductor substrate on which the second pattern has been formed, A method of manufacturing a semiconductor device, comprising: forming a fourth pattern on a formed semiconductor substrate using an electron beam lithography apparatus, wherein the step of forming the second pattern includes the step of: When forming, the position shift amount caused in the first pattern due to the light reduction projection exposure apparatus is corrected, and when forming the fourth pattern, when forming the third pattern, A semiconductor device, wherein a pattern is drawn so as to correct a displacement amount different from a displacement amount generated in the first pattern caused in the third pattern due to the light reduction projection exposure apparatus. Manufacturing method.  6-The amount of misregistration generated in the first pattern is obtained by using a first exposure distortion measuring mark, and the amount of misregistration generated in the third pattern is determined by the first exposure. 6. The method for manufacturing a semiconductor device according to claim 5, wherein the determination is performed using a second exposure distortion measurement mark different from the distortion measurement mark.  7. The first distortion measurement mark is a mark having substantially the same pitch as the pattern constituting the first pattern, and the second distortion measurement mark is a mark having the third pattern. 7. The method for manufacturing a semiconductor device according to claim 6, wherein the mark has a pitch substantially the same as a pattern constituting the pattern.  8-The semiconductor device according to claim 5, wherein a pitch of a chip mark used for writing the second pattern is different from a pitch of the chip mark used for writing the fourth pattern. Manufacturing method. 9.Expand the light on the mask with the line and space pattern Exposing with an optical device to form a wiring layer pattern on a semiconductor substrate; and subjecting the mask on which a strain measurement mark including an aggregate of line segments having substantially the same pitch as the line and space pattern is formed to the optical reduction projection exposure Exposing with an apparatus to form the distortion measurement mark on the sample, and measuring the amount of distortion by the light reduction projection exposure apparatus;  Drawing a contact hole pattern with the wiring layer on the semiconductor substrate on which the wiring layer is formed using an electron beam drawing apparatus; A method of drawing a pattern using the electron beam drawing apparatus, wherein drawing is performed so as to correct the amount of distortion measured using the distortion measurement mark. Semiconductor device manufacturing method.