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WO1998012568A1 - Process for producing semiconductor device and semiconductor device - Google Patents

Process for producing semiconductor device and semiconductor device Download PDF

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Publication number
WO1998012568A1
WO1998012568A1 PCT/JP1997/000095 JP9700095W WO9812568A1 WO 1998012568 A1 WO1998012568 A1 WO 1998012568A1 JP 9700095 W JP9700095 W JP 9700095W WO 9812568 A1 WO9812568 A1 WO 9812568A1
Authority
WO
WIPO (PCT)
Prior art keywords
inspection
bare chip
bonding wire
bonding
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP1997/000095
Other languages
French (fr)
Japanese (ja)
Inventor
Osamu Horiuchi
Toshihiro Tsuboi
Hirotaka Nishizawa
Masataka Murata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Solutions Technology Ltd
Original Assignee
Hitachi ULSI Engineering Corp
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi ULSI Engineering Corp, Hitachi Ltd filed Critical Hitachi ULSI Engineering Corp
Priority to TW086101501A priority Critical patent/TW360911B/en
Publication of WO1998012568A1 publication Critical patent/WO1998012568A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/04—Housings; Supporting members; Arrangements of terminals
    • G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
    • G01R1/0433—Sockets for IC's or transistors
    • G01R1/0483—Sockets for un-leaded IC's having matrix type contact fields, e.g. BGA or PGA devices; Sockets for unpackaged, naked chips
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    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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Definitions

  • the present invention relates to a semiconductor device manufacturing technique, and more particularly, to a semiconductor device manufacturing method and a semiconductor device in which an inspection is performed in advance to obtain a good quality chip.
  • a bare chip that is, a non-defective product, in which the packaging density is greatly improved as compared with packaging using a packaged product due to the higher integration of a semiconductor integrated circuit.
  • Semiconductor devices mounted with a bare chip (KGD: Known Good Die) using IE and a technology using a stacked general-purpose memory module that modularizes this semiconductor device are considered to be effective in the future.
  • a burn-in board is mounted on a burn-in board using a test chip carrier and a burn-in socket. Screening tests are performed by storing the burn-in in a chamber.
  • the mainstream is to take out a bare chip from a bare chip carrier after a screening test and obtain a KGD.
  • the bare chip carrier can be connected to the bare chip by a method in which a bare chip pad (device electrode) is pressed against a bump (connection terminal) of an element supporting substrate that supports the bare chip carrier, and an electrical connection is made.
  • a method of connecting the bumps of the element support substrate and the pads of the base by wire bonding There are two methods, a method of connecting the bumps of the element support substrate and the pads of the base by wire bonding.
  • a bare chip carrier is fixed on a bare chip carrier using a thermosetting adhesive, a thermoplastic adhesive, an adhesive film, or a silicone gel, and then the bare chip carrier and the bare chip are bonded by wire bonding. And are electrically connected. Furthermore, after sorting and aging, the bonding wire is melted by etching or removed by mechanical engraving, and then the bare chip carrier is heated to remove the bare chip from the bare chip carrier to obtain a KGD.
  • Japanese Patent Application Laid-Open No. Hei 8-124980 discloses that a bonding wire is melted by etching and removed from the pad, or gold or solder is used for the bonding wire and these are melted by heat. It describes how to form bumps for compress electrodes.
  • a thin aluminum wire is used as a bonding wire, and a bonding crimping area having a small crimping area is used to bond the end of the pad.
  • a technique for weakening the bonding conditions and, as a result, mechanically separating the bonding wire from the pad by pulling the bonding wire.
  • the bare chip is fixed to the bare chip carrier using a thermoplastic adhesive
  • the bare chip is heated to a high temperature during bonding or aging.
  • a thermosetting adhesive is used, it is difficult to remove the bare chip from the bare chip carrier after aging.
  • the adhesive remains on the bare chips after obtaining the KGD, so that after the bare chips are commercialized, cracks occur due to reduced adhesion to the sealing resin.
  • the problem is that it has an adverse effect on the reliability of the system.
  • Japanese Unexamined Patent Application Publication No. Hei 8-124980 discloses a method of removing bonding bonds after aging, a method by etching using an acid, or a method of immersing ripened solder during melting. Describes how to melt the gold wire by heating, but there are concerns about reliability issues such as residual solvent on bare chips, adhesion of foreign matter, or cracking of bare chips due to heat, and the need for manufacturing equipment and facilities Therefore, investment cost and increase in bare chip unit cost are problematic.
  • U.S. Pat.No. 5,173,451 discloses that wire bonding at the time of aging is carried out by bonding, and in this case, a thin bonding wire is used, and the bonding area of the bonding wedge is reduced. By bonding to the end of the pad at the time of aging, and bonding to avoid the indentation of the bonding at the time of aging when bonding the wire as a product after obtaining KGD Is described.
  • the method for mechanically pulling the wire is described as a method for removing the wire Force ⁇ Since the bare chip is placed above the bare chip carrier, the wire is fixed by any method and is not pulled upward.
  • the problem is that it is difficult to remove the wires all at once, and it is also a problem that it takes time to remove the wires one by one, leading to cost increase.
  • an object of the present invention is to provide a method of manufacturing a semiconductor device and a semiconductor device for obtaining KGD having high performance and high reliability at low cost and in a stable manner. It is another object of the present invention to provide a method of manufacturing a semiconductor device and a semiconductor device which can easily obtain KGD having high performance and high reliability.
  • an element supporting substrate having a through hole formed therein and having connection terminals provided on a first main surface around the through hole.
  • the bare chip when the bare chip is separated from the bonding wire for inspection after the inspection, the vicinity of the wire bonding portion on the substrate is fixed and separated, so that the bare chip and the bonding wire for testing are separated at or near the element side wire bonding portion. Can be separated.
  • the element-side wire bonding portion of the bonding wire for inspection remains on the element electrode of the bare chip. The two are separated so that they do not separate.
  • the method of manufacturing a semiconductor device further includes a step of disposing a bare chip on a chip supporting portion of an element supporting substrate in which a poor hole is formed in the center and connection terminals are provided around the through hole.
  • the semiconductor device of the present invention is a semiconductor device on which a bare chip that has been subjected to an electrical inspection in advance and is selected as a non-defective product is mounted, and that an inspection bonder passed through a through hole of an element supporting substrate used for the inspection is provided. After performing the inspection by connecting the bare chip and the element supporting substrate with a bonding wire, the vicinity of the base-side wire bonding portion of the bonding wire for inspection is fixed to connect the bare chip and the bonding wire for inspection. One or more bare chips obtained separately are mounted, and the bare chip and the bonding wire for inspection are not left on the device electrode of the base without leaving the element-side wire bonding portion of the bonding wire for inspection.
  • the lead portion of the device mounting member or the lead portion of the mounting board is electrically connected to the device electrode.
  • the element-side wire bonding portion is left on the device electrode of the bay chip to separate the bare chip and the bonding wire for inspection, the bare chip and the inspection bonding wire are separated from the lead portion via the element-side wire bonding portion.
  • the device electrodes are electrically connected.
  • FIG. 1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention.
  • FIG. 2 is a plan view showing a structure of an element supporting member used in a method of manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 3 is a partial cross-sectional view showing the structure of a bare chip carrier used in the method for manufacturing a semiconductor device according to the first embodiment.
  • FIGS. 4 (a), 4 (b), and 4 (c) are diagrams showing a method for manufacturing the semiconductor device according to the first embodiment.
  • FIGS. 1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention.
  • FIG. 2 is a plan view showing a structure of an element supporting member used in a method of manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 3 is a partial cross-sectional view showing the structure of a bare chip carrier used in the method for manufacturing a semiconductor device according
  • FIGS. 4A and 4B are diagrams showing a bonding method between a bonding wire for inspection and a bare chip in the method, in which (a) and (b) are partial sectional views, (c) is an enlarged partial plan view,
  • FIG. 5 is a cross-sectional view showing a method of separating a bonding wire for inspection and a bare chip in the method of manufacturing a semiconductor device according to the first embodiment.
  • FIG. 6 is a sectional view showing a method of manufacturing the bonding device according to the first embodiment.
  • FIG. 7 is an enlarged partial plan view showing the structure of the bare chip after being made,
  • FIG. 7 is a perspective view showing the structure of a burn-in board used in the method of manufacturing a semiconductor device according to the first embodiment, and FIGS.
  • FIG. 8 is a diagram showing a method for separating inspection bonding wires and bare chips in a semiconductor device manufacturing method according to a second embodiment of the present invention, wherein (a) is a partial cross-sectional view, and (b) is an enlarged partial plan view.
  • FIG. 9 is a partial cross-sectional view showing the structure of a semiconductor device according to the second embodiment of the present invention, and FIGS. 10A and 10B are inspections in the method of manufacturing the semiconductor device according to the third embodiment of the present invention.
  • Bonding wire for FIG. 11 is a cross-sectional view illustrating a method of separating a semiconductor device from a bare chip, FIG.
  • FIG. 11 is a cross-sectional view illustrating the structure of a semiconductor device according to a third embodiment of the present invention
  • FIG. 12 is a cross-sectional view illustrating the structure of the semiconductor device according to the fourth embodiment of the present invention.
  • FIG. 13 is a cross-sectional view showing a structure of a bare chip carrier used in a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention, an enlarged partial cross-sectional view showing a bonding state between a key and a bare chip
  • FIG. 15 is a cross-sectional view showing a method for separating a bonding wire for inspection and a bare chip in a method for manufacturing a semiconductor device according to the fifth embodiment.
  • FIG. 13 is a cross-sectional view showing a structure of a bare chip carrier used in a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention, an enlarged partial cross-sectional view showing a bonding state between a key and a bare chip
  • FIG. 16 is a sectional view showing a method for manufacturing a semiconductor device according to a sixth embodiment of the present invention.
  • FIG. 17 is a partial front view showing the bonding method used in the method for manufacturing a semiconductor device according to the sixth embodiment, and
  • FIG. 17 is a partial front view showing the structure of the bonding wedge.
  • a semiconductor device FIG. 19 is an enlarged partial plan view showing the structure of the bare chip obtained by the inspection in the method of manufacturing the semiconductor device according to the seventh embodiment.
  • FIG. 19 is an enlarged view showing the bonding state between the bare chip and the bonding wire obtained by the inspection in the method of manufacturing the semiconductor device according to the seventh embodiment.
  • FIG. 20 is an enlarged partial plan view showing a bonded state between a bare chip and a bonding wire obtained by inspection in the method of manufacturing a semiconductor device according to the seventh embodiment.
  • FIG. 21 is an embodiment of the present invention.
  • FIG. 22 is a cross-sectional view showing a method of separating the bonding wire for inspection and the bare chip in the method of manufacturing a semiconductor device according to the eighth embodiment.
  • FIG. 23 is a cross-sectional view showing a separation method.
  • FIG. Cross-sectional view illustrating the method for separating and flop, Bonn inspection in the manufacturing method of FIG. 2 4 is a semiconductor device of the eighth embodiment
  • FIG. 25 is a cross-sectional view showing a method for separating the bonding wire from the element supporting substrate.
  • FIG. 25 is a cross-sectional view showing a method for separating the bonding wire for inspection and the element supporting substrate in the method for manufacturing a semiconductor device according to the eighth embodiment. Is a cross-sectional view showing a method of separating a bonding wire for inspection and an element supporting substrate in the method of manufacturing a semiconductor device according to the eighth embodiment.
  • FIG. 27 is a flow chart showing a manufacturing procedure of the semiconductor device according to the ninth embodiment of the present invention.
  • FIG. 28 is a cross-sectional view illustrating a manufacturing procedure of the semiconductor device according to the ninth embodiment
  • FIG. 29 is a cross-sectional view illustrating the structure of the semiconductor device according to the ninth embodiment, and FIG. FIG.
  • FIG. 31 is a partial cross-sectional view showing a manufacturing procedure of the semiconductor device according to the tenth embodiment of the present invention
  • FIG. 31 is a partial cross-sectional view showing the structure of the semiconductor device according to the tenth embodiment of the present invention
  • FIG. Embodiment 11 Used in a manufacturing method of a semiconductor device according to Embodiment 11.
  • Plan view showing a structure of a child support substrate
  • Figure 3 3 is an enlarged planar view showing the structure of an element supporting substrate used in the method of manufacturing a semiconductor device according to Embodiment 1 1 embodiment.
  • FIG. 4 is a cross-sectional view showing the structure of the semiconductor device of FIG. 1, a plan view showing the structure of the element supporting member of FIG. 2, a partial cross-sectional view showing the structure of the bare chip carrier of FIG. Figure showing the bonding method between the bonding wire for inspection and bare chip
  • Figure 5 is a cross-sectional view showing the method for separating the bonding wire for inspection and bare chip
  • Figure 6 shows the structure of the bare chip after being separated from the bonding wire for inspection.
  • the burn-in board 3 of the first embodiment is used at the time of inspection when obtaining a good KGD.
  • the inspection is performed on the bare chip 1 (also referred to as a pellet), and is, for example, an aging test such as burn-in (various operation life tests also called a screening test) or a reliability test. It is also a screening test of 1.
  • burn-in various operation life tests also called a screening test
  • the burn-in board 3 is, for example, a board used for storing a large number of bare chips 1 in a chamber of a burn-in device for performing a screening test.
  • a plurality of bare chip carriers 18 are mounted on the burn-in board 3 via a socket 11, and the burn-in removes the bare chip 1 having an inherent defect and a potential defect factor. I have.
  • bare chip carrier 18 is connected to pad 1a (element electrode) on bare chip 1.
  • the lead 10 c (connection terminal) on the element support board 10 are electrically connected to each other, and are externally connected through the force connector 10 b, which is an external connection terminal on the element support board 10.
  • the pad 1a of the bare chip 1 and the lead 10c of the element supporting substrate 10 are made of aluminum by wire bonding. Or bonding wire for inspection made of gold, etc.
  • the bonding wire 4 for parentheses inspection is cuttable, and the element supporting substrate 10 has a structure that can be reused.
  • the bare chip carrier 18 is composed of a lower lid member 12 (one cover member), an upper lid member 15 and an element supporting board 10, and the bare chip 1 It is hermetically sealed by the lid member 12, the upper lid member 15, and the element supporting substrate 10, and has high airtightness.
  • the bare chip 1 is arranged on the chip supporting portion 10a so as to be aligned with the through hole 10d of the element supporting substrate 10, and in the bare chip carrier 18, the insulating sheet 14 is provided.
  • the base chip 1 is sandwiched between the element supporting substrate 10 and the lower lid member 12 via the base chip 1.
  • connection holes 10 e are formed at four places, and pin holes 13 e are formed in the connection holes 10 e as shown in FIG. Is embedded.
  • the bare chip carrier 18 can be assembled, disassembled, and reassembled by fitting the upper lid member 15 and the lower lid member 12 into the pin member 13 attached to the element supporting substrate 10. It has a structure.
  • the lower lid member 12 in the first embodiment has a box-like shape that covers the bare chip 1.
  • it is made of a resin such as BT resin or a metal material such as stainless steel.
  • the upper cover member 15 is also box-shaped like the lower cover member 12, and is made of, for example, a resin such as BT resin or a metal material such as stainless steel.
  • the insulating sheet 14 has, for example, a thickness of about 500 and is made of an elastic fluororesin (for example, PTFE) or a polyimide resin.
  • the element supporting substrate 10 is electrically connected to the chip supporting portion 10 a for supporting the bare chip 1 via the socket 3 and the input board 3. It has a card edge connector 10b and a lead 10c (see Fig. 3) that is electrically connected to the card edge connector 10b by internal wiring or the like and to which the bonding wire 4 for inspection is connected.
  • the printed wiring board is made of, for example, an epoxy resin.
  • the bare chip 1 when the bare chip 1 is supported by the bare chip carrier 18, that is, the bare chip 1 can be attached to and detached from the chip supporting portion 10 a of the element supporting substrate 10.
  • the bare chip 1 When mounting the bare chip 1, the bare chip 1 is sandwiched between the lower lid member 12 and the chip supporting portion 10 a of the element supporting substrate 10.
  • an insulating sheet 14 is disposed between the bare chip 1 and the chip supporting portion 10a of the element supporting substrate 10.
  • the element supporting substrate 10 has an oval through hole 10d formed substantially at the center thereof, and furthermore, the back surface 10 g of the element supporting substrate 10 (see FIG. 3).
  • the through hole 10d on the surface opposite to the contact terminal surface 10f provided with the lead 10c shown in FIG. a is provided.
  • the base chip 1 is disposed in the chip supporting portion 10a, and bonding between the pad 1a of the base chip 1 and the lead 10c of the element supporting substrate 10 is performed through the through hole 10d. It is getting to be.
  • the electrical connection between the element supporting substrate 10 and the outside is made by a bar as shown in FIG.
  • the card edge connector formed at the end of the element support board 10 by inserting the carrier carrier 18 vertically into the general card edge-type socket 11 mounted on the inboard 3 Via the wiring in the socket 11 and the substrate electrode 3 a, the connection is made to the burn-in board 3.
  • the card edge connector 1 Ob which is an external connection terminal in the element supporting board 10
  • the card edge connector 1 Ob has a through hole ⁇ ⁇ 0 d so that the element supporting board 10 can be used for multiple inspections. , That is, at both ends of the element supporting substrate 10.
  • the semiconductor device S is a multi-chip module 2 in which a plurality (four in this case) of base chips 1 acquired as KGD are stacked and arranged and mounted, for example, a DRAM (Dynamic Random Accelerator). s Memory) is used as a semiconductor device S of chip stack type.
  • a DRAM Dynamic Random Accelerator
  • the multi-chip module 2 shown in Fig. 1 has a bare chip 1 (obtained as a KGD) that has been inspected in advance for burn-in tests, etc., and has been selected as a non-defective product.
  • a bare chip 1 obtained as KGD
  • the lead portion 5a of the element mounting member on which the bare chip 1 is mounted the outer lead 5b connected to the lead portion 5a
  • the bare chip 1 and its peripheral portion 6 are described.
  • the pad 1a of the bare chip 1 and the lead portion 5a as an inner lead are electrically connected by a bonding wire 8 such as a gold wire or an aluminum wire.
  • the bay chip 1 mounted on the multi-chip module 2 of the first embodiment is inspected in advance by a single chip, and as a result, is selected as a non-defective product.
  • the bare chip 1 performs the burn-in inspection by connecting the bare chip 1 and the element supporting substrate 10 with the bonding wire 4 for inspection passed through the through hole 10 d of the element supporting substrate 10 used in the burn-in inspection. After the inspection is completed, the bare chip 1 and the inspection bonding wire 4 are separated by fixing the vicinity of the board-side wire bonding portion 4 d of the inspection bonding wire 4, and are thus selected and obtained as non-defective KGD. It is. Further, in the first embodiment, after the bare chip 1 and the element supporting substrate 10 are electrically connected to each other by the bonding wire 4 for inspection and the burn-in inspection is performed, the bonding wire 4 for inspection and the bare chip 1 are connected. A case will be described in which the bare chip 1 and the bonding wire for inspection 4 are separated without leaving the element-side wire bonding portion 4a of the bonding wire for inspection 4 on the pad 1a of the bare chip 1 when separating.
  • the bonding wire 8 in the first embodiment is a thin metal wire formed of gold (Au), but is not limited thereto.
  • Au gold
  • Al aluminum
  • Cu copper
  • a lead which is an element mounting member for mounting the bare chip 1 is electrically connected to a bonding wire 8 and a lead portion 5a for supporting the bare chip 1 and a laser or the like. It is composed of the outer lead 5b joined to the lead portion 5a. For example, both are formed of an alloy of iron and nickel.
  • the element mounting member is not limited to the lead as long as it can support the bare chip 1, and the element mounting member formed by ceramic or the like is used.
  • Substrate also referred to as package substrate
  • ⁇ ⁇ A film substrate or the like may be used.
  • the sealing resin 7 is, for example, a thermosetting epoxy resin.
  • the circuit forming surface 1b of the bare chip I and the lead portion 5a which is an inner lead of a lead frame (not shown), are arranged to face each other. It has an L 0 C (Lead On Chip) structure, and has four bare chips 1 (obtained as KGD) that have been inspected and sorted by a single chip in advance.
  • the four bare chips 1 and their peripheral portions 6 are arranged and sealed with a sealing resin 7 for the purpose of protecting the bare chips 1.
  • common terminals of the respective bare chips 1 are electrically connected by the outer leads 5b.
  • a passivation film 1 d for protecting the circuit forming surface 1 b is formed on the bare chip 1 of the first embodiment, and the bare chip 1 is fixed to the lead portion 5 a with an insulating tape 9 or the like. Supported and supported. Next, a method for manufacturing a semiconductor device according to the first embodiment will be described.
  • the bare chip 1 divided into individual chips by dicing is mounted on the chip supporting portion 10a of the element supporting substrate 10 shown in FIG. 3 so as to be detachable.
  • the element supporting board 10 is a card supporting section 10a on which the bare chip 1 is mounted, and a card edge connector 1 which is electrically connected to the burn-in board 3 (inspection board) via a socket 11 or the like.
  • 0b and a lead 10c (connection terminal) electrically connected to the card edge connector 10b by internal wiring or the like and connected to the bonding wire 4 for inspection.
  • the printed circuit board on which the card edge connector 10b and the lead 10c are formed is used as the element supporting board 10.
  • the element supporting substrate 10 is formed of, for example, an epoxy resin, and the chip supporting portion 10a is provided with a through hole 10d for disposing the bonding wire 4 for inspection.
  • a through hole 10d for disposing the bonding wire 4 for inspection.
  • connection holes 10e in which pin members 13 to be fitted with the lower lid member 12 (cover member) are provided are provided.
  • a through hole 10d is formed in the center, and an element supporting substrate in which the lead 10c is provided on the contact terminal surface 10f (first main surface) around the through hole 10 of the bracket.
  • the bare chip 1 is arranged on the chip supporting portion 10a on the second main surface opposite to the connection terminal surface 10f of the connection terminal 10.
  • the bare chip 1 when supporting the chip 1 by the element supporting substrate 10, that is, the bare chip 1 is detachably attached to the chip supporting portion 10 a of the element supporting substrate 10.
  • the bare chip 1 When mounting, the bare chip 1 is arranged on the chip supporting side of the element supporting substrate 10, that is, on the second main surface of the back surface 10 g, and the lower lid member 12 and the element supporting substrate 10 that cover the bare chip 1.
  • the chip 1 is sandwiched between the chip supports 10 a of the chip.
  • an insulating sheet 14 is disposed between the bare chip 1 and the chip supporting portion 10a of the element supporting substrate 10.
  • the lower lid member 12 in the first embodiment is a box-shaped profile that covers the bare chip 1, and is made of, for example, a resin such as BT resin or a metal material such as stainless steel. Is formed by
  • the insulating sheet 14 according to the first embodiment has a thickness of, for example, about 500 m, and is formed of an elastic fluororesin (for example, PTFE) or a polyimide resin. Have been.
  • an elastic fluororesin for example, PTFE
  • a polyimide resin for example, polyimide resin
  • the bare chip 1 when the bare chip 1 is sandwiched between the lower lid member 12 and the element supporting substrate 10, first, the bare chip 1 is placed at a predetermined location near the center of the inside of the lower lid member 12.
  • an element supporting substrate 10 having an insulating sheet 14 attached to the chip supporting portion 10a is prepared, and is isolated by the element supporting substrate 10 and the lower lid member 12.
  • the bare chip 1 is supported via the sheet 14.
  • the pin member 13 is arranged in each of the four connecting holes 10 e of the element supporting substrate 10, and the lower lid member 12 is fitted to the pin member 13, and the element supporting substrate 10 Attach to
  • the bare chip 1 is pressed against the chip supporting portion 10 a of the element supporting substrate 10 by the lower lid member 12, and at that time, the insulating sheet 14 force ⁇ deforms (shrinks) Thus, the bare chip 1 is fixed.
  • the pad 1a (device electrode) of the bare chip 1 and the lead 10c of the device support substrate 10 are electrically connected by the bonding wire for inspection 4 passed through the through hole 10d.
  • the bonding wire 4 when the pad 1 a of the bay chip 1 and the lead 10 c of the element supporting substrate 10 are electrically connected by the bonding wire 4 for inspection, An aluminum wire is used for the bonding wire 4, and the two are connected by ultrasonic bonding (also called edge bonding).
  • the pad 1a of the bare chip 1 is electrically connected to the lead 10c of the element supporting substrate 10 by the bonding wire 4 for inspection, as shown in FIG.
  • the pads 1a of the bare chip 1 and the bonding wires 4 for inspection are connected. That is, when performing wire bonding using an ultrasonic bonding apparatus, first, the lead 10 c of the element supporting substrate 10 is connected to the bonding wire 4 for inspection. Then, as shown in FIG. 4 (b), the bonding wire 4 for inspection is passed through the bonding wire 4 for inspection through the through hole 10 d of the element supporting substrate 10, and the pad 1 a of the bare chip 1 is connected. .
  • the element-side wire of the bonding wire for inspection 4 is placed on the pad 1 a of the bare chip 1. Separate so that the joint 4a (see Fig. 4 (c)) does not remain.
  • the bonding conditions on the bare chip 1 side (when connecting the bonding wire 4 for inspection and the pad 1a of the bare chip 1) to prevent the element-side wire joint 4a from remaining on the pad 1a are as follows, for example.
  • the ultrasonic power is about 10 to 60% of the maximum power of the device, the optimal is 15%, the load is about 10 to 45 g, the optimal is 35 g, and the ultrasonic application time is 10 ⁇ 40 msec, optimally set to 30 msec, and bonding wire diameter 25, crimping part length of bonding tool 25-60 m, optimally 51 m, crimping part width 90 -Use 110 m, thereby performing ultrasonic bonding.
  • the bonding conditions are such that the connection strength between the bonding wire 4 for inspection and the pad 1a of the base chip 1 is smaller than the connection strength between the bonding wire 4 for inspection and the lead 10c of the element supporting board 10. Things.
  • the pad 1a of the bare chip 1 and the lead 10c of the element supporting substrate 10 are electrically connected by the bonding wire 4 for inspection and, as shown in FIG.
  • the bonding wire 4 and the bare chip 1 are connected to each other by forming an element-side wire bonding portion 4 a with the pad 1 a of the bare chip 1.
  • the upper cover member 15 is attached to the surface of the element supporting substrate 10 opposite to the surface to which the lower cover member 12 is attached, that is, to the contact terminal surface 10f.
  • the upper lid member 15 is fixed by fitting it to the pin member 13 via the pin member i3, similarly to the lower lid member 12.
  • the bare chip 1 and the bonding wire for inspection 4 can be brought into a substantially hermetically closed state by the upper lid member 15, the element supporting substrate 10 and the lower lid member 12. Therefore, the bare chip 1 can be inspected in an atmosphere in which dust and foreign matter do not adhere to the bare chip 1, and the reliability of the burn-in inspection can be improved.
  • the bare chip carrier 18 can be assembled.
  • the upper lid member 15 has a box-like shape that covers the bare chip 1 like the lower lid member 12 and is made of, for example, a resin such as BT resin or a metal material such as stainless steel. .
  • the element supporting board 10 of the bare chip carrier 18 is inserted into the socket 11 installed on the burn-in board 3 such as a test board.
  • the card edge connector 10b of the element support board 10 is electrically connected to the electrode of the socket 1I, and the card edge connector 10b of the element support board 10 is connected to the socket 1b. It is also electrically connected to the substrate electrode 3 a on the burn-in board 3 via 1.
  • the inspection performed at this time is a burn-in inspection in the first embodiment, and is performed using the burn-in board 3 shown in FIG.
  • the bare chip 1 and the bonding wire 4 for inspection are separated.
  • the bare chip carrier 18 is removed from the socket 11 on the burn-in board 3, the upper cover member 15 shown in FIG. 3 is removed from the element supporting board 10, and then the lower cover member 1 2 Remove.
  • the bare chip 1 and the bonding wire for inspection 4 are separated.
  • the bare chip 1 and the bonding wire for inspection 4 are separated from each other, as shown in FIG. 5, the bare chip 1 is opposite to the circuit forming surface 1 b on which the pad 1 a is formed.
  • the non-circuit forming surface 1c on the side is suctioned by the suction collet 16 (tip holding means) to separate them.
  • the non-circuit-forming surface 1c of the bare chip 1 be sucked by pressing the bonding portion 4c of the bonding wire 4 for inspection on the lead 10c of the element supporting substrate 10 from above.
  • the board side wire connection which is the joint 4c of the inspection bonding wire 4
  • the bonding wire for inspection 4 can be securely separated from the bare chip 1.
  • the bare chip 1 is removed from the element supporting substrate 10.
  • the bare chip 1 is removed from the element supporting board 10 at the same time as the bare chip 1 is suctioned by the suction collet 16 to separate the bare chip 1 from the bonding wire 4 for inspection. It becomes possible. This makes it possible to determine whether the bare chip 1 is good or bad, and obtain a good bare chip 1 as KGD.
  • the bare chip 1 selected by the inspection that is, the bare chip 1 ( KGD) is attached (fixed) to the lead portion 5 a using the insulating tape 9.
  • the pad 1 a of the bare chip 1 and the lead portion 5 a are electrically connected by a bonding wire 8 such as a gold wire.
  • the inspection bonding wire 4 is placed on the pad 1 a of the bare chip 1.
  • the bonding wire 8 and the pad 1a of the bare chip 1 are separated from the bonding chip 4 for inspection because the bare chip 1 and the bonding wire 4 for inspection are separated without leaving the wire bonding portion 4a on the element side. Can be electrically connected with high reliability.
  • the multi-chip module 2 of the first embodiment has four bare chips 1, the four bare chips 1 supported by the lead portion 5a are stacked and arranged in four stages. .
  • the sealing according to the first embodiment is performed by, for example, a transfer molding method ⁇ a potting method or the like for sealing with a resin.
  • the non-defective bare chip 1 and its peripheral portion 6 that have been inspected and selected in advance are sealed with the sealing resin 7.
  • each bare chip 1 and the lead portions 5a connected thereto are electrically connected to each other by the outer leads 5b.
  • the lead portion 5a which is the inner lead, and the outer lead 5b are joined by laser processing or the like.
  • one end of the portal 5b is previously bent into a predetermined shape.
  • the element-side wire bonding portion of the bonding wire 4 for inspection is placed on the pad 1 a of the bare chip 1.
  • the obtained non-defective bare chip I may be shipped as a product in itself, so that 4a is separated so as not to remain.
  • the pad 1a of the bare chip 1 and the lead 10c of the element supporting substrate 10 are electrically connected to each other using the bonding wire 4 for inspection, and the bare chip 1 is subjected to burn-in inspection.
  • KGD can be obtained using the existing wire bonding equipment.
  • the existing wire bonding apparatus can be used as it is.
  • the position of the pad 1a of the bare chip 1 and the position of the lead 10c of the element supporting substrate 10 at the time of wire bonding can be individually detected. Can be. Thereby, the dimensional accuracy of the element supporting substrate 10 can be relaxed.
  • the structure of the bare chip carrier 18 can be simplified.
  • the element supporting substrate 1 is provided for each type of the bare chip 1. There is no need to prepare 0.
  • the number of element supporting substrates 10 and bare chip carriers 18 can be reduced, and the cost for obtaining KGD can be reduced.
  • the wire bonding apparatus can automatically recognize it by using the wire bonding apparatus, so that strict positioning accuracy is not required, and the positioning of the bare chip 1 is not required. Can be easily performed.
  • the bare chip 1 and the element supporting substrate 10 are connected by the bonding wire 4 for inspection to inspect the bare chip 1, and after the inspection is completed, the bare chip 1 and the bonding wire 4 for inspection are separated. Since the pad 1a of the base 1 is not directly pressed against the lead 10c of the element supporting substrate 10, deterioration of the lead 10c of the element supporting substrate I0 and adhesion of dust can be prevented.
  • the bonding is performed so that the wire bonding portion 4a on the element side of the bonding wire 4 for inspection does not remain on the pad 1a of the bare chip 1.
  • the bare chip 1 can be commercialized as a single product and shipped without being incorporated into a semiconductor device such as the multi-chip module 2.
  • a printed wiring board on which leads 10c are formed as element support board 10 By using this, the structure of the element supporting substrate 10 can be easily formed, and the element supporting substrate 10 and the base chip carrier 18 can be formed at low cost. Further, by using an aluminum wire as the bonding wire 4 for inspection and electrically connecting the pad 1 a of the bare chip 1 and the lead 10 c of the element supporting substrate 10 by ultrasonic bonding, When the bare chip 1 and the bonding wire for inspection 4 are separated after completion of the inspection, the bonding wire for inspection 4 can be easily formed.
  • the bare chip 1 can be commercialized and shipped as it is, as described above.
  • the bonding wire on the element 1 side is formed on the pad 1a. 4a can be prevented from remaining.
  • the base 1 is sandwiched between the lower lid member 12 for holding the bare chip 1 and the element supporting substrate 10 via the insulating sheet 14, no adhesive is used for fixing the bare chip 1.
  • the bare chip 1 can be separated from the element supporting substrate 10 easily and without soiling.
  • the bare chip 1 since the bare chip 1 is not damaged, the bare chip 1 can be commercialized and shipped as it is, as described above.
  • the lead 10 c of the element supporting board 10 is connected to the bonding wire 4 for inspection, and thereafter, By connecting the pad 1 a of the bare chip 1 and the bonding wire 4 for inspection, it is possible to prevent a pick tail from being formed on the pad 1 a of the bare chip 1.
  • the bare chip 1 can be commercialized as it is and shipped.
  • the bare chip 1 is supported on the back surface 10 g of the element supporting substrate 10, when the bare chip 1 is separated from the bonding wire 4 for inspection after the inspection, the non-circuit forming surface 1 of the bare chip 1 is separated. As a result, the non-circuit-forming surface 1c of the bare chip 1 is sucked and separated from each other, so that all the inspection bonding wires 4 and the bare chip 1 are collectively collected. In addition to being able to be separated, the bonding wire for inspection 4 can be removed collectively. As a result, the time spent for obtaining the KGD can be reduced.
  • the step of separating the bare chip 1 from the bonding wire 4 for inspection by sucking the non-circuit forming surface 1 c of the bare chip 1 and the step of removing the bare chip 1 from the element supporting substrate 10 can be performed simultaneously. Will be possible.
  • the card edge connector 10b which is an external connection terminal, is provided on both sides of the through hole 10d on the element supporting board 10, the force connector 10b on one side and the connector 10b on the other side are provided. Since the card edge connector 1 Ob can be used separately, the element supporting board 10 can be used a plurality of times during burn-in inspection.
  • the bonding wire 4 for inspection is separated from the base 1 by using an aluminum wire for the bonding wire 4 for inspection and the bonding wire 8 made of gold for the wire bonding of the multi-chip module 2 (semiconductor device).
  • the pad 1 a of the bare chip 1 can be easily separated without damaging it, and furthermore, the bonding wire 8 in the multi-chip module 2 can be prevented from being corroded.
  • the quality of the bare chip 1 can be improved even when a good bare chip 1 is obtained by KGD, and the quality of the multi-chip module 2 can be improved. As a result, it is possible to easily obtain KGD with high performance and high reliability.
  • Embodiment 2 of the present invention will be described with reference to a partial sectional view and an enlarged partial plan view showing a method of separating a bonding wire for inspection and a bare chip shown in FIG. 8, and a partial sectional view showing the structure of a semiconductor device shown in FIG. I do.
  • the element-side wire bonding portion 4a of the bonding wire 4 for inspection is left on the pad 1a of the The bonding wire 4 is separated. That is, in the first embodiment, when the bare chip 1 and the bonding wire for inspection 4 are separated after the completion of the inspection, the element-side wire bonding portion 4 of the bonding wire for inspection 4 is placed on the pad 1 a of the bare chip 1.
  • the bonding of the bare chip 1 is completed after the burn-in inspection is completed, as in the method of separating the bonding wire 4 for inspection and the tape 1 shown in FIG. in which de 1 leaving a device-side wire bonding portion 4 a of the testing Bondi Nguwaiya 4 on a separation of the inspection Bondi Nguwaiya 4 and Beachi-up 1 (see FIG. 8 (a) see
  • the bonding conditions on the bare chip 1 side (when bonding the bonding wire 4 for inspection and the pad 1a of the bare chip 1) to leave the element side wire bonding portion 4a on the pad 1a are as follows.
  • the ultrasonic power is about 25 to 40% of the maximum power of the apparatus, and optimally 30% (ultrasonic power is larger than in the first embodiment), and the load is 25 to 60 g. Degree, optimally 35 g, and the time is set to about 25 to 35 msec, optimally 30 msec, thereby performing ultrasonic bonding.
  • FIG. 8 (a) When the bare chip 1 and the bonding wire 4 for inspection are separated from each other, the element-side wire bonding portion 4a of the bonding wire 4 for inspection can be left on the pad 1a as shown in FIG. .
  • the bonding bonder 4 for inspection is not covered with the wire bonding portion 4a on the element side, but the bonding bonder 4 for inspection is bonded.
  • the bare chip 1 and the bonding wire 4 for inspection are separated by cutting the wire 4 from the neck 4 e (see FIG. 8 (b)) of the wire-side connection 4 a on the element side.
  • this bare chip 1 is used for the multi-chip module 2 shown in FIG. It is also possible to use it for a type of semiconductor device in which the base chip 1 is mounted on the tab 5c of the element mounting member shown in FIG.
  • a gold wire is used for the bonding wire 4 for inspection shown in FIG. 8 (a), and the bonding wire 8 for connecting the lead portion 5 a to the pad 1 a of the bare chip 1 is also used. It is preferable to use a gold wire.
  • Embodiment 3 of the present invention will be described with reference to a cross-sectional view of FIG. 10 showing a method of separating a bonding wire for inspection and a bare chip, and a cross-sectional view showing the structure of a semiconductor device of FIG.
  • the bonding of the inspection bonding wire 4 is performed by ultrasonic thermocompression bonding other than ultrasonic bonding.
  • the bonding wire 4 is connected by ultrasonic thermocompression bonding.
  • a gold wire or a copper wire is used for the bonding wire for inspection 4 instead of the aluminum wire.
  • the bonding conditions for performing the ultrasonic thermocompression bonding are as follows.
  • the ultrasonic power is set to 25 to 4 which is the maximum power of the device.
  • ultrasonic thermocompression bonding is performed.
  • the conditions for the bare chip 1 include, for example, an ultrasonic power of about 25 to 40% of the maximum power of the apparatus, optimally about 30%, and a load of about 50 to 100 g, optimal.
  • 60 g and the time are set to about 25 to 40 msec, optimally to 30 msec, thereby performing ultrasonic thermocompression bonding.
  • the heating temperature is about 200 ° C in pellet temperature.
  • the ultrasonic power and load on the bare chip 1 side were made larger than those in the case of ultrasonic bonding, so that when the bare chip 1 and the bonding wire 4 for inspection were separated, the element side wire joint 4 was placed on the bare chip 1. a can be left.
  • the bonding wire for inspection 4 is placed on the pad 1a of the bare chip 1 as shown in FIG. 10 (b).
  • the protruding element-side wire bonding portion 4a can be left, and is used as a ball-shaped bump when manufacturing a semiconductor device.
  • the semiconductor device shown in FIG. 11 in which the lead portion 5a and the pad 1a of the base chip 1 are electrically connected to each other through the protruding wire bonding portion 4a and by the bonding wire 8 of the gold wire. Can be manufactured.
  • Embodiment 4 of the present invention will be described with reference to a cross-sectional view showing the structure of the semiconductor device in FIG.
  • the bare chip 1 is flip-chip connected.
  • a semiconductor device is manufactured by connecting a bonding wire 8 from above to the protruding element-side wire bonding portion 4a left on the pad 1a of the bare chip 1.
  • the flip chip connection of the bare chip 1 is performed using the protruding wire bonding portion 4 a left on the pad 1 a of the bare chip 1.
  • the projecting wire bonding portion 4a remaining on the pad 1a of the bare chip 1 is used as a bump electrode, and the element side wire bonding portion is connected to the lead portion i7a of the mounting substrate 17 such as a printed board.
  • the bare chip 1 is flip-chip mounted via 4a.
  • FIG. 13 is a cross-sectional view showing the structure of the bare chip carrier in FIG. 13;
  • FIG. 14 is an enlarged partial cross-sectional view showing the bonding state between the bonding wire for inspection and the bare chip in FIG. This will be described with reference to a cross-sectional view illustrating a method of separating the bonding wire for inspection and the bare chip.
  • the base carrier 18 of the fifth embodiment differs from the base chip carrier 18 of the first embodiment in that the upper lid member 15 and the lower lid member 12 have different shapes. The airtightness inside the bare chip carrier 18 is improved.
  • a recessed portion 10h which is a counterbore is formed as a chip supporting portion 10a around the through hole 10d.
  • the bay chip 1 is mounted on the surface of the recess 10h via the insulation sheet 14a.
  • the upper lid member 15 and the lower lid member 12 are provided with convex portions 15a and 12a, respectively.
  • the back surface of the bare chip 1 is supported by the convex portion 12a of the lower lid member 12 via the insulating sheet 14b.
  • the insulating sheets 14a and 14b are arranged on both the circuit forming surface 1b and the non-circuit forming surface 1c of the bare chip 1, and the bare chip 1 in this state is It is sandwiched between the chip supporting portion 10a and the convex portion 12a of the lower lid member 12.
  • the bare chip 1 is protected by the insulating sheets 14a and 14b on both sides of the circuit forming surface 1b and the non-circuit forming surface 1c.
  • an insulating sheet 14c is disposed on the connection terminal surface 10f of the element supporting substrate 10, and a projection 15a of the upper lid member 15 is provided on the connection terminal surface 10f. It is in close contact with sheet 14c.
  • the element supporting substrate 10 of the bare chip carrier 18 of the fifth embodiment, the upper lid member 15, the lower lid member 12, and the insulating sheets 14 a and 14 c are relatively soft and easily deformed, for example, formed of a fluorine-based resin (PTFE).
  • PTFE fluorine-based resin
  • the insulating sheet 14b is formed of a polyimide resin sheet that is harder than the fluorine resin.
  • the element support substrate 10 is provided with pin members 13 embedded on both sides thereof by press-fitting or the like, and the upper cover member 15 and the lower cover member 12 are attached to the pin members 13. This allows the bare chip carrier 18 to be assembled, and allows the bare chips 1 to be separated and taken out, and then reassembled.
  • a snap ring 10 i is provided at the fitting portion 15 b. 12 b of the upper lid member 15 and the lower lid member 12 in the fifth embodiment where the pin member 13 is fitted. I have.
  • the inner peripheral portion of the snap ring 10 i tightens the outer peripheral portion of the pin member 13 with an appropriate force (a force that does not allow the two to easily move). It goes without saying that they are in a relationship. Subsequently, as shown in FIG. 14, the element supporting substrate 10 and the bare chip 1 are electrically connected using the bonding wires 4 for inspection.
  • the bonding method of the bonding wire for inspection 4 in the fifth embodiment is the same as the bonding method of the bonding wire for inspection 4 described in the first embodiment.
  • the inspection is performed on the pad 1a of the bare chip 1. Separate so that the element-side wire joint 4a of the bonding wire 4 for use does not remain.
  • the ultrasonic bonding is performed under the same bonding conditions as those described in the first embodiment (the conditions for easily separating the element-side wire bonding portion 4a without leaving it).
  • the pad 1a of the bare chip 1 and the lead 10c of the element supporting board 10 are electrically connected by the bonding wire 4 for inspection, and the bonding wire 4 for inspection and the bare chip 1 are An element-side wire bonding portion 4a is formed and connected to the pad 1a of the bare chip 1.
  • the upper lid member 15 and the lower lid member 12 are removed from the element supporting substrate 10, and the bare chip 1 is separated using the suction collet 16.
  • the method of separating the bonding wire for inspection 4 and the bare chip 1 in the fifth embodiment is the same as the separation method described in the first embodiment. That is, as shown in FIG. 15, the non-circuit forming surface 1c of the bare chip 1 is sucked by the suction collet 16 to separate them.
  • the bonding portion 4 c of the bonding wire 4 for inspection on the lead 10 c of the element supporting substrate 10 is pressed down from above and the non-circuit forming surface of the bare chip 1 is pressed.
  • 1 c is aspirated. That is, the bonding wire 4 for inspection is securely separated from the bare chip 1 by pressing down and fixing the board-side wire connection portion 4 d which is the bonding portion 4 c of the bonding wire 4 for inspection from above. Can be.
  • Embodiment 6 of the present invention will be described with reference to a partial sectional view showing a bonding method shown in FIG. 16 and a partial front view showing a structure of a bonding edge shown in FIG.
  • the sixth embodiment specifically describes the bonding conditions in the fifth embodiment, and the bonding conditions are the same as the bonding conditions described in the first embodiment. belongs to.
  • the bonding conditions are such that the connection strength between the bonding wire 4 for inspection and the pad 1a of the bare chip 1 is smaller than the connection strength between the bonding wire 4 for inspection and the lead 10c of the element supporting board 10. This is performed by ultrasonic bonding in the same manner as in the first embodiment using a bonding wedge 19 shown in FIGS. 16 and 17.
  • the element support is carried out in the same manner as in the first embodiment. After connecting the lead 10c of the substrate 10 and the bonding wire 4 for inspection, the pad 1a of the bare chip 1 is connected to the bonding wire 4 for inspection.
  • the lead 10c of the element supporting substrate 10 and the bonding wire 4 for inspection are connected. Then, the bonding wire 4 for inspection is connected to the pad 1 a of the bare chip 1 through the bonding wire 4 for inspection through the through hole 10 d of the element supporting substrate 10.
  • the wire forms a wire loop after the first crimping, and the crimped portion may be pulled apart by the wire and may be separated. It is a thing to do.
  • the pick tail is formed on the side where the bonding is performed first, bonding the bare chip 1 side later prevents the pick tail from being formed on the pad 1 a of the bare chip 1. it can.
  • a uniform load can be applied to the crimped portion.
  • FIG. 18 is an enlarged partial plan view showing the structure of the bare chip shown in FIG. 18;
  • FIG. 19 is an enlarged partial plan view showing the joint state between the bare chip and the bonding wire shown in FIG. 20; This will be described with reference to the drawings.
  • the bare chip 1 can be mounted on a semiconductor device, or can be shipped as a single chip in a state of the bare chip 1 as shown in FIG.
  • the bonding wire 8 of a gold wire is used.
  • a semiconductor device is manufactured by forming a gold wire ball 8a on an impression 4b on a pad 1a and performing wire bonding on the gold ball 8a using a bonding wire 8 of a gold wire.
  • the pad 1 a Bonding wire 8 of aluminum wire is crimped onto the indentation 4 on a to manufacture a semiconductor device.
  • Embodiment 8 of the present invention will be described with reference to FIGS. 21, 22 and 23, which are sectional views showing a method of separating the bonding wire for inspection and the bare chip, and the inspections shown in FIGS. 24, 25 and 26. This will be described with reference to a cross-sectional view illustrating a method of separating a bonding wire for use from an element supporting substrate.
  • Embodiment 8 shows a method of separating the bare chip 1 from the element supporting substrate 10 (the method of taking out the bare chip 1) after performing the burn-in inspection using the bare chip carrier 18 described in Embodiment 5.
  • a tape 20 is used.
  • the automatic mounting / dismounting unit S completes the burn-in inspection and separates the bare chip 1 connected to the element supporting substrate 10 by the inspection bonding wire 4 from the inspection bonding wire 4.
  • the configuration of the automatic communication device includes a stage 21 for holding an element supporting substrate 10 electrically connected to the pad 1a of the bare chip 1 by the bonding wire 4 for inspection, and a bare chip for holding the bare chip 1 Suction collet 16 which is a chip holding means for moving vacuum suction of element 1 away from element support substrate 10, roller 25 for winding adhesive tape 20, and pressing adhesive tape 20 when separated It consists of a tape retainer 26 that performs the inspection and a wire pressing plate 27 that presses the bonding wire 4 for inspection when the vehicle is in operation.
  • the bare chip 1 is moved in a direction away from the element supporting board 10 to bond the inspection bonding wire 4 and the bare chip 1 is separated.
  • the adhesive tape 20 used in the eighth embodiment has adhesiveness on only one side, such as a dicing tape (also referred to as a UV tape) used in a dicing step or the like.
  • a dicing tape also referred to as a UV tape
  • the tape is not limited to the dicing tape, and other tape members may be used as long as they do not adversely affect the semiconductor substrate and the semiconductor element (Bear Chip 1) in the semiconductor device manufacturing process. Good.
  • the method for taking out the base chip 1 from the element supporting substrate 10 according to the eighth embodiment explain about.
  • the lower lid member 12 and the upper lid member 15 are removed from the element supporting substrate 10.
  • the lower lid member 12, the element supporting substrate 10, and the upper lid member 15 are separated from each other.c Then, as shown in FIG. 1, 10 g of the back side of the element supporting substrate 10 (the bare chip 1 is supported).
  • the device supporting substrate 10 is mounted with its side facing upwards and positioned on the stage 21 of the automatic communication device.
  • the adhesive surface 20a of the adhesive tape 20 disposed below the stage 21 and the connection terminal surface 10 # of the element supporting substrate 10 are disposed to face each other.
  • suction collet 16 is lowered from above the bare chip 1 toward the non-circuit forming surface 1c, and the tape retainer 26 is raised below the stage 21.
  • the adhesive tape 20 is pressed by the tape retainer 26, thereby pressing the adhesive tape 20 near the board side wire joint 4 d and adhering it. Affix the tape 20 to the connection terminal surface 10 ⁇ of the element supporting substrate 10 to fix the substrate side wire bonding portion 4 d.
  • the adhesive tape 20 is adhered to the vicinity of the periphery of the through hole 10 d of the connection terminal surface 10 f of the element supporting substrate 10, thereby forming the bonding wire 4 d on the substrate side of the bonding wire 4 for inspection.
  • the area is fixed with adhesive tape 20.
  • the non-circuit forming surface 1 c of the bare chip 1 is vacuum-adsorbed by the suction collet 16, and the bare chip 1 is held.
  • the bare chip 1 is held by the suction collet 16, and in this state, the suction collet 16 is held above the element supporting substrate 10, that is, in a direction away from the element supporting substrate 10. By moving it, the bare chip 1 and the bonding wire for inspection 4 are separated.
  • the bonding wire 4 for inspection and the bare chip 1 are bonded under bonding conditions that do not leave the element-side wire joint 4a on the pad 1a of the bare chip 1, the pad 1a The element-side wire joint 4a does not remain on the upper side.
  • the bonding wire for inspection 4 and the bare chip 1 are bonded according to the bonding conditions that leave the wire bonding portion 4a on the element side, the wire bonding portion 4a on the element side remains on the head 1a. I do.
  • the picked-up bare chip 1 is held and transported by the suction collet 16 and stored in a chip storage section (not shown) (for example, tray).
  • a chip storage section for example, tray
  • the wire pressing plate 27 is lowered from above the element supporting substrate 10 toward the through hole 10 d, and the inspection bonding wire 4 is moved by the wire pressing plate 27. To the adhesive tape 20.
  • the bonding wire for inspection 4 is attached to the adhesive tape 20. Further, as shown in FIG. 25, the state in which the bonding wire for inspection 4 is adhered to the adhesive tape 20 by the wire pressing plate 27 is maintained (by the wire pressing plate 27 and the tape retainer 26). While holding the bonding wire for inspection 4 and the adhesive tape 20), the tape retainer 26 is moved downward, that is, moved in a direction away from the element supporting substrate 10.
  • the bonding wire 4 for inspection can be attached to the adhesive tape 20 to separate the bonding wire 4 for inspection from the element supporting substrate 10, and the adhesive tape 20 can be detached from the element supporting substrate 10. .
  • the wire pressing plate 27 is lifted, that is, moved in a direction away from the element supporting substrate 10.
  • the tape retainer 26 is lowered, separated from the adhesive tape 20 to make the adhesive tape 20 movable freely, and the roller 25 is rotated in one predetermined direction. Then take up the adhesive tape 20.
  • the used inspection bonding wire 4 can be collected without being scattered while being adhered to the adhesive tape 20.
  • the unused adhesive surface 2 of the adhesive tape 20 is located below the vicinity of the through hole 10d of the element supporting substrate 10. 0a can be arranged.
  • the bonding wire 4 for inspection is attached to the adhesive tape 20 to separate the element supporting substrate 10, the bonding wire 4 for inspection, and the bare chip 1. it can.
  • the burn-in inspection when separating the bare chip 1 from the bonding wire 4 for inspection, by fixing and separating the vicinity of the board-side wire joint 4 d, the element-side wire joint 4 a or the vicinity thereof is fixed.
  • the base chip 1 and the bonding wire 4 for inspection can be separated.
  • the bonding wire 4 for inspection When the bonding wire 4 for inspection is fixed in the vicinity of the wire bonding portion 4 d on the substrate side, it can be easily fixed by using the adhesive tape 20, and the bare chip 1 and the bonding wire 4 for inspection can be securely fixed. And can be separated. Furthermore, the use of the adhesive tape 20 allows the automatic communication device to have a simple structure.
  • the adhesive tape 20 was detached from the element supporting substrate 10. At this time, the inspection bonding wire 4 can be attached to the adhesive tape 20.
  • the bonding wire 4 for inspection after the inspection can be easily and quickly collected by the adhesive tape 20 without scattering.
  • the bonding wire 4 for inspection is attached to the adhesive tape 20 to separate the element supporting substrate 10 and the bonding wire 4 for inspection, so that the bonding bond 10 for inspection is attached to the lead 10 c of the element supporting substrate 10.
  • the entire inspection bonding wire 4 can be removed (removed) without leaving the substrate-side wire joint 4 d of the bonding wire 4.
  • the element supporting substrate 1.0 can be used multiple times, whereby the bare chip carrier 18 can also be used as a reproducing carrier. It can be used again.
  • the ninth embodiment of the present invention shows a manufacturing procedure of the semiconductor device of FIGS. 27 and 28. This will be described with reference to a cross-sectional view and a cross-sectional view showing the structure of the semiconductor device in FIG.
  • the semiconductor device described in the ninth embodiment has an L0C structure in which a good bare chip 1 obtained from the result of burn-in inspection is mounted.
  • the configuration of the semiconductor device includes a circuit forming surface 1b and a lead frame 5 (see FIG. 27) of the base chip 1, which is selected as a non-defective product based on a result of performing a burn-in test using an aluminum wire as the test bonding wire 4.
  • the lead portion 5a of the element mounting member is disposed so as to face the pad, and the pad 1a of the bare chip 1 and the lead portion 5a are connected with each other by a bonding wire 8 made of gold.
  • the base chip 1 and the bonding wire 8 are sealed with a sealing resin 7.
  • a bare chip 1 that is selected as a non-defective product based on the result of a burn-in inspection using an aluminum wire as the inspection bonding wire 4 shown in FIG. 13 is prepared. Subsequently, as shown in FIG. 27, the circuit forming surface 1 b of the bare chip 1 and the lead portion 5 a of the lead frame 5 are opposed to each other, and an insulating tape 9 made of polyimide or the like is interposed therebetween. The bare chip 1 is mounted on the lead section 5a.
  • the pad 1a of the bare chip 1 and the lead portion 5a are electrically connected by a bonding wire 8 made of gold.
  • the bare chip 1 and the bonding wire 8 are sealed with a sealing resin 7 to manufacture the semiconductor device having the LOC structure.
  • the lead frame 5 on which the bonded bare chip 1 has been mounted is loaded into a mold (not shown), and resin sealing is performed by, for example, transfer molding.
  • a dam portion (not shown) of the lead frame 5 is cut, and a solder plating process is performed, and a mark is formed.
  • the outer lead 5b is formed by a molding die (not shown), and the LOC shown in FIG. 29 can be manufactured.
  • sorting and aging are performed in advance on the bare chip 1, so that sorting and aging after forming the outer leads 5b are performed. Is no longer required and can be shipped immediately after assembly.
  • Embodiment 10 of the present invention will be described with reference to a partial cross-sectional view showing a procedure for manufacturing the semiconductor device in FIG. 30-a partial cross-sectional view showing the structure of the semiconductor device in FIG. 31.
  • the semiconductor device described in the present embodiment 10 has a structure in which a good bare chip 1 obtained from the result of burn-in inspection is directly mounted on a mounting board 17.
  • the bare chip 1 which was selected as a non-defective product from the result of burn-in inspection using an aluminum wire for the inspection bonding wire 4 (see FIG. 13) was performed as shown in FIG. While being mounted on the mounting board 17, the pad 1 a of the bare chip 1 and the lead portion 17 a which is an electrode of the mounting board 17 are electrically connected by bonding wires 8 made of gold, Further, the bare chip 1 and the bonding wire 8 are sealed with a sealing resin 7.
  • a method of manufacturing the COB according to the tenth embodiment will be described.
  • a bare chip 1 that is selected as a non-defective product based on the result of a burn-in inspection performed using an aluminum wire as the inspection bonding wire 4 shown in FIG. 13 is prepared.
  • the bare chip 1 is mounted on the mounting board 17 using an Ag paste or an insulating adhesive.
  • the pad 1a of the bare chip 1 and the lead portion 17a of the mounting board 17 are connected in a frosty manner by bonding wires 8 made of gold.
  • the bare chip 1 and the bonding wire 8 are sealed with a sealing resin 7 to manufacture the semiconductor device having the C0B structure.
  • the resin sealing according to the tenth embodiment is performed by, for example, potting or the like, and is cured.
  • Embodiment 11 of the present invention will be described with reference to a plan view showing the structure of the element support substrate in FIG. 32 and an enlarged plan view showing the structure of the element support substrate in FIG.
  • the present embodiment 11 is different from the element supporting substrate 10 described in the first embodiment. It has a different structure.
  • the lead 10c is provided only on one side of the longitudinal direction periphery of the through hole 10d formed near the center, and the inspection bonding wire 4 is provided. -It can be taken out only in the direction.
  • the force edge connector 10b is provided only at one end of the through hole I 0d.
  • the bonding wire 4 for the inspection is used as the bonding wire 10c for the inspection.
  • a straight line is drawn from the position of pad 1a of bare chip 1 to the line (A) outside (A-a '), the lead 10c is arranged on the straight line, and the bonding area of the lead 10c is formed to be long in the same direction as the extending direction of the bonding wire 4 for inspection.
  • one end of the element supporting board 10 is used as a card edge connector 10 b, and through the card edge connector 10 b.
  • the bare chip carrier 18 (see Fig. 13) is inserted vertically into the general card-edge socket 11 (see Fig. 7) mounted on the burn-in board 3 (see Fig. 7). It has become.
  • a convex portion 22 is provided on one of the sides where the card edge connector 10b is arranged in order to prevent reverse insertion.
  • a notch 23 and an opening 24 are provided at both ends where the card edge connector 10 b is not disposed, and the notch 23 and the opening 24 are provided.
  • the bare chip carrier 18 can be easily removed from the socket 11 on the burn-in board 3 by using a jig or the like fitted into the hole 24.
  • the element supporting substrate 10 in the first to eleventh embodiments is a printed wiring board.
  • the element support substrate 10 is not limited to this, and may have an external connection terminal such as a card edge connector 10 b that supports the bare chip 1 and electrically connects to the burn-in board 3. It may have another shape such as a box shape.
  • the burn-in inspection is performed in an atmosphere in which the periphery of the bare chip 1 and the bonding wire 4 for inspection is sealed by the lower lid member 12 and the upper lid member 15.
  • the lower lid member 12 and the upper lid member 15 are not necessarily used, and the inspection may be performed in a state where the bare chip 1 and the bonding wire for inspection 4 are exposed.
  • the pad 1 a of the bare chip 1 is connected to the bonding wire 4 for inspection.
  • the order of bonding is not limited to this. After connecting the pad 1a of the bare chip 1 and the bonding wire 4 for inspection, the bonding order of the element supporting board 1 is determined. The pad 1 a of No. 0 may be connected to the bonding wire 4 for inspection.
  • the bonding chip 4 is suctioned by the suction collet 16 to separate the bonding wire 4 for inspection from the bare chip 1, but the bonding wire 4 for inspection and the bare chip 1 are described.
  • the hook member or the like may be hooked on the inspection bonding wire 4 and pulled and separated, or the inspection bonding wire 4 may be cut using a cutter member or the like. You may.
  • the bare chip 1 and the insulating sheet 14 or the insulating sheet 14a are simultaneously sucked by the suction collet 16 and separated from the element supporting board 10 together with the insulating sheet 14 or the insulating sheet 14a. After that, the bare chip 1 and the insulating sheet 14 or the insulating sheet 14a can be separated.
  • various bonding conditions for electrically connecting the bare chip 1 and the carrier 10 using the inspection bonding wires 4 described in the first to eleventh embodiments are not limited thereto. If the bonding wire 4 for inspection and the bonding tape 1 or the bonding wire 4 for inspection and the element supporting board 10 can achieve a desired connection state, the other bonding conditions may be satisfied. Is also good.
  • the inspection bonding wire 4 is formed by using an aluminum wire as the inspection bonding wire 4 and using the bonding wire 8 made of gold for the wire bonding of the semiconductor device.
  • the bonding wire 4 is separated from the base 1, the pad 1 a of the bare chip 1 can be easily separated without damaging the bonding wire 4, and the bonding wire 8 is corroded in the semiconductor device. Can be prevented.
  • the structure, shape, material, and the like of the bare chip carrier 18 are not limited to those in Embodiments 1 to 11, and in the present invention, in particular, the device support substrate 10 Combinations of reuse and wire bonding can be widely applied.
  • the separation method and the material of the bonding wire 8 are not limited to the combinations described in the first to eleventh embodiments, and it goes without saying that any combination may be used.
  • bare chip 1 With the reliable KGD technology of bare chip 1 as described above, DRAM, SRAM, FLASH, MCM, PDA (Personal Digital Assistant), Handy PC, simple mobile phone, mobile phone, module, etc. It can be expected to be effective for small equipment with limited capacity, such as lower product prices due to lower bare chip prices and module prices, and the availability of highly reliable bare chips1.
  • a module with a high mounting density using the bare chip 1 can be configured, thereby making it possible to reduce the size and weight of the device.
  • the method of manufacturing a semiconductor device according to the present invention is suitable for the KGD technology for obtaining a high-performance and high-reliability base chip at low cost, easily, and stably.
  • the semiconductor device of the present invention to be mounted is not only highly reliable and inexpensive but also includes DRAM, SRAMs FLASH, MCM, PDA (portable information terminal), handy personal computer, PHS, mobile phone, module, etc. It is suitable for small devices with limited capacity, especially for modules with a high mounting density using bare chips such as stacked DRAM general-purpose memory modules.

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Abstract

A process for producing a semiconductor device by which a high-performance highly reliable KGD can be manufactured easily and stably at a low cost. A semiconductor device manufactured by the method is also disclosed. A bare chip carrier (18) comprises a chip supporting substrate (10), an upper lid member (15), and a lower lid member (12), and a bare chip (1) is held between the member (12) and the substrate (10) through insulating sheets (14). The chip (1) is connected to the substrate (10) through a bonding aluminum wire (4) for inspection. To separate the bare chip (1) from the substrate (10) after burn-in inspection, a substrate-side wire bonding section (4d) or its vicinity is fixed with an adhesive tape and the wire (4) is stuck to the adhesive tape by moving the chip (1) from the substrate (10). After the separation, the chip (1) is connected to a lead section by performing wire bonding using a new gold bonding wire. Then the chip (1), bonding wire, and part of the lead section are encapsulated with resin, thus completing a semiconductor device.

Description

明 細 書 半導体装置の製造方法および半導体装置 技術分野  Description: Semiconductor device manufacturing method and semiconductor device technical field

本発明は、 半導体装置の製造技術に関し、 特に予め検査を行って良品のベアチ ップを取得する半導体装置の製造方法および半導体装置に関する。 背景技術  The present invention relates to a semiconductor device manufacturing technique, and more particularly, to a semiconductor device manufacturing method and a semiconductor device in which an inspection is performed in advance to obtain a good quality chip. Background art

例えば、 発明者が検討したところによれば、 半導体集積回路の高集積化 .高密 度化に伴ってパッケージ品を使った実装に比べ、 実装密度が大幅に向上するベア チップすなわち良品であることを保 IEしたベアチップ （K G D ： Known Good D i e ) を実装した半導体装置、 さらにこの半導体装置をモジュール化した積層汎用メ モリモジュールを用いる技術などが、 今後、 有効と考えられる。  For example, according to studies by the inventor, it has been found that a bare chip, that is, a non-defective product, in which the packaging density is greatly improved as compared with packaging using a packaged product due to the higher integration of a semiconductor integrated circuit. Semiconductor devices mounted with a bare chip (KGD: Known Good Die) using IE and a technology using a stacked general-purpose memory module that modularizes this semiconductor device are considered to be effective in the future.

このベアチップにおいては、 近年、 パッケージ品と同等の信頼性が保 IEされて きている。 例えば、 固有欠陥および潜在的不良要因を持ったベアチップを除去す るためのスク リ一二ング試験を行うバーンィン技術としては、 テス ト用のベアチ ップキヤ リァとバーンィンソケッ トを用いてバーンィンボードに搭載し、 このバ ーンインポ一 ドをチヤンバ内に収納することによりスク リーニング試験が行われ るようになっている。  In recent years, this bare chip has been assured of the same reliability as packaged products. For example, as a burn-in technology for conducting a screening test to remove a bare chip having an inherent defect and a potential defect factor, a burn-in board is mounted on a burn-in board using a test chip carrier and a burn-in socket. Screening tests are performed by storing the burn-in in a chamber.

このようなベアチップのバーンィン技術においては、 スクリ一二ング試験後に ベアチップキヤリアからベアチップを取り出し、 K G Dを取得することが主流と となっている。  In such bare chip burn-in technology, the mainstream is to take out a bare chip from a bare chip carrier after a screening test and obtain a KGD.

なお、 このベアチップキャリアとベアチップとの接铳方法としては、 ベアチッ プキャリアを支持する素子支持基板のバンプ （接続端子） にベアチップのパッ ド (素子電極） を押し付けて電気的接続を行う方法と、 前記素子支持基板のバンプ とべァチッブのパッ ドとをワイヤボンディ ングによって接铳する方法との 2つの 方法がある。  The bare chip carrier can be connected to the bare chip by a method in which a bare chip pad (device electrode) is pressed against a bump (connection terminal) of an element supporting substrate that supports the bare chip carrier, and an electrical connection is made. There are two methods, a method of connecting the bumps of the element support substrate and the pads of the base by wire bonding.

ここで、 後者のワイヤボンディ ングによって接铳する方法と しては、 例えば、 特開平 8 - 1 2 4 9 8 0号公報、 あるいは、 米国特許第 5 1 7 3 4 5 1号公報に 記載された技術が挙げられる。 Here, as a method of connecting by the latter wire bonding, for example, The technology described in Japanese Unexamined Patent Application Publication No. Hei 8-124980 or US Pat. No. 5,173,451 may be mentioned.

これらの技術においては、 熱硬化性接着剤、 熱可塑性接着剤、 粘着フイルムま たはシリ コーンゲルなどを用いて、 ベアチップキヤ リア上にベアチップを固定し た後、 ワイヤボンディ ングによってベアチップキャ リアとベアチップとを電気的 に接続している。 さらに、 選別、 エージング後、 ボンディ ングワイヤをエツチン グによって溶解、 あるいは機械的剝雜によって除去し、 その後、 ベアチップキヤ リァを加熱することにより、 ベアチップをベアチップキャ リアから取り外して K G Dを取得している。  In these technologies, a bare chip carrier is fixed on a bare chip carrier using a thermosetting adhesive, a thermoplastic adhesive, an adhesive film, or a silicone gel, and then the bare chip carrier and the bare chip are bonded by wire bonding. And are electrically connected. Furthermore, after sorting and aging, the bonding wire is melted by etching or removed by mechanical engraving, and then the bare chip carrier is heated to remove the bare chip from the bare chip carrier to obtain a KGD.

なお、 特開平 8 - 1 2 4 9 8 0号公報には、 ボンディ ングワイヤをエッチング により溶解してパッ ド上から除去するか、 あるいは、 ボンディ ングワイヤに金や はんだを用い、 これらを熱によって溶融して罨極用のバンプを形成する方法が記 載されている。  Japanese Patent Application Laid-Open No. Hei 8-124980 discloses that a bonding wire is melted by etching and removed from the pad, or gold or solder is used for the bonding wire and these are melted by heat. It describes how to form bumps for compress electrodes.

また、 米国特許第 5 1 7 3 4 5 1号公報には、 ボンディ ングワイヤに細いアル ミニゥム線を用い、 かつボンディ ングゥヱッジにも圧着面積の小さいものを使用 してパッ ドの端部にボンディ ングを行うとともに、 ボンディ ング条件を弱く し、 その結果、 ボンディ ングワイヤを引っ張ることにより、 パッ ドから機械的にボン ディ ングワイヤを剝離させる技術が記載されている。  Also, in U.S. Pat. No. 5,173,451, a thin aluminum wire is used as a bonding wire, and a bonding crimping area having a small crimping area is used to bond the end of the pad. In addition, there is described a technique for weakening the bonding conditions and, as a result, mechanically separating the bonding wire from the pad by pulling the bonding wire.

ところで、 前記のようなベアチップとベアチップキヤ リアとを分離させる技術 においては、 例えば、 ベアチップを熱可塑性接着剤を用いてベアチップキャ リア に固定した場合、 ボンディ ング時またはエージング時に高温に加熱されるため、 ベアチップがベアチッブキヤ リァから剝離して雜脱することが問題とされる。 また、 熱硬化性接着剤を用いた場合、 エージング後にベアチップをベアチップ キヤ リァから取り出すのは困難である。  By the way, in the technology for separating the bare chip and the bare chip carrier as described above, for example, when the bare chip is fixed to the bare chip carrier using a thermoplastic adhesive, the bare chip is heated to a high temperature during bonding or aging. However, it is a problem that the bare chip separates from the bare carrier and escapes. When a thermosetting adhesive is used, it is difficult to remove the bare chip from the bare chip carrier after aging.

さらに、 これらの接着剤を用いたベアチップの固定方法では、 K G D取得後に ベアチップに接着剤が残留するため、 ベアチップを製品化した後、 封止樹脂との 密着性低下によるクラック （亀裂） 発生など製品の信頼性に悪影響を及ぼすこと が問題とされる。  Furthermore, in the method of fixing bare chips using these adhesives, the adhesive remains on the bare chips after obtaining the KGD, so that after the bare chips are commercialized, cracks occur due to reduced adhesion to the sealing resin. The problem is that it has an adverse effect on the reliability of the system.

さらに、 接着剤に含まれる揮発性溶剤の付着によって発生する汚染も問題とさ れる。 In addition, contamination caused by the adhesion of volatile solvents contained in the adhesive is also a problem. It is.

なお、 以上のように、 接着剤を用いてベアチップを固定する場合に、 ベアチッ プ取り出し後のベアチップキヤ リァを再利用するためには、 素子支持基板に残留 した接着剤およびボンディ ングワイヤを除去する必要がある。  As described above, when the bare chip is fixed using an adhesive, in order to reuse the bare chip carrier after removing the bare chip, it is necessary to remove the adhesive and the bonding wire remaining on the element supporting substrate. There is.

ここで、 特開平 8 - 1 2 4 9 8 0号公報には、 エージング後のボンディ ングヮ ィャの除去方法として、 酸を用いたエッチングによる方法、 あるいは、 加熟はん だ溶融中に浸潰して金線を溶融させる方法が記載されているが、 ベアチップへの 溶剤の残留、 異物付着または熱によるベアチップクラックの発生など信頼性につ いての問題が懸念されるとともに、 製造装置や設備が必要となり、 投資費用およ びベアチップ単価の増大が問題とされる。  Here, Japanese Unexamined Patent Application Publication No. Hei 8-124980 discloses a method of removing bonding bonds after aging, a method by etching using an acid, or a method of immersing ripened solder during melting. Describes how to melt the gold wire by heating, but there are concerns about reliability issues such as residual solvent on bare chips, adhesion of foreign matter, or cracking of bare chips due to heat, and the need for manufacturing equipment and facilities Therefore, investment cost and increase in bare chip unit cost are problematic.

また、 米国特許第 5 1 7 3 4 5 1号公報には、 エージング時のワイヤボンディ ングをゥヱッジボンディ ングによって行い、 この際、 ボンディ ングワイヤに細い ものを用い、 かつボンディ ングゥ ッジの圧着面積を従来の 1ノ 4にすることに より、 エージング時にはパッ ドの端部にボンディ ングし、 K G D取得後の製品と してのワイヤボンディ ング時にはエージング時のボンディ ングの圧痕を避けてボ ンディ ングする方法が記載されている。  U.S. Pat.No. 5,173,451 discloses that wire bonding at the time of aging is carried out by bonding, and in this case, a thin bonding wire is used, and the bonding area of the bonding wedge is reduced. By bonding to the end of the pad at the time of aging, and bonding to avoid the indentation of the bonding at the time of aging when bonding the wire as a product after obtaining KGD Is described.

し力、し、 エージング時に細いボンディ ングワイヤを用いると、 ボンディ ング時 にワイヤ切れが発生し、 連統運転が困難になることが問題とされるとともに、 ェ 一ジング後のワイヤ除去時にもワイヤが切れ易く、 パッ ド以外すなわちワイヤの 途中で切断することも問題とされる。  If a thin bonding wire is used during aging, wire breakage will occur during bonding, making continuous operation difficult, and the wire will be removed when removing the wire after aging. It is easy to cut, and it is also a problem that it is cut outside the pad, that is, in the middle of the wire.

さらに、 圧着面積を小さくすることにより、 単位面積当たりに掛かるエネルギ が増大し、 パッ ド下地を破壊するという問題が起こる。  Furthermore, reducing the crimping area increases the energy required per unit area, causing the problem of destroying the pad base.

なお、 ワイヤの除去方法として、 機械的にワイヤを引っ張る方法が記載されて いる力 <、 ベアチップがベアチップキャリアの上方に配置されているため、 ワイヤ を何れかの方法によって固定して上方に引っ張らざるを得ず、 一括でワイヤを除 去するのは困難であることが問題とされ、 また、 ワイヤを 1本毎に除去するのに は時間が掛かり、 コス トアップにつながることが問題とされる。  Note that the method for mechanically pulling the wire is described as a method for removing the wire Force <Since the bare chip is placed above the bare chip carrier, the wire is fixed by any method and is not pulled upward The problem is that it is difficult to remove the wires all at once, and it is also a problem that it takes time to remove the wires one by one, leading to cost increase.

そこで、 本発明の目的は、 高性能および高信頼性を有する K G Dを安価にかつ 安定して取得する半導体装置の製造方法および半導体装置を提供することにある。 また、 本発明の他の目的は、 高性能および高信頼性を有する K G Dを容易に取 得する半導体装 の製造方法および半導体装置を提供することにある。 Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device and a semiconductor device for obtaining KGD having high performance and high reliability at low cost and in a stable manner. It is another object of the present invention to provide a method of manufacturing a semiconductor device and a semiconductor device which can easily obtain KGD having high performance and high reliability.

本発明の前記ならびにその他の目的と新規な特徴は、 本明細書の記述および添 付図面から明らかになるであろう。 発明の開示  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention

本発明の半導体装置の製造方法は、 貫通孔が形成されかつこの貫通孔の周囲の 第 1主面に接続端子が設けられた素子支持基板を準備し、 前記第 1主面と反対側 の第 2主面にベアチップを配置する工程と、 前記素子支持基板の第 2主面側に配 置させるカバー部材と前記素子支持基板とによって前記べァチップを挟持するェ 程と、 前記べァチップの素子電極と前記素子支持基板の接铳端子とを前記貫通孔 に通した検査用ボンディ ングワイヤによって電気的に接続する工程と、 前記素子 支持基板の接続端子と検査基板の基板電極とを電気的に接続して前記べァチップ を検査する工程と、 検査後、 前記検査用ボンディ ングワイヤの基板側ワイヤ接合 部付近を固定して前記ベアチップと前記検査用ボンディ ングワイヤとを分離し、 前記べァチップを前記素子支持基板から取り外す工程とを含み、 前記検査によつ て良品のベアチップを選別するものである。  In the method for manufacturing a semiconductor device according to the present invention, an element supporting substrate having a through hole formed therein and having connection terminals provided on a first main surface around the through hole is provided. (2) a step of disposing a bare chip on the main surface; a step of sandwiching the bay chip between the cover member disposed on the second main surface side of the element support substrate and the element support substrate; and an element electrode of the bay chip. Electrically connecting the connection terminal of the element support substrate to the connection terminal of the element support substrate by a bonding wire for inspection passed through the through hole; and electrically connecting the connection terminal of the element support substrate to the substrate electrode of the inspection substrate. Inspecting the bare chip by using the method described above. After the inspection, fixing the vicinity of the board-side wire bonding portion of the bonding wire for inspection to separate the bare chip and the bonding wire for inspection. And a step of removing the flop from the element supporting substrate, is intended for sorting bare non-defective Te cowpea to the test.

これにより、 検査後、 ベアチップと検査用ボンディ ングワイヤとを分離する際 に、 基板側ワイヤ接合部付近を固定して分離することにより、 素子側ワイヤ接合 部もしくはその近傍においてベアチップと検査用ボンディ ングワイヤとを分離す ることができる。  Thus, when the bare chip is separated from the bonding wire for inspection after the inspection, the vicinity of the wire bonding portion on the substrate is fixed and separated, so that the bare chip and the bonding wire for testing are separated at or near the element side wire bonding portion. Can be separated.

さらに、 本発明の半導体装置の製造方法は、 検査後に前記ベアチップと前記検 査用ボンディ ングワイヤとを分離する際、 前記ベアチップの素子電極上に前記検 査用ボンディ ングワイヤの素子側ワイヤ接合部が残留しないように両者を剝離さ せて分離するものである。  Further, in the method of manufacturing a semiconductor device according to the present invention, when separating the bare chip and the bonding wire for inspection after the inspection, the element-side wire bonding portion of the bonding wire for inspection remains on the element electrode of the bare chip. The two are separated so that they do not separate.

また、 本発明の半導体装置の製造方法は、 中心部に貧通孔が形成されかっこの 貫通孔の周囲に接続端子が設けられた素子支持基板のチップ支持部にベアチップ を配置する工程と、 前記素子支持基板のチップ支持側に配置させるカバ一部材と 前記素子支持基板とによって前記べァチップを挟持する工程と、 前記べァチップ の素子電極と前記素子支持基板の接続端子とを前記貫通孔に通した検査用ボンデ ィ ングワイヤによって電気的に接続する工程と、 前記素子支持基板の接続端子と 検査基板の基板電極とを電気的に接続して前記べァチップを検査する工程と、 検 査後、 前記検査用ボンディ ングワイヤの基板側ワイヤ接合部付近を固定するとと もに前記ベアチップの素子電極上に前記検査用ボンディ ングワイヤの素子側ワイ ャ接合部を残留させて前記べァチップと前記検査用ボンディ ングワイヤとを分離 し、 前記ベアチップを前記素子支持基板から取り外す工程とを含み、 前記検査に よって良品のベアチッブを選別するものである。 The method of manufacturing a semiconductor device according to the present invention further includes a step of disposing a bare chip on a chip supporting portion of an element supporting substrate in which a poor hole is formed in the center and connection terminals are provided around the through hole. A step of clamping the bay chip by a cover member arranged on a chip supporting side of an element supporting substrate and the element supporting substrate; Electrically connecting the device electrode of the device support and the connection terminal of the device support substrate by a bonding wire for inspection passed through the through hole; and electrically connecting the connection terminal of the device support substrate and the substrate electrode of the test substrate. A step of testing the bare chip by connecting the chip to the substrate, and after the test, fixing the vicinity of the board-side wire bonding portion of the bonding wire for testing, and the device side of the bonding wire for testing on the device electrode of the bare chip. A step of separating the bare chip from the bonding wire for inspection by leaving a wire bonding portion, and removing the bare chip from the element supporting substrate, and selecting a good bare chip by the inspection.

なお、 本発明の半導体装置は、 予め電気的な検査を行って良品と して選別され たベアチップを搭載した半導体装置であって、 前記検査時に用いる素子支持基板 の貫通孔に通した検査用ボンディ ングワイヤによって前記ベアチップと前記素子 支持基板とを接铳して前記検査を行った後、 前記検査用ボンディ ングワイヤの基 板側ワイヤ接合部付近を固定して前記ベアチップと前記検査用ボンディ ングワイ ャとを分離して取得した 1つまたは複数のベアチップが搭載され、 前記べァチッ プの素子電極上に前記検査用ボンディ ングワイヤの素子側ワイヤ接合部を残留さ せずに前記ベアチップと前記検査用ボンディ ングワイヤとを分離した際には、 素 子搭載部材のリ一ド部または実装基板のリード部と前記素子電極とが電気的に接 続され、 前記べァチップの素子電極上に前記素子側ヮィャ接合部を残留させて前 記ベアチップと前記検査用ボンディ ングワイヤとを分離した際には、 前記素子側 ワイヤ接合部を介して前記リ一ド部と前記素子電極とが電気的に接続されている ものである。 図面の簡単な説明  Note that the semiconductor device of the present invention is a semiconductor device on which a bare chip that has been subjected to an electrical inspection in advance and is selected as a non-defective product is mounted, and that an inspection bonder passed through a through hole of an element supporting substrate used for the inspection is provided. After performing the inspection by connecting the bare chip and the element supporting substrate with a bonding wire, the vicinity of the base-side wire bonding portion of the bonding wire for inspection is fixed to connect the bare chip and the bonding wire for inspection. One or more bare chips obtained separately are mounted, and the bare chip and the bonding wire for inspection are not left on the device electrode of the base without leaving the element-side wire bonding portion of the bonding wire for inspection. When the device electrode is separated, the lead portion of the device mounting member or the lead portion of the mounting board is electrically connected to the device electrode. When the element-side wire bonding portion is left on the device electrode of the bay chip to separate the bare chip and the bonding wire for inspection, the bare chip and the inspection bonding wire are separated from the lead portion via the element-side wire bonding portion. The device electrodes are electrically connected. BRIEF DESCRIPTION OF THE FIGURES

図 1は本発明の実施の形態 1である半導体装置の構造を示す断面図、 図 2本発 明の実施の形態 1である半導体装置の製造方法に用いられる素子支持部材の構造 を示す平面図、 図 3は実施の形態 1の半導体装置の製造方法に用いられるベアチ ップキャリアの構造を示す部分断面図、 図 4 ( a ) , ( b ) , ( c ) は実施の形態 1 の半導体装置の製造方法における検査用ボンディ ングワイヤとベアチップとの接 合方法を示す図であり、 （a )， ( b ) は部分断面図、 （ c ) は拡大部分平面図、 図 5は実施の形態 1の半導体装置の製造方法における検査用ボンディ ングワイヤ とべァチップとの分離方法を示す断面図、 図 6は実施の形態 1の半導体装置の製 造方法において検査用ボンディ ングワイヤから分離させた後のベアチップの構造 を示す拡大部分平面図、 図 7は実施の形態 1の半導体装置の製造方法に用いられ るバーンインボードの構造を示す斜視図、 図 8 ( a ) , ( b ) は本発明の実施の形 態 2である半導体装置の製造方法における検査用ボンディ ングワイヤとベアチッ プとの分雜方法を示す図であり、 （a ) は部分断面図、 （b ) は拡大部分平面図、 図 9は本発明の実施の形態 2である半導体装置の構造を示す部分断面図、 図 1 0 ( a ), ( b ) は本発明の実施の形態 3である半導体装置の製造方法における検査 用ボンディ ングワイヤとベアチップとの分離方法を示す断面図、 図 1 1 は本発明 の実施の形態 3である半導体装置の構造を示す断面図、 図 1 2は本発明の実施の 形態 4である半導体装置の構造を示す断面図、 図 1 3は本発明の実施の形態 5で ある半導体装置の製造方法に用いられるベアチップキヤリァの構造を示す断面図、 ィャとベアチップとの接合状態を示す拡大部分断面図、 図 1 5は実施の形態 5の 半導体装置の製造方法における検査用ボンディ ングワイヤとベアチップとの分離 方法を示す断面図、 図 1 6は本発明の実施の形態 6である半導体装置の製造方法 におけるボンディ ング方法を示す部分断面図、 図 1 7は実施の形態 6の半導体装 置の製造方法に用いられるボンディ ングゥ ッジの構造を示す部分正面図、 図 1 8は本発明の実施の形態 7である半導体装置の製造方法における検査によって得 られたベアチップの構造を示す拡大部分平面図、 図 1 9は実施の形態 7の半導体 装置の製造方法における検査によって得られたベアチップとボンディ ングワイヤ との接合状態を示す拡大部分平面図、 図 2 0は実施の形態 7の半導体装置の製造 方法における検査によって得られたベアチップとボンディ ングワイヤとの接合状 態を示す拡大部分平面図、 図 2 1 は本発明の実施の形態 8である半導体装置の製 造方法における検査用ボンディ ングワイヤとベアチップとの分雠方法を示す断面 図、 図 2 2は実施の形態 8の半導体装置の製造方法における検査用ボンディ ング ワイヤとベアチップとの分離方法を示す断面図、 図 2 3は実施の形態 8の半導体 装置の製造方法における検査用ボンディ ングワイヤとベアチップとの分離方法を 示す断面図、 図 2 4は実施の形態 8の半導体装置の製造方法における検査用ボン ディ ングワイヤと素子支持基板との分離方法を示す断面図、 図 2 5は実施の形態 8の半導体装置の製造方法における検査用ボンディ ングワイヤと素子支持基板と の分離方法を示す断面図、 図 2 6は実施の形態 8の半導体装置の製造方法におけ る検査用ボンディ ングワイヤと素子支持基板との分離方法を示す断面図、 図 2 7 は本発明の実施の形態 9である半導体装置の製造手順を示す断面図、 図 2 8は実 施の形態 9の半導体装匱の製造手順を示す断面図、 図 2 9は実施の形態 9の半導 体装置の構造を示す断面図、 図 3 0は本発明の実施の形態 1 0である半導体装置 の製造手順を示す部分断面図、 図 3 1 は本発明の実施の形態 1 0である半導体装 置の構造を示す部分断面図、 図 3 2は本発明の実施の形態 1 1である半導体装置 の製造方法に用いられる素子支持基板の構造を示す平面図、 図 3 3は実施の形態 1 1である半導体装置の製造方法に用いられる素子支持基板の構造を示す拡大平 面図である。 発明を実施するための最良の形態 FIG. 1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a plan view showing a structure of an element supporting member used in a method of manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a partial cross-sectional view showing the structure of a bare chip carrier used in the method for manufacturing a semiconductor device according to the first embodiment. FIGS. 4 (a), 4 (b), and 4 (c) are diagrams showing a method for manufacturing the semiconductor device according to the first embodiment. FIGS. 4A and 4B are diagrams showing a bonding method between a bonding wire for inspection and a bare chip in the method, in which (a) and (b) are partial sectional views, (c) is an enlarged partial plan view, FIG. 5 is a cross-sectional view showing a method of separating a bonding wire for inspection and a bare chip in the method of manufacturing a semiconductor device according to the first embodiment. FIG. 6 is a sectional view showing a method of manufacturing the bonding device according to the first embodiment. FIG. 7 is an enlarged partial plan view showing the structure of the bare chip after being made, FIG. 7 is a perspective view showing the structure of a burn-in board used in the method of manufacturing a semiconductor device according to the first embodiment, and FIGS. 8 (a) and (b) are FIG. 8 is a diagram showing a method for separating inspection bonding wires and bare chips in a semiconductor device manufacturing method according to a second embodiment of the present invention, wherein (a) is a partial cross-sectional view, and (b) is an enlarged partial plan view. FIG. 9 is a partial cross-sectional view showing the structure of a semiconductor device according to the second embodiment of the present invention, and FIGS. 10A and 10B are inspections in the method of manufacturing the semiconductor device according to the third embodiment of the present invention. Bonding wire for FIG. 11 is a cross-sectional view illustrating a method of separating a semiconductor device from a bare chip, FIG. 11 is a cross-sectional view illustrating the structure of a semiconductor device according to a third embodiment of the present invention, and FIG. 12 is a cross-sectional view illustrating the structure of the semiconductor device according to the fourth embodiment of the present invention. FIG. 13 is a cross-sectional view showing a structure of a bare chip carrier used in a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention, an enlarged partial cross-sectional view showing a bonding state between a key and a bare chip, FIG. 15 is a cross-sectional view showing a method for separating a bonding wire for inspection and a bare chip in a method for manufacturing a semiconductor device according to the fifth embodiment. FIG. 16 is a sectional view showing a method for manufacturing a semiconductor device according to a sixth embodiment of the present invention. FIG. 17 is a partial front view showing the bonding method used in the method for manufacturing a semiconductor device according to the sixth embodiment, and FIG. 17 is a partial front view showing the structure of the bonding wedge. A semiconductor device FIG. 19 is an enlarged partial plan view showing the structure of the bare chip obtained by the inspection in the method of manufacturing the semiconductor device according to the seventh embodiment. FIG. 19 is an enlarged view showing the bonding state between the bare chip and the bonding wire obtained by the inspection in the method of manufacturing the semiconductor device according to the seventh embodiment. FIG. 20 is an enlarged partial plan view showing a bonded state between a bare chip and a bonding wire obtained by inspection in the method of manufacturing a semiconductor device according to the seventh embodiment. FIG. 21 is an embodiment of the present invention. FIG. 22 is a cross-sectional view showing a method of separating the bonding wire for inspection and the bare chip in the method of manufacturing a semiconductor device according to the eighth embodiment. FIG. FIG. 23 is a cross-sectional view showing a separation method. FIG. Cross-sectional view illustrating the method for separating and flop, Bonn inspection in the manufacturing method of FIG. 2 4 is a semiconductor device of the eighth embodiment FIG. 25 is a cross-sectional view showing a method for separating the bonding wire from the element supporting substrate. FIG. 25 is a cross-sectional view showing a method for separating the bonding wire for inspection and the element supporting substrate in the method for manufacturing a semiconductor device according to the eighth embodiment. Is a cross-sectional view showing a method of separating a bonding wire for inspection and an element supporting substrate in the method of manufacturing a semiconductor device according to the eighth embodiment. FIG. 27 is a flow chart showing a manufacturing procedure of the semiconductor device according to the ninth embodiment of the present invention. FIG. 28 is a cross-sectional view illustrating a manufacturing procedure of the semiconductor device according to the ninth embodiment, FIG. 29 is a cross-sectional view illustrating the structure of the semiconductor device according to the ninth embodiment, and FIG. FIG. 31 is a partial cross-sectional view showing a manufacturing procedure of the semiconductor device according to the tenth embodiment of the present invention, FIG. 31 is a partial cross-sectional view showing the structure of the semiconductor device according to the tenth embodiment of the present invention, and FIG. Embodiment 11 Used in a manufacturing method of a semiconductor device according to Embodiment 11. Plan view showing a structure of a child support substrate, Figure 3 3 is an enlarged planar view showing the structure of an element supporting substrate used in the method of manufacturing a semiconductor device according to Embodiment 1 1 embodiment. BEST MODE FOR CARRYING OUT THE INVENTION

本発明をより詳述に説述するために、 添付の図面に従ってこれを説明する。 本発明の実施の形態 1を、 図 1の半導体装置の構造を示す断面図、 図 2の素子 支持部材の構造を示す平面図、 図 3のベアチップキヤ リァの構造を示す部分断面 図、 図 4の検査用ボンディ ングワイヤとベアチップとの接合方法を示す図、 図 5 の検査用ボンディ ングワイヤとベアチップとの分離方法を示す断面図、 図 6の検 査用ボンディ ングワイヤから分離させた後のベアチップの構造を示す拡大部分平 面図、 図 7のバーンィンボードの構造を示す斜視図を用いて説明する。  The present invention will be described in more detail with reference to the accompanying drawings. FIG. 4 is a cross-sectional view showing the structure of the semiconductor device of FIG. 1, a plan view showing the structure of the element supporting member of FIG. 2, a partial cross-sectional view showing the structure of the bare chip carrier of FIG. Figure showing the bonding method between the bonding wire for inspection and bare chip, Figure 5 is a cross-sectional view showing the method for separating the bonding wire for inspection and bare chip, and Figure 6 shows the structure of the bare chip after being separated from the bonding wire for inspection. This will be described with reference to an enlarged partial plan view showing the structure and a perspective view showing the structure of the burn-in board shown in FIG.

まず、 図 7に示す本実施の形態 1の半導体装置の製造方法に用いるベアチップ キヤ リアが搭載されるバーンィンボード 3の構成を説明する。  First, the configuration of the burn-in board 3 on which the bare chip carrier used in the method for manufacturing a semiconductor device according to the first embodiment shown in FIG. 7 is mounted will be described.

本実施の形態 1のバーンィンボード 3は、 良品の K G Dを取得する際の検査時 に用いられるものである。  The burn-in board 3 of the first embodiment is used at the time of inspection when obtaining a good KGD.

すなわち、 前記検査は、 ベアチップ 1 (ペレッ トともいう） に対して行われる ものであり、 例えば、 バーンイン （スク リーニングテス トとも呼ばれる各種動作 寿命試験） などのエージングや信頼性検査などであり、 ベアチップ 1の選別検査 でもある。 ここでは、 バーンイ ンの場合について説明する。 また、 バーンィンボー ド 3は、 例えば、 スクリーニングテス 卜を行うバーンィ ン装置のチヤンバ内に多数個のベアチップ 1を収納するために用いられるボード である。 That is, the inspection is performed on the bare chip 1 (also referred to as a pellet), and is, for example, an aging test such as burn-in (various operation life tests also called a screening test) or a reliability test. It is also a screening test of 1. Here, the case of burn-in will be described. The burn-in board 3 is, for example, a board used for storing a large number of bare chips 1 in a chamber of a burn-in device for performing a screening test.

なお、 このバーンインボード 3には複数個のベアチップキャリア 1 8がソケッ ト 1 1を介して搭載され、 このバーンインによって固有欠陥および潜在的不良要 因を持ったベアチッブ 1が除去されるようになっている。  A plurality of bare chip carriers 18 are mounted on the burn-in board 3 via a socket 11, and the burn-in removes the bare chip 1 having an inherent defect and a potential defect factor. I have.

ここで、 ベアチップキャ リア 1 8は、 ベアチップ 1上のパッ ド 1 a (素子電極 Here, bare chip carrier 18 is connected to pad 1a (element electrode) on bare chip 1.

) と素子支持基板 1 0上のリー ド 1 0 c (接続端子） 間を電気的に接统し、 素子 支持基板 1 0上の外部接铳端子である力一ドエツジコネクタ 1 0 bを通じて外部 に接铳することができるキャリアであり、 例えば、 図 3に示すような構造によつ て、 ベアチップ 1のパッ ド 1 aと素子支持基板 1 0のリード 1 0 cとがワイヤボ ンディ ングによりアルミニウムまたは金などからなる検査用ボンディ ングワイヤ) And the lead 10 c (connection terminal) on the element support board 10 are electrically connected to each other, and are externally connected through the force connector 10 b, which is an external connection terminal on the element support board 10. For example, according to the structure shown in FIG. 3, the pad 1a of the bare chip 1 and the lead 10c of the element supporting substrate 10 are made of aluminum by wire bonding. Or bonding wire for inspection made of gold, etc.

4を通じて接铳され、 かっこの検査用ボンディ ングワイヤ 4は切断可能とされて 素子支持基板 1 0が再利用可能な構造となっている。 4, the bonding wire 4 for parentheses inspection is cuttable, and the element supporting substrate 10 has a structure that can be reused.

また、 ベアチップキヤ リア 1 8は、 図 3に示すように、 下部蓋部材 1 2 (カバ 一部材） と上部蓋部材 1 5と素子支持基板 1 0とからなるものであり、 ベアチッ プ 1が下部蓋部材 1 2と上部蓋部材 1 5と素子支持基板 1 0とによって密閉され、 高い気密性を有している。  As shown in FIG. 3, the bare chip carrier 18 is composed of a lower lid member 12 (one cover member), an upper lid member 15 and an element supporting board 10, and the bare chip 1 It is hermetically sealed by the lid member 12, the upper lid member 15, and the element supporting substrate 10, and has high airtightness.

なお、 ベアチップ 1 は、 素子支持基板 1 0の貫通孔 1 0 dと位置合わせしてチ ップ支持部 1 0 aに配置され、 このベアチップキャ リア 1 8においては、 絶緣シ ー ト 1 4を介してべァチップ 1が素子支持基板 1 0と下部蓋部材 1 2とによって 挟持される構造となっている。  The bare chip 1 is arranged on the chip supporting portion 10a so as to be aligned with the through hole 10d of the element supporting substrate 10, and in the bare chip carrier 18, the insulating sheet 14 is provided. The base chip 1 is sandwiched between the element supporting substrate 10 and the lower lid member 12 via the base chip 1.

また、 図 2に示す素子支持基板 1 0には、 例えば、 4箇所に連桔孔 1 0 eが形 成されており、 この連結孔 1 0 eに、 図 3に示すようにピン部材 1 3が埋め込ま れている。  In addition, in the element supporting substrate 10 shown in FIG. 2, for example, connection holes 10 e are formed at four places, and pin holes 13 e are formed in the connection holes 10 e as shown in FIG. Is embedded.

従って、 ベアチップキヤ リア 1 8は、 素子支持基板 1 0に取り付けられたピン 部材 1 3に上部蓋部材 1 5と下部蓋部材 1 2とを嵌め込むことにより、 組立、 分 解および再組立可能な構造となっている。  Therefore, the bare chip carrier 18 can be assembled, disassembled, and reassembled by fitting the upper lid member 15 and the lower lid member 12 into the pin member 13 attached to the element supporting substrate 10. It has a structure.

また、 実施の形態 1における下部蓋部材 1 2は、 ベアチップ 1を覆う箱形の形 伏のものであり、 例えば、 B Tレジンなどの樹脂やステンレス鋼などの金属材に よって形成されている。 Further, the lower lid member 12 in the first embodiment has a box-like shape that covers the bare chip 1. For example, it is made of a resin such as BT resin or a metal material such as stainless steel.

さらに、 上部羞部材 1 5についても下部蓋部材 1 2と同様に箱形のものであり, 例えば、 B Tレジンなどの樹脂やステンレス鋼などの金属材によって形成されて いる。  Further, the upper cover member 15 is also box-shaped like the lower cover member 12, and is made of, for example, a resin such as BT resin or a metal material such as stainless steel.

また、 絶緣シート 1 4は、 例えば、 厚さ 5 0 0 程度のものであり、 弾性を 有したフッ素系樹脂 （例えば、 P T F E ) あるいはボリイ ミ ド系榭脂などによつ て形成されている。  The insulating sheet 14 has, for example, a thickness of about 500 and is made of an elastic fluororesin (for example, PTFE) or a polyimide resin.

ここで、 本実施の形態 1 における素子支持基板 1 0は、 ベアチップ 1 を支持す るチップ支持部 1 0 aと、 <ーンィンボ一ド 3とソケッ ト I 1などを介して電気 的に接铳するカー ドエッジコネクタ 1 0 bと、 内部配線などによってカー ドエッ ジコネクタ 1 0 bと電気的に接铳しかつ検査用ボンディ ングワイヤ 4が接铳され るリー ド 1 0 c (図 3参照） とを備えたブリ ン 卜配線基板であり、 例えば、 ェポ キシ系の樹脂などによって形成されている。  Here, the element supporting substrate 10 according to the first embodiment is electrically connected to the chip supporting portion 10 a for supporting the bare chip 1 via the socket 3 and the input board 3. It has a card edge connector 10b and a lead 10c (see Fig. 3) that is electrically connected to the card edge connector 10b by internal wiring or the like and to which the bonding wire 4 for inspection is connected. The printed wiring board is made of, for example, an epoxy resin.

本実施の形態 1においては、 図 3に示すように、 ベアチップキャ リア 1 8によ つてベアチップ 1を支持する際、 すなわち、 ベアチップ 1を素子支持基板 1 0の チップ支持部 1 0 aに着脱可能に搭載する際に、 ベアチップ 1を覆ケ下部蓋部材 1 2と素子支持基板 1 0のチップ支持部 1 0 aとによってベアチップ 1を挟持す る。  In the first embodiment, as shown in FIG. 3, when the bare chip 1 is supported by the bare chip carrier 18, that is, the bare chip 1 can be attached to and detached from the chip supporting portion 10 a of the element supporting substrate 10. When mounting the bare chip 1, the bare chip 1 is sandwiched between the lower lid member 12 and the chip supporting portion 10 a of the element supporting substrate 10.

この時、 ベアチップ 1 と素子支持基板 1 0のチップ支持部 1 0 aとの間に絶縁 シート 1 4を配置させる。  At this time, an insulating sheet 14 is disposed between the bare chip 1 and the chip supporting portion 10a of the element supporting substrate 10.

また、 素子支持基板 1 0には、 図 2に示すように、 ほぼ中心部に長円形の貫通 孔 1 0 dが形成され、 さらに、 素子支持基板 1 0の裏面側 1 0 g (図 3に示すリ ード 1 0 cが設けられた接铳端子面 1 0 f と反対側の面） の貫通孔 1 0 dの周囲 には、 この貫通孔 1 0 dを中心にしてチップ支持部 1 0 aが設けられている。 これにより、 このチッブ支持部 1 0 aにべァチップ 1が配置され、 貫通孔 1 0 dを通じてべァチップ 1のパッ ド 1 aと素子支持基板 1 0のリード 1 0 cとのヮ ィャボンディ ングが行われるようになつている。  As shown in FIG. 2, the element supporting substrate 10 has an oval through hole 10d formed substantially at the center thereof, and furthermore, the back surface 10 g of the element supporting substrate 10 (see FIG. 3). Around the through hole 10d on the surface opposite to the contact terminal surface 10f provided with the lead 10c shown in FIG. a is provided. As a result, the base chip 1 is disposed in the chip supporting portion 10a, and bonding between the pad 1a of the base chip 1 and the lead 10c of the element supporting substrate 10 is performed through the through hole 10d. It is getting to be.

ここで、 素子支持基板 1 0の外部との電気的接続は、 図 3に示すように、 バー ンィンボー ド 3に搭載された一般的なカードエツジ型のソケッ 卜 1 1にべァチッ ブキャ リア 1 8を垂直状態で挿し込むことにより、 素子支持基板 1 0の端部に形 成されたカー ドエッジコネクタ 1 0 bとソケッ 卜 1 1内の配線と基板電極 3 aと を介し、 これにより、 バーンインボード 3と接铳される。 Here, the electrical connection between the element supporting substrate 10 and the outside is made by a bar as shown in FIG. The card edge connector formed at the end of the element support board 10 by inserting the carrier carrier 18 vertically into the general card edge-type socket 11 mounted on the inboard 3 Via the wiring in the socket 11 and the substrate electrode 3 a, the connection is made to the burn-in board 3.

なお、 素子支持基板 1 0において外部接続端子であるカードエッジコネクタ 1 O bは、 図 2に示すように、 素子支持基板 1 0を複数回の検査に使用可能なよう に、 貫通孔〗 0 dの両側すなわち素子支持基板 1 0の両端に設けられている。 次に、 図 1に示す本実施の形態 1の半導体装置について説明する。  Note that, as shown in FIG. 2, the card edge connector 1 Ob, which is an external connection terminal in the element supporting board 10, has a through hole よ う 0 d so that the element supporting board 10 can be used for multiple inspections. , That is, at both ends of the element supporting substrate 10. Next, the semiconductor device of the first embodiment shown in FIG. 1 will be described.

なお、 前記半導体装 Sは、 K G Dとして取得された複数 （ここでは 4個） のべ ァチップ 1を積展配置しかつ搭載してなるマルチチップモジュール 2であり、 例 えば、 D R A M ( Dynam i c Random Acces s Memo ry) 用のチップ積暦形の半導体装 Sとして用いられるものである。  The semiconductor device S is a multi-chip module 2 in which a plurality (four in this case) of base chips 1 acquired as KGD are stacked and arranged and mounted, for example, a DRAM (Dynamic Random Accelerator). s Memory) is used as a semiconductor device S of chip stack type.

図 1に示すマルチチップモジユール 2は、 予めバーンィンテス 卜などの検査を 行いかつ良品として選別された （K G Dとして取得された） ベアチップ 1を搭載 したものであり、 図 1〜図 4を用いてその構成を説明すると、 K G Dとして取得 したベアチップ 1 と、 ベアチップ 1を搭載する素子搭載部材のリード部 5 aと、 リード部 5 aに接続されたァウタリード 5 bと、 ベアチップ 1 とその周辺部 6と を封止した封止樹脂 7とからなり、 ベアチップ 1のパッ ド 1 aとインナリー ドで あるリー ド部 5 aとが、 金線またはアルミニウム線などのボンディ ングワイヤ 8 によって電気的に接続されている。  The multi-chip module 2 shown in Fig. 1 has a bare chip 1 (obtained as a KGD) that has been inspected in advance for burn-in tests, etc., and has been selected as a non-defective product. To explain the configuration, the bare chip 1 obtained as KGD, the lead portion 5a of the element mounting member on which the bare chip 1 is mounted, the outer lead 5b connected to the lead portion 5a, the bare chip 1 and its peripheral portion 6 are described. The pad 1a of the bare chip 1 and the lead portion 5a as an inner lead are electrically connected by a bonding wire 8 such as a gold wire or an aluminum wire.

ここで、 本実施の形態 1のマルチチッブモジュール 2に搭載されたべァチップ 1 は、 チップ単体で予め検査が行われ、 その結果、 そこで良品として選別された ものである。  Here, the bay chip 1 mounted on the multi-chip module 2 of the first embodiment is inspected in advance by a single chip, and as a result, is selected as a non-defective product.

つまり、 ベアチップ 1は、 バーンイン検査時に用いる素子支持基板 1 0の貫通 孔 1 0 dに通した検査用ボンディ ングワイヤ 4によってベアチップ 1 と素子支持 基板 1 0 とを接铳して前記バーンイン検査を行い、 検査終了後、 検査用ボンディ ングワイヤ 4の基板側ワイヤ接合部 4 d付近を固定してベアチップ 1 と検査用ボ ンディ ングワイヤ 4 とを分離し、 これにより、 良品の K G Dとして選別されて取 得したものである。 また、 本実施の形態 1 においては、 検査用ボンディ ングワイヤ 4によってベア チップ 1 と素子支持基板 1 0 とを電気的に接続してバーンィン検査を行った後、 検査用ボンディ ングワイヤ 4 とベアチップ 1 とを分離させる際に、 ベアチップ 1 のパッ ド 1 a上に検査用ボンディ ングワイヤ 4の素子側ワイヤ接合部 4 aを残留 させずにベアチップ 1 と検査用ボンディ ングワイヤ 4とを分離する場合を説明す る。 In other words, the bare chip 1 performs the burn-in inspection by connecting the bare chip 1 and the element supporting substrate 10 with the bonding wire 4 for inspection passed through the through hole 10 d of the element supporting substrate 10 used in the burn-in inspection. After the inspection is completed, the bare chip 1 and the inspection bonding wire 4 are separated by fixing the vicinity of the board-side wire bonding portion 4 d of the inspection bonding wire 4, and are thus selected and obtained as non-defective KGD. It is. Further, in the first embodiment, after the bare chip 1 and the element supporting substrate 10 are electrically connected to each other by the bonding wire 4 for inspection and the burn-in inspection is performed, the bonding wire 4 for inspection and the bare chip 1 are connected. A case will be described in which the bare chip 1 and the bonding wire for inspection 4 are separated without leaving the element-side wire bonding portion 4a of the bonding wire for inspection 4 on the pad 1a of the bare chip 1 when separating.

ここで、 本実施の形態 1 におけるボンディ ングワイヤ 8は、 金 （A u ) によつ て形成された金属細線であるが、 これに限らず、 例えば、 アルミニウム （A 1 ) ゃ鐧 （C u ) などによって形成されたものであってもよい。  Here, the bonding wire 8 in the first embodiment is a thin metal wire formed of gold (Au), but is not limited thereto. For example, aluminum (A1)) (Cu) It may be formed by such means.

さらに、 図 1 に示すように、 ベアチップ 1を搭載する素子搭載部材であるリー ドは、 ボンディ ングワイヤ 8と電気的に接続されかつべァチップ 1を支持するリ ー ド部 5 aと、 レーザなどによってリード部 5 aに接合されるァウタリー ド 5 b とからなり、 例えば、 両者とも鉄とニッケルの合金などによって形成されている。 なお、 半導体装置がマルチチップモジュール 2以外の場合などには、 前記素子 搭載部材は、 ベアチップ 1を支持可能なものであれば、 前記リードに限らず、 セ ラミ ックなどによって形成された素子搭載基板 （パッケージ基板ともいう） ゃフ ィルム基板などであってもよい。  Further, as shown in FIG. 1, a lead which is an element mounting member for mounting the bare chip 1 is electrically connected to a bonding wire 8 and a lead portion 5a for supporting the bare chip 1 and a laser or the like. It is composed of the outer lead 5b joined to the lead portion 5a. For example, both are formed of an alloy of iron and nickel. When the semiconductor device is other than the multi-chip module 2, for example, the element mounting member is not limited to the lead as long as it can support the bare chip 1, and the element mounting member formed by ceramic or the like is used. Substrate (also referred to as package substrate) で あ A film substrate or the like may be used.

また、 封止樹脂 7は、 例えば、 熱硬化性のエポキシ系樹脂などである。  The sealing resin 7 is, for example, a thermosetting epoxy resin.

ここで、 本実施の形態 1によるマルチチップモジュール 2は、 ベアチップ Iの 回路形成面 1 bとリードフレーム （図示せず） のインナリ一 ドであるリ一ド部 5 aとを対向させて配置した L 0 C (Lead On Ch i p) 構造のものであり、 チップ単 体で予め検査して選別された （K G Dとして取得した） 4個のベアチップ 1を有 し、 前記 4個のベアチップ 1が穰層配置され、 かつ、 4個のベアチップ 1 とその 周辺部 6とがベアチップ 1を保護する目的で封止榭脂 7によって封止されている。 さらに、 それぞれのベアチップ 1における共通端子がァウタリード 5 bによつ て電気的に接続されている。  Here, in the multi-chip module 2 according to the first embodiment, the circuit forming surface 1b of the bare chip I and the lead portion 5a, which is an inner lead of a lead frame (not shown), are arranged to face each other. It has an L 0 C (Lead On Chip) structure, and has four bare chips 1 (obtained as KGD) that have been inspected and sorted by a single chip in advance. The four bare chips 1 and their peripheral portions 6 are arranged and sealed with a sealing resin 7 for the purpose of protecting the bare chips 1. Further, common terminals of the respective bare chips 1 are electrically connected by the outer leads 5b.

また、 本実施の形態 1のベアチップ 1には、 回路形成面 1 bを保護するパッシ ベーショ ン膜 1 dが形成され、 さらに、 ベアチップ 1 は、 リー ド部 5 aに絶縁性 テープ 9などによって固着されかつ支持されている。 次に、 本実施の形態 1による半導体装置の製造方法について説明する。 Further, a passivation film 1 d for protecting the circuit forming surface 1 b is formed on the bare chip 1 of the first embodiment, and the bare chip 1 is fixed to the lead portion 5 a with an insulating tape 9 or the like. Supported and supported. Next, a method for manufacturing a semiconductor device according to the first embodiment will be described.

まず、 ダイシングによって個々のチップに分割されたベアチップ 1を、 図 3に 示す素子支持基板 1 0のチップ支持部 1 0 aに着脱可能になる様に搭載する。 ここで、 素子支持基板 1 0は、 ベアチップ 1を搭載するチップ支持部 1 0 aと、 バーンインボード 3 (検査基板） とソケッ 卜 1 1などを介して ¾気的に接続する カー ドエッジコネクタ 1 0 bと、 内部配線などによってカー ドエッジコネクタ 1 0 bと電気的に接続しかつ検査用ボンディ ングワイヤ 4が接铳されるリード 1 0 c (接続端子） とを備えており、 本実施の形態 1 においては、 素子支持基板 1 0 としてカードエッジコネクタ 1 0 bとリー ド 1 0 cとが形成されたプリ ン ト配線 基板を用いる。  First, the bare chip 1 divided into individual chips by dicing is mounted on the chip supporting portion 10a of the element supporting substrate 10 shown in FIG. 3 so as to be detachable. Here, the element supporting board 10 is a card supporting section 10a on which the bare chip 1 is mounted, and a card edge connector 1 which is electrically connected to the burn-in board 3 (inspection board) via a socket 11 or the like. 0b and a lead 10c (connection terminal) electrically connected to the card edge connector 10b by internal wiring or the like and connected to the bonding wire 4 for inspection. In 1, the printed circuit board on which the card edge connector 10b and the lead 10c are formed is used as the element supporting board 10.

また、 素子支持基板 1 0は、 例えば、 エポキシ系の樹脂などによって形成され、 そのチップ支持部 1 0 aには、 検査用ボンディ ングワイヤ 4を配置させる貫通孔 1 0 dが設けられ、 さらに、 チップ支持部 1 0 aの周辺には、 下部蓋部材 1 2 ( カバー部材） と嵌合するピン部材 1 3が配置される 4つの連結孔 1 0 eが設けら れている。  The element supporting substrate 10 is formed of, for example, an epoxy resin, and the chip supporting portion 10a is provided with a through hole 10d for disposing the bonding wire 4 for inspection. Around the support portion 10a, four connection holes 10e in which pin members 13 to be fitted with the lower lid member 12 (cover member) are provided are provided.

これにより、 まず、 中心部に貫通孔 1 0 dが形成されかっこの貫通孔 1 0 の 周囲の接铳端子面 1 0 f (第 1主面） にリード 1 0 cが設けられた素子支持基板 1 0の接铳端子面 1 0 f と反対側の第 2主面のチップ支持部 1 0 aにベアチップ 1を配置する。  As a result, first, a through hole 10d is formed in the center, and an element supporting substrate in which the lead 10c is provided on the contact terminal surface 10f (first main surface) around the through hole 10 of the bracket. The bare chip 1 is arranged on the chip supporting portion 10a on the second main surface opposite to the connection terminal surface 10f of the connection terminal 10.

本実施の形態 1 においては、 図 3に示すように、 素子支持基板 1 0によってベ ァチップ 1を支持する際、 すなわち、 ベアチップ 1を素子支持基板 1 0のチップ 支持部 1 0 aに着脱可能に搭載する際に、 ベアチップ 1を素子支持基板 1 0のチ ップ支持側つまり裏面側 1 0 gの前記第 2主面に配置させるとともにベアチップ 1を覆う下部蓋部材 1 2と素子支持基板 1 0のチップ支持部 1 0 aとによってべ ァチップ 1を挟持する。  In the first embodiment, as shown in FIG. 3, when supporting the chip 1 by the element supporting substrate 10, that is, the bare chip 1 is detachably attached to the chip supporting portion 10 a of the element supporting substrate 10. When mounting, the bare chip 1 is arranged on the chip supporting side of the element supporting substrate 10, that is, on the second main surface of the back surface 10 g, and the lower lid member 12 and the element supporting substrate 10 that cover the bare chip 1. The chip 1 is sandwiched between the chip supports 10 a of the chip.

この時、 ベアチップ 1 と素子支持基板 1 0のチップ支持部 1 0 aとの間に絶縁 シート 1 4を配置させる。  At this time, an insulating sheet 14 is disposed between the bare chip 1 and the chip supporting portion 10a of the element supporting substrate 10.

なお、 本実施の形態 1における下部蓋部材 1 2は、 ベアチップ 1を覆う箱形の 形伏のものであり、 例えば、 B Tレジンなどの樹脂やステンレス鋼などの金属材 によって形成されている。 Note that the lower lid member 12 in the first embodiment is a box-shaped profile that covers the bare chip 1, and is made of, for example, a resin such as BT resin or a metal material such as stainless steel. Is formed by

さらに、 本実施の形態 1 における絶縁シート 1 4は、 例えば、 厚さ 5 0 0 m 程度のものであり、 弾性を有したフッ素系樹脂 （例えば、 P T F E ) あるいはポ リイ ミ ド系樹脂などによって形成されている。  Further, the insulating sheet 14 according to the first embodiment has a thickness of, for example, about 500 m, and is formed of an elastic fluororesin (for example, PTFE) or a polyimide resin. Have been.

ここで、 下部蓋部材 1 2と素子支持基板 1 0とによってベアチップ 1を挟持す る際には、 まず、 下部蓋部材 1 2の内部中央付近の所定箇所にベアチップ 1を配 置する。  Here, when the bare chip 1 is sandwiched between the lower lid member 12 and the element supporting substrate 10, first, the bare chip 1 is placed at a predetermined location near the center of the inside of the lower lid member 12.

さらに、 図 3に示すように、 チップ支持部 1 0 aに絶縁シ一ト 1 4を貼り付け た素子支持基板 1 0を準備し、 素子支持基板 1 0と下部蓋部材 1 2とによって絶 縁シート 1 4を介してベアチップ 1を支持する。  Further, as shown in FIG. 3, an element supporting substrate 10 having an insulating sheet 14 attached to the chip supporting portion 10a is prepared, and is isolated by the element supporting substrate 10 and the lower lid member 12. The bare chip 1 is supported via the sheet 14.

この際、 素子支持基板 1 0の 4つの連桔孔 1 0 eの各々にピン部材 1 3を配置 させておき、 ピン部材 1 3に下部蓋部材 1 2を嵌合させて素子支持基板 1 0に取 り付ける。  At this time, the pin member 13 is arranged in each of the four connecting holes 10 e of the element supporting substrate 10, and the lower lid member 12 is fitted to the pin member 13, and the element supporting substrate 10 Attach to

これにより、 図 3に示すように、 下部蓋部材 1 2によってベアチップ 1が素子 支持基板 1 0のチップ支持部 1 0 aに押し付けられ、 その際、 絶縁シ一 ト 1 4力 < 変形する （縮む） ことにより、 ベアチップ 1は固定される。  As a result, as shown in FIG. 3, the bare chip 1 is pressed against the chip supporting portion 10 a of the element supporting substrate 10 by the lower lid member 12, and at that time, the insulating sheet 14 force <deforms (shrinks) Thus, the bare chip 1 is fixed.

その後、 ベアチップ 1のパッ ド 1 a (素子電極） と素子支持基板 1 0のリー ド 1 0 cとを貫通孔 1 0 dに通した検査用ボンディ ングワイヤ 4によって電気的に 接梡する。  Thereafter, the pad 1a (device electrode) of the bare chip 1 and the lead 10c of the device support substrate 10 are electrically connected by the bonding wire for inspection 4 passed through the through hole 10d.

ここで、 本実施の形態 1 においては、 検査用ボンディ ングワイヤ 4によってベ ァチップ 1のパッ ド 1 aと素子支持基板 1 0のリー ド 1 0 cとを電気的に接続す る際に、 検査用ボンディ ングワイヤ 4にアルミニゥム線を用い、 かつ超音波ボン ディ ング （ゥヱッジボンディ ングともいう） によって両者を接続する。  Here, in the first embodiment, when the pad 1 a of the bay chip 1 and the lead 10 c of the element supporting substrate 10 are electrically connected by the bonding wire 4 for inspection, An aluminum wire is used for the bonding wire 4, and the two are connected by ultrasonic bonding (also called edge bonding).

さらに、 検査用ボンテ'ィ ングワイヤ 4によってベアチップ 1のパッ ド 1 aと素 子支持基板 1 0のリード 1 0 cとを電気的に接铳する際に、 図 4 ( a ) に示すよ うに、 素子支持基板 1 0のリード 1 0 cと検査用ボンディ ングワイヤ 4 とを接続 した後、 ベアチップ 1のパッ ド 1 aと検査用ボンディ ングワイヤ 4 とを接続する。 すなわち、 超音波ボンディ ング装置を用いてワイヤボンディ ングを行う際に、 まず、 素子支持基板 1 0のリード 1 0 cと検査用ボンディ ングワイヤ 4 とを接続 し、 その後、 図 4 ( b ) に示すように、 素子支持基板 1 0の貫通孔 1 0 dに検査 用ボンディ ングワイヤ 4を通して検査用ボンディ ングワイヤ 4 とベアチップ 1の パッ ド 1 aとを接铳する。 Further, when the pad 1a of the bare chip 1 is electrically connected to the lead 10c of the element supporting substrate 10 by the bonding wire 4 for inspection, as shown in FIG. After connecting the leads 10c of the element supporting board 10 and the bonding wires 4 for inspection, the pads 1a of the bare chip 1 and the bonding wires 4 for inspection are connected. That is, when performing wire bonding using an ultrasonic bonding apparatus, first, the lead 10 c of the element supporting substrate 10 is connected to the bonding wire 4 for inspection. Then, as shown in FIG. 4 (b), the bonding wire 4 for inspection is passed through the bonding wire 4 for inspection through the through hole 10 d of the element supporting substrate 10, and the pad 1 a of the bare chip 1 is connected. .

なお、 本実施の形態 1では、 検査終了後にベアチップ 1 と検査用ボンディ ング ワイヤ 4 とを剝離して分離する際に、 ベアチップ 1のバッ ド 1 a上に検査用ボン デイ ングワイヤ 4の素子側ワイヤ接合部 4 a (図 4 ( c ) 参照） が残留しないよ うに分離する。  In the first embodiment, when the bare chip 1 and the bonding wire for inspection 4 are separated and separated after the inspection, the element-side wire of the bonding wire for inspection 4 is placed on the pad 1 a of the bare chip 1. Separate so that the joint 4a (see Fig. 4 (c)) does not remain.

したがって、 パッ ド 1 aに素子側ワイヤ接合部 4 aを残留させないためのベア チップ 1側 （検査用ボンディ ングワイヤ 4とベアチップ 1のパッ ド 1 aとを接続 する際） のボンディ ング条件として、 例えば、 超音波パワーを装置の最大パワー の 1 0〜6 0 %程度、 最適には 1 5 %、 荷重を 1 0〜4 5 g程度、 最適には 3 5 g、 および超音波印加時間を 1 0〜4 0 m s e c程度、 最適には 3 0 m s e cに 設定し、 かつボンディ ングワイヤ径 2 5 , ボンディ ングツールの圧着部長さ 2 5〜6 0 m程度、 最適には 5 1 m、 圧着部幅 9 0 - 1 1 0 mを使用し、 これにより、 超音波ボンディ ングを行う。  Therefore, the bonding conditions on the bare chip 1 side (when connecting the bonding wire 4 for inspection and the pad 1a of the bare chip 1) to prevent the element-side wire joint 4a from remaining on the pad 1a are as follows, for example. The ultrasonic power is about 10 to 60% of the maximum power of the device, the optimal is 15%, the load is about 10 to 45 g, the optimal is 35 g, and the ultrasonic application time is 10 ~ 40 msec, optimally set to 30 msec, and bonding wire diameter 25, crimping part length of bonding tool 25-60 m, optimally 51 m, crimping part width 90 -Use 110 m, thereby performing ultrasonic bonding.

なお、 前記ボンディ ング条件は、 検査用ボンディ ングワイヤ 4とべァチップ 1 のパッ ド 1 aとの接続強度を検査用ボンディ ングワイヤ 4 と素子支持基板 1 0の リー ド 1 0 cとの接続強度より小さくするものである。  The bonding conditions are such that the connection strength between the bonding wire 4 for inspection and the pad 1a of the base chip 1 is smaller than the connection strength between the bonding wire 4 for inspection and the lead 10c of the element supporting board 10. Things.

その結果、 ベアチップ 1のパッ ド 1 aと素子支持基板 1 0のリード 1 0 cとは、 検査用ボンディ ングワイヤ 4によって電気的に接続されるとともに、 図 4 ( c ) に示すように、 検査用ボンディ ングワイヤ 4 とベアチップ 1 とは、 ベアチップ 1 のパッ ド 1 aで素子側ワイヤ接合部 4 aが形成されて接続されている。  As a result, the pad 1a of the bare chip 1 and the lead 10c of the element supporting substrate 10 are electrically connected by the bonding wire 4 for inspection and, as shown in FIG. The bonding wire 4 and the bare chip 1 are connected to each other by forming an element-side wire bonding portion 4 a with the pad 1 a of the bare chip 1.

その後、 図 3に示すように、 素子支持基板 1 0の下部蓋部材 1 2を取り付けた 面と反対側の面すなわち接铳端子面 1 0 f に、 上部蓋部材 1 5を取り付ける。 この際の上部蓋部材 1 5の固定方法は、 下部蓋部材 1 2と同様に、 ピン部材 i 3を介し、 このピン部材 1 3に嵌合させて固定する。  Thereafter, as shown in FIG. 3, the upper cover member 15 is attached to the surface of the element supporting substrate 10 opposite to the surface to which the lower cover member 12 is attached, that is, to the contact terminal surface 10f. In this case, the upper lid member 15 is fixed by fitting it to the pin member 13 via the pin member i3, similarly to the lower lid member 12.

これにより、 ベアチップ 1および検査用ボンディ ングワイヤ 4を上部蓋部材 1 5と素子支持基板 1 0 と下部蓋部材 1 2とによって つてほぼ密閉伏態にするこ とができる。 したがって、 ベアチップ 1にゴミや異物などが付着しない雰囲気においてベア チップ 1を検査することができ、 バーンイン検査の信頼性を向上させることがで きる。 As a result, the bare chip 1 and the bonding wire for inspection 4 can be brought into a substantially hermetically closed state by the upper lid member 15, the element supporting substrate 10 and the lower lid member 12. Therefore, the bare chip 1 can be inspected in an atmosphere in which dust and foreign matter do not adhere to the bare chip 1, and the reliability of the burn-in inspection can be improved.

これにより、 ベアチップキャリア 1 8を組み立てることができる。  Thereby, the bare chip carrier 18 can be assembled.

なお、 上部蓋部材 1 5は、 下部蓋部材 1 2と同様に、 ベアチップ 1を覆う箱形 の形状のものであり、 例えば、 B Tレジンなどの樹脂やステンレス鋼などの金属 材によって形成されている。  The upper lid member 15 has a box-like shape that covers the bare chip 1 like the lower lid member 12 and is made of, for example, a resin such as BT resin or a metal material such as stainless steel. .

その後、 テス トボー ドなどのバーンインボー ド 3に設置されたソケッ ト 1 1 に ベアチップキヤ リア 1 8の素子支持基板 1 0を差し込む。  After that, the element supporting board 10 of the bare chip carrier 18 is inserted into the socket 11 installed on the burn-in board 3 such as a test board.

これにより、 素子支持基板 1 0のカー ドエッジコネクタ 1 0 bとソケッ ト 1 I の電極とが電気的に接铳するとともに、 素子支持基板 1 0のカードエッジコネク 夕 1 0 bはソケッ ト 1 1を介してバーンィンボード 3上の基板電極 3 aとも電気 的に接続する。  As a result, the card edge connector 10b of the element support board 10 is electrically connected to the electrode of the socket 1I, and the card edge connector 10b of the element support board 10 is connected to the socket 1b. It is also electrically connected to the substrate electrode 3 a on the burn-in board 3 via 1.

その後、 ベアチップ 1に対して所定の検査を行う。  Thereafter, a predetermined inspection is performed on the bare chip 1.

この際行う前記検査は、 本実施の形態 1では、 バーンイン検査であり、 図 7に 示すバーンィンボード 3を用いて行う。  The inspection performed at this time is a burn-in inspection in the first embodiment, and is performed using the burn-in board 3 shown in FIG.

検査終了後、 ベアチップ 1 と検査用ボンディ ングワイヤ 4とを分離する。 まず、 バーンィンボー ド 3上のソケッ ト 1 1からベアチップキャ リア 1 8を抜 き取り、 さらに、 素子支持基板 1 0から図 3に示す上部蓋部材 1 5を取り外し、 続いて、 下部蓋部材 1 2を取り外す。  After the inspection, the bare chip 1 and the bonding wire 4 for inspection are separated. First, the bare chip carrier 18 is removed from the socket 11 on the burn-in board 3, the upper cover member 15 shown in FIG. 3 is removed from the element supporting board 10, and then the lower cover member 1 2 Remove.

その後、 ベアチップ 1 と検査用ボンディ ングワイヤ 4 とを分離させる。  After that, the bare chip 1 and the bonding wire for inspection 4 are separated.

なお、 本実施の形態 1 においては、 ベアチップ 1 と検査用ボンディ ングワイヤ 4とを分離する際に、 図 5に示すように、 ベアチップ 1のパッ ド 1 aが形成され た回路形成面 1 bと反対側の非回路形成面 1 cを吸着コレツ 卜 1 6 (チップ保持 手段） によって吸引して両者を分離させる。  In the first embodiment, when the bare chip 1 and the bonding wire for inspection 4 are separated from each other, as shown in FIG. 5, the bare chip 1 is opposite to the circuit forming surface 1 b on which the pad 1 a is formed. The non-circuit forming surface 1c on the side is suctioned by the suction collet 16 (tip holding means) to separate them.

この際、 素子支持基板 1 0のリード 1 0 cにおける検査用ボンディ ングワイヤ 4の接合箇所 4 cを上方から押さえ付けてベアチップ 1の非回路形成面 1 cを吸 引することが好ましい。  At this time, it is preferable that the non-circuit-forming surface 1c of the bare chip 1 be sucked by pressing the bonding portion 4c of the bonding wire 4 for inspection on the lead 10c of the element supporting substrate 10 from above.

すなわち、 検査用ボンディ ングワイヤ 4の接合箇所 4 cである基板側ワイヤ接 合部 4 dを上方から押さえ付けて固定しておく ことにより、 検査用ボンディ ング ワイヤ 4をベアチップ 1から確実に剝離させることができる。 In other words, the board side wire connection, which is the joint 4c of the inspection bonding wire 4, By pressing and fixing the joint 4 d from above, the bonding wire for inspection 4 can be securely separated from the bare chip 1.

その結果、 図 6に示すように、 ベアチップ 1のパッ ド 1 a上には、 検査用ボン デイ ングワイヤ 4 (図 4参照） の圧痕 4 bだけが残り、 図 4に示す素子側ワイヤ 接合部 4 aを残留させずにベアチップ 1 と前記検査用ボンディ ングワイヤ 4とを 分離させることができる。  As a result, as shown in FIG. 6, only the indentation 4b of the bonding wire for inspection 4 (see FIG. 4) remains on the pad 1a of the bare chip 1, and the element-side wire joint 4 shown in FIG. The bare chip 1 and the bonding wire for inspection 4 can be separated without leaving a.

铳いて、 ベアチップ 1を素子支持基板 1 0から取り外す。  Then, the bare chip 1 is removed from the element supporting substrate 10.

なお、 本実施の形態 1においては、 ベアチップ 1を吸着コレツ ト 1 6によって 吸引してベアチップ 1 と検査用ボンディ ングワイヤ 4 とを分離させるため、 その 際同時に、 ベアチップ 1を素子支持基板 1 0から取り外すことが可能になる。 これにより、 ベアチップ 1の良 ·不良を判別することができ、 K G Dとして良 品のベアチップ 1を取得できる。  In the first embodiment, the bare chip 1 is removed from the element supporting board 10 at the same time as the bare chip 1 is suctioned by the suction collet 16 to separate the bare chip 1 from the bonding wire 4 for inspection. It becomes possible. This makes it possible to determine whether the bare chip 1 is good or bad, and obtain a good bare chip 1 as KGD.

その後、 図 1 に示す本実施の形態 1 における半導体装置であるマルチチップモ ジュール 2を製造する際には、 前記検査によって選別されたベアチップ 1、 すな わち、 良品と判定されたベアチップ 1 ( K G D ) をリー ド部 5 aに絶緣性テープ 9を用いて取り付ける （固着する） 。  Thereafter, when manufacturing the multi-chip module 2 which is the semiconductor device according to the first embodiment shown in FIG. 1, the bare chip 1 selected by the inspection, that is, the bare chip 1 ( KGD) is attached (fixed) to the lead portion 5 a using the insulating tape 9.

さらに、 ベアチップ 1のパッ ド 1 aとリード部 5 aとを金線などのボンディ ン グワイヤ 8によって電気的に接铳する。  Further, the pad 1 a of the bare chip 1 and the lead portion 5 a are electrically connected by a bonding wire 8 such as a gold wire.

この際、 本実施の形態 1 は、 図 4および図 6に示すように、 検査用ボンディ ン グワイャ 4 とべァチップ 1 とを分離させる際に、 ベアチップ 1のパッ ド 1 a上に 検査用ボンディ ングワイヤ 4の素子側ワイヤ接合部 4 aを残留させずにベアチッ プ 1 と検査用ボンディ ングワイヤ 4とを分離した場合であるため、 マルチチップ モジュール 2においては、 ボンディ ングワイヤ 8とベアチップ 1のパッ ド 1 aと を信頼性よく電気的に接続することが可能である。  At this time, in the first embodiment, as shown in FIGS. 4 and 6, when the inspection bonding wire 4 and the base chip 1 are separated from each other, the inspection bonding wire 4 is placed on the pad 1 a of the bare chip 1. In the multi-chip module 2, the bonding wire 8 and the pad 1a of the bare chip 1 are separated from the bonding chip 4 for inspection because the bare chip 1 and the bonding wire 4 for inspection are separated without leaving the wire bonding portion 4a on the element side. Can be electrically connected with high reliability.

また、 本実施の形態 1のマルチチップモジュール 2は、 4個のベアチップ 1を 有しているため、 リー ド部 5 aに支持された状態の 4個のベアチップ 1を 4展に 積展配置する。  Further, since the multi-chip module 2 of the first embodiment has four bare chips 1, the four bare chips 1 supported by the lead portion 5a are stacked and arranged in four stages. .

つまり、 図 1に示すように、 ペレツ ト単体で予め検査して選別された 4個のベ ァチップ 1を積層配置した後、 4個のベアチップ 1 とその周辺部 6とをべァチッ プ 1 やボンディ ングワイヤ 8を保護する目的で封止樹脂 7によって封止する。 ここで、 本実施の形態 1 による封止は、 樹脂による封止のため、 例えば、 トラ ンスファーモールド方法ゃポッティ ング方法などによって行う。 In other words, as shown in Fig. 1, after stacking and arranging four bare chips 1 that have been inspected and selected by a single pellet in advance, the four bare chips 1 and their peripheral portions 6 are baked. It is sealed with a sealing resin 7 for the purpose of protecting the step 1 and the bonding wire 8. Here, the sealing according to the first embodiment is performed by, for example, a transfer molding method ゃ a potting method or the like for sealing with a resin.

これにより、 予め検査して選別された良品のベアチップ 1 とその周辺部 6とが 封止樹脂 7によって封止される。  As a result, the non-defective bare chip 1 and its peripheral portion 6 that have been inspected and selected in advance are sealed with the sealing resin 7.

その後、 それぞれのベアチップ 1における共通端子と各々に接铳されたリ一ド 部 5 a同士をァウタリード 5 bによって電気的に接铳する。  Thereafter, the common terminal of each bare chip 1 and the lead portions 5a connected thereto are electrically connected to each other by the outer leads 5b.

この際、 インナリー ドであるリー ド部 5 aとァウタリー ド 5 bとをレーザ加工 などによって接合する。  At this time, the lead portion 5a, which is the inner lead, and the outer lead 5b are joined by laser processing or the like.

なお、 ァウタリー ド 5 bは、 その一端が予め所定の形状に曲げ加工されたもの である。  It should be noted that one end of the portal 5b is previously bent into a predetermined shape.

また、 本実施の形態 1においては、 検査終了後にベアチップ 1 と検査用ボンデ ィ ングワイヤ 4 とを分離する際に、 ベアチップ 1のパッ ド 1 a上に検査用ボンデ ィ ングワイヤ 4の素子側ワイヤ接合部 4 aが残留しないように分離させるため、 これにより、 取得した良品のベアチップ I ( K G D ) を、 それ自体を製品と して 出荷してもよい。  In the first embodiment, when the bare chip 1 and the bonding wire 4 for inspection are separated after the completion of the inspection, the element-side wire bonding portion of the bonding wire 4 for inspection is placed on the pad 1 a of the bare chip 1. In this way, the obtained non-defective bare chip I (KGD) may be shipped as a product in itself, so that 4a is separated so as not to remain.

本実施の形態 1の半導体装置の製造方法および半導体装置によれば、 以下のよ うな作用効果が得られる。  According to the method of manufacturing a semiconductor device and the semiconductor device of the first embodiment, the following operational effects can be obtained.

すなわち、 ベアチップ 1のパッ ド 1 aと素子支持基板 1 0のリー ド 1 0 cとを 検査用ボンディ ングワイヤ 4を用いて電気的に接続してベアチップ 1をバーンィ ン検査し、 検査終了後、 ベアチップ 1 と検査用ボンディ ングワイヤ 4 とを分離し て良品のベアチップ 1を選別することにより、 既存のワイヤボンディ ング装置を 用いて K G Dを取得することができる。  That is, the pad 1a of the bare chip 1 and the lead 10c of the element supporting substrate 10 are electrically connected to each other using the bonding wire 4 for inspection, and the bare chip 1 is subjected to burn-in inspection. By separating 1 and the bonding wire 4 for inspection and selecting a good bare chip 1, KGD can be obtained using the existing wire bonding equipment.

つまり、 ベアチップ 1 と素子支持基板 1 0との接続をワイヤボンディ ングによ つて行うため、 既存のワイヤボンディ ング装置をそのまま用いることが可能にな る。  That is, since the connection between the bare chip 1 and the element supporting board 10 is performed by wire bonding, the existing wire bonding apparatus can be used as it is.

したがって、 前記既存のワイヤボンディ ング装置を用いることにより、 ワイヤ ボンディ ング時のベアチップ 1のパッ ド 1 aの位置や素子支持基板 1 0のリー ド 1 0 cの位置をそれぞれ個別に位置検出することができる。 これにより、 素子支持基板 1 0の寸法精度を緩和することができる。 Therefore, by using the existing wire bonding apparatus, the position of the pad 1a of the bare chip 1 and the position of the lead 10c of the element supporting substrate 10 at the time of wire bonding can be individually detected. Can be. Thereby, the dimensional accuracy of the element supporting substrate 10 can be relaxed.

その桔果、 ベアチップキャリア 1 8の構造を簡略化させることができる。  As a result, the structure of the bare chip carrier 18 can be simplified.

さらに、 ワイヤボンディ ング時のベアチップ 1のパッ ド i aの位置や素子支持 基板 1 0のリード 1 0 cの位置をそれぞれ個別に位置検出することができるため- ベアチップ 1の品種毎に素子支持基板 1 0を準備しなくて済む。  Furthermore, since the position of the pad ia of the bare chip 1 and the position of the lead 10 c of the element supporting substrate 10 during wire bonding can be individually detected, the element supporting substrate 1 is provided for each type of the bare chip 1. There is no need to prepare 0.

これにより、 素子支持基板 1 0およびベアチップキヤ リア 1 8の数を减らすこ とができ、 K G D取得にかかるコス トを低減することができる。  As a result, the number of element supporting substrates 10 and bare chip carriers 18 can be reduced, and the cost for obtaining KGD can be reduced.

また、 素子支持基板 1 0によってベアチップ 1を支持する際にもワイヤボンデ ィ ング装匿を用いることにより、 ワイヤボンディ ング装置により自動認識可能な ため、 厳密な位置決め精度が要求されず、 ベアチップ 1の位置決めなどを容易に 行うことができる。  Also, when the bare chip 1 is supported by the element supporting substrate 10, the wire bonding apparatus can automatically recognize it by using the wire bonding apparatus, so that strict positioning accuracy is not required, and the positioning of the bare chip 1 is not required. Can be easily performed.

その結果、 ベアチップ 1を搭載する際の高精度の位 S合わせが不要となるため、 量産化する際にも専用のチップ搭載装置を準備する必要がなくなる。  As a result, high-precision alignment when mounting the bare chip 1 is not required, so that it is not necessary to prepare a dedicated chip mounting device even in mass production.

これにより、 無駄な設備投資を行う必要がなく、 K G D取得にかかるコス トを 低減することができる。  This eliminates the need for unnecessary capital investment and can reduce the cost of acquiring KGD.

また、 ベアチップ 1 と素子支持基板 1 0とを検査用ボンディ ングワイヤ 4によ つて接铳してベアチップ 1を検査するとともに、 検査終了後、 ベアチップ 1 と検 査用ボンディ ングワイヤ 4 とを分離することにより、 素子支持基板 1 0のリー ド 1 0 cにべァチッブ 1のパッ ド 1 aを直接押し付けていないため、 素子支持基板 I 0のリード 1 0 cの劣化ゃゴミの付着を防止できる。  In addition, the bare chip 1 and the element supporting substrate 10 are connected by the bonding wire 4 for inspection to inspect the bare chip 1, and after the inspection is completed, the bare chip 1 and the bonding wire 4 for inspection are separated. Since the pad 1a of the base 1 is not directly pressed against the lead 10c of the element supporting substrate 10, deterioration of the lead 10c of the element supporting substrate I0 and adhesion of dust can be prevented.

これにより、 素子支持基板 1 0とベアチップ 1 との接触抵抗が高くなることを 防止でき、 その結果、 良好な電気接続を得ることが可能になる。  As a result, it is possible to prevent the contact resistance between the element supporting substrate 10 and the bare chip 1 from increasing, and as a result, it is possible to obtain a good electrical connection.

したがって、 高性能な K G Dを安定して取得することができる。  Therefore, high-performance KGD can be obtained stably.

また、 検査終了後にベアチップ 1 と検査用ボンディ ングワイヤ 4 とを分離する 際に、 ベアチッブ 1のパッ ド 1 a上に検査用ボンディ ングワイヤ 4の素子側ワイ ャ接合部 4 aが残留しないように分離することにより、 ベアチップ 1をマルチチ ップモジュール 2などの半導体装置に組み込むのではなく、 そのまま単体で製品 化して出荷することが可能になる。  When the bare chip 1 and the bonding wire 4 for inspection are separated after the inspection is completed, the bonding is performed so that the wire bonding portion 4a on the element side of the bonding wire 4 for inspection does not remain on the pad 1a of the bare chip 1. As a result, the bare chip 1 can be commercialized as a single product and shipped without being incorporated into a semiconductor device such as the multi-chip module 2.

さらに、 素子支持基板 1 0としてリード 1 0 cが形成されたプリ ン ト配線基板 を用いることにより、 素子支持基板 1 0の構造を容易にできるとともに、 素子支 持基板 1 0とべァチップキヤ リア 1 8とを安い費用で形成することができる。 また、 検査用ボンディ ングワイヤ 4にアルミニウム線を用い、 かつ超音波ボン ディ ングによってベアチップ 1のパッ ド 1 aと素子支持基板 1 0のリー ド 1 0 c とを電気的に接铳することにより、 検査終了後にベアチップ 1 と検査用ボンディ ングワイヤ 4 とを分雜する際、 検査用ボンディ ングワイヤ 4を剝雜し易くするこ とができる。 Furthermore, a printed wiring board on which leads 10c are formed as element support board 10 By using this, the structure of the element supporting substrate 10 can be easily formed, and the element supporting substrate 10 and the base chip carrier 18 can be formed at low cost. Further, by using an aluminum wire as the bonding wire 4 for inspection and electrically connecting the pad 1 a of the bare chip 1 and the lead 10 c of the element supporting substrate 10 by ultrasonic bonding, When the bare chip 1 and the bonding wire for inspection 4 are separated after completion of the inspection, the bonding wire for inspection 4 can be easily formed.

これにより、 ベアチップ 1のバッ ド 1 a上に検査用ボンディ ングワイヤ 4の素 子側ワイヤ接合部 4 aが残留しないように分離させることが可能になる。  As a result, it is possible to separate the bonding wire 4a of the inspection side so that the element side wire bonding portion 4a does not remain on the pad 1a of the bare chip 1.

その结果、 ベアチップ 1のパッ ド 1 aを損傷させることがないため、 前記同様 に、 ベアチップ 1をそのまま単体で製品化して出荷することができる。  As a result, since the pad 1a of the bare chip 1 is not damaged, the bare chip 1 can be commercialized and shipped as it is, as described above.

ここで、 超音波ボンディ ングの際に、 検査用ボンディ ングワイヤ 4 とべァチッ プ 1のパッ ド 1 aとの接合強度を弱く設定して接合させることにより、 パッ ド 1 a上に素子側ワイヤ接合部 4 aが残留することを防止できる。  Here, at the time of ultrasonic bonding, by setting the bonding strength between the bonding wire for inspection 4 and the pad 1a of the tape 1 to be weak, the bonding wire on the element 1 side is formed on the pad 1a. 4a can be prevented from remaining.

また、 ベアチップ 1を Sう下部蓋部材 1 2と素子支持基板 1 0 とによって絶縁 シート 1 4を介してべァチッブ 1を挟持することにより、 ベアチッブ 1の固定に 接着剤を用いていないため、 検査終了後に下部蓋部材 1 2を取り外すだけでベア チップ 1を容易にかつ汚すことなく、 素子支持基板 1 0から分離させることがで きる。  In addition, since the base 1 is sandwiched between the lower lid member 12 for holding the bare chip 1 and the element supporting substrate 10 via the insulating sheet 14, no adhesive is used for fixing the bare chip 1. By simply removing the lower lid member 12 after completion, the bare chip 1 can be separated from the element supporting substrate 10 easily and without soiling.

これにより、 ベアチップ 1を損傷させることがないため、 前記同様に、 ベアチ ッブ 1をそのまま単体で製品化して出荷することができる。  As a result, since the bare chip 1 is not damaged, the bare chip 1 can be commercialized and shipped as it is, as described above.

さらに、 素子支持基板 1 0とベアチップ 1 とを検査用ボンディ ングワイヤ 4に よって接铳する際に、 まず、 素子支持基板 1 0のリード 1 0 cと検査用ボンディ ングワイヤ 4 とを接^し、 その後、 ベアチップ 1のパッ ド 1 aと検査用ボンディ ングワイヤ 4とを接铳することにより、 ベアチップ 1のパッ ド 1 a上にピックテ ールが形成されることを防止できる。  Further, when the element supporting board 10 and the bare chip 1 are connected by the bonding wire 4 for inspection, first, the lead 10 c of the element supporting board 10 is connected to the bonding wire 4 for inspection, and thereafter, By connecting the pad 1 a of the bare chip 1 and the bonding wire 4 for inspection, it is possible to prevent a pick tail from being formed on the pad 1 a of the bare chip 1.

これにより、 図 4 ( c ) に示す素子側ワイヤ接合部 4 aにおけるネック部 4 e の破断強度の低下を抑制することが可能になる。  This makes it possible to suppress a decrease in the breaking strength of the neck portion 4e at the element-side wire joint portion 4a shown in FIG. 4 (c).

その桔果、 素子側ワイヤ接合部 4 aを残留させずに検査用ボンディ ングワイヤ 4 とべァチップ 1 とを分離できるため、 ベアチップ 1をそのまま単体で製品化し て出荷することができる。 As a result, a bonding wire for inspection without leaving the element-side wire joint 4a Since 4 and the bare chip 1 can be separated, the bare chip 1 can be commercialized as it is and shipped.

また、 ベアチップ 1を素子支持基板 1 0の裏面側 1 0 gにおいて支持している ため、 検査終了後、 ベアチップ 1 と検査用ボンディ ングワイヤ 4 とを分離する際 に、 ベアチップ 1の非回路形成面 1 cを吸引することが可能になり、 その锆果、 ベアチップ 1の非回路形成面 1 cを吸引して両者を分雜することにより、 全ての 検査用ボンディ ングワイヤ 4とベアチップ 1 とを一括して分離することができる とともに、 一括して検査用ボンディ ングワイヤ 4を除去することが可能になる。 これにより、 K G Dを取得する際に費やす時間を短縮することができる。 さらに、 ベアチップ 1の非回路形成面 1 cを吸引することにより、 ベアチップ 1 と検査用ボンディ ングワイヤ 4 とを分離させる工程と、 ベアチップ 1を素子支 持基板 1 0から取り外す工程とを同時に行うことが可能になる。  Further, since the bare chip 1 is supported on the back surface 10 g of the element supporting substrate 10, when the bare chip 1 is separated from the bonding wire 4 for inspection after the inspection, the non-circuit forming surface 1 of the bare chip 1 is separated. As a result, the non-circuit-forming surface 1c of the bare chip 1 is sucked and separated from each other, so that all the inspection bonding wires 4 and the bare chip 1 are collectively collected. In addition to being able to be separated, the bonding wire for inspection 4 can be removed collectively. As a result, the time spent for obtaining the KGD can be reduced. Furthermore, the step of separating the bare chip 1 from the bonding wire 4 for inspection by sucking the non-circuit forming surface 1 c of the bare chip 1 and the step of removing the bare chip 1 from the element supporting substrate 10 can be performed simultaneously. Will be possible.

これにより、 前記同様、 K G Dを取得する際に費やす時間を短縮することがで きる。  As a result, as described above, it is possible to reduce the time spent for acquiring the KGD.

また、 素子支持基板 1 0において、 外部接続端子であるカードエッジコネクタ 1 0 bが篾通孔 1 0 dの両側に設けられていることにより、 片側の力一ドエツジ コネクタ 1 0 bと他方側のカー ドエッジコネクタ 1 O bとを分けて使用できるた め、 バーンイン検査を行う際に、 素子支持基板 1 0を複数回使用することができ る。  In addition, since the card edge connector 10b, which is an external connection terminal, is provided on both sides of the through hole 10d on the element supporting board 10, the force connector 10b on one side and the connector 10b on the other side are provided. Since the card edge connector 1 Ob can be used separately, the element supporting board 10 can be used a plurality of times during burn-in inspection.

これにより、 素子支持基板 1 0の寿命を長くすることができる。  Thus, the life of the element supporting substrate 10 can be extended.

さらに、 検査用ボンディ ングワイヤ 4にアルミニゥム線を用い、 かつマルチチ ップモジュール 2 (半導体装置） のワイヤボンディ ングに金からなるボンディ ン グワイヤ 8を用いることにより、 検査用ボンディ ングワイヤ 4をべァチッブ 1か ら分離させる際には、 ベアチップ 1のパッ ド 1 aを損傷させることなくかつ容易 に分離させることができ、 さらに、 マルチチップモジュール 2においてボンディ ングワイヤ 8の腐食などを防止することができる。  Furthermore, the bonding wire 4 for inspection is separated from the base 1 by using an aluminum wire for the bonding wire 4 for inspection and the bonding wire 8 made of gold for the wire bonding of the multi-chip module 2 (semiconductor device). In this case, the pad 1 a of the bare chip 1 can be easily separated without damaging it, and furthermore, the bonding wire 8 in the multi-chip module 2 can be prevented from being corroded.

これにより、 K G Dによって良品のベアチップ 1を取得する際にも、 ベアチッ プ 1の品質を向上させることが可能になり、 さらに、 マルチチップモジュール 2 の品質も向上させることができる。 その結果、 高性能および高信頼性を有する K G Dを容易に取得することが可能 になる。 As a result, the quality of the bare chip 1 can be improved even when a good bare chip 1 is obtained by KGD, and the quality of the multi-chip module 2 can be improved. As a result, it is possible to easily obtain KGD with high performance and high reliability.

本発明の実施の形態 2を、 図 8の検査用ボンディ ングワイヤとベアチップとの 分離方法を示す部分断面図および拡大部分平面図、 図 9の半導体装置の構造を示 す部分断面図を用いて説明する。  Embodiment 2 of the present invention will be described with reference to a partial sectional view and an enlarged partial plan view showing a method of separating a bonding wire for inspection and a bare chip shown in FIG. 8, and a partial sectional view showing the structure of a semiconductor device shown in FIG. I do.

本実施の形態 2の半導体装置の製造方法は、 バーンイン検査終了後、 ベアチッ プ 1のパッ ド 1 a上に検査用ボンディ ングワイヤ 4の素子側ワイヤ接合部 4 aを 残留させてベアチップ 1 と検査用ボンディ ングワイヤ 4 とを分離するものである。 すなわち、 前記実施の形態 1においては、 検査終了後にベアチップ 1 と検査用 ボンディ ングワイヤ 4とを分雜する際、 ベアチップ 1のパッ ド 1 a上に検査用ボ ンディ ングワイヤ 4の素子側ワイヤ接合部 4 aが残留しないように分離したのに 対して、 本実施の形態 2は、 図 8に示す検査用ボンディ ングワイヤ 4 とべァチッ プ 1 との分離方法のように、 バーンィン検査終了後、 ベアチップ 1のパッ ド 1 a 上に検査用ボンディ ングワイヤ 4の素子側ワイヤ接合部 4 aを残留させてベアチ ップ 1 と検査用ボンディ ングワイヤ 4とを分離するものである （図 8 ( a ) 参照In the method of manufacturing the semiconductor device according to the second embodiment, after the burn-in inspection is completed, the element-side wire bonding portion 4a of the bonding wire 4 for inspection is left on the pad 1a of the The bonding wire 4 is separated. That is, in the first embodiment, when the bare chip 1 and the bonding wire for inspection 4 are separated after the completion of the inspection, the element-side wire bonding portion 4 of the bonding wire for inspection 4 is placed on the pad 1 a of the bare chip 1. In the second embodiment, as shown in FIG. 8, the bonding of the bare chip 1 is completed after the burn-in inspection is completed, as in the method of separating the bonding wire 4 for inspection and the tape 1 shown in FIG. in which de 1 leaving a device-side wire bonding portion 4 a of the testing Bondi Nguwaiya 4 on a separation of the inspection Bondi Nguwaiya 4 and Beachi-up 1 (see FIG. 8 (a) see

) o ) o

つまり、 パッ ド 1 aに素子側ワイヤ接合部 4 aを残留させるためのベアチップ 1側 （検査用ボンディ ングワイヤ 4 とベアチップ 1のパッ ド 1 aとを接铳する際 ) のボンディ ング条件として、 例えば、 超音波パワーを装置の最大パワーの 2 5 〜 4 0 %程度、 最適には 3 0 % (前記実施の形態 1の時より超音波パワーを大き くする） 、 荷重を 2 5〜6 0 g程度、 最適には 3 5 g、 および時間を 2 5〜3 5 m s e c程度、 最適には 3 0 m s e cに設定し、 これにより、 超音波ボンディ ン グを行う。  In other words, the bonding conditions on the bare chip 1 side (when bonding the bonding wire 4 for inspection and the pad 1a of the bare chip 1) to leave the element side wire bonding portion 4a on the pad 1a are as follows. The ultrasonic power is about 25 to 40% of the maximum power of the apparatus, and optimally 30% (ultrasonic power is larger than in the first embodiment), and the load is 25 to 60 g. Degree, optimally 35 g, and the time is set to about 25 to 35 msec, optimally 30 msec, thereby performing ultrasonic bonding.

これにより、 ベアチップ 1のパッ ド 1 aと検査用ボンディ ングワイヤ 4 との接 铳が強化されるため、 図 5に示す吸着コレッ ト 1 6 (チップ保持手段） などを用 い、 図 8 ( a ) に示すように、 ベアチップ 1 と検査用ボンディ ングワイヤ 4 とを 分離させる際に、 パッ ド 1 a上に検査用ボンディ ングワイヤ 4の素子側ワイヤ接 合部 4 aを残留させた状態にすることができる。 つまり、 検査用ボンディ ングヮ ィャ 4を素子側ワイヤ接合部 4 aごと剝雜させるのではなく、 検査用ボンディ ン グワイヤ 4の素子側ワイャ接合部 4 aのネック部 4 e (図 8 ( b ) 参照） からの 切断によってベアチップ 1 と検査用ボンディ ングワイヤ 4 とを分離する。 As a result, the connection between the pad 1 a of the bare chip 1 and the bonding wire 4 for inspection is strengthened, and the suction collet 16 (tip holding means) shown in FIG. 5 is used, and FIG. 8 (a) When the bare chip 1 and the bonding wire 4 for inspection are separated from each other, the element-side wire bonding portion 4a of the bonding wire 4 for inspection can be left on the pad 1a as shown in FIG. . In other words, the bonding bonder 4 for inspection is not covered with the wire bonding portion 4a on the element side, but the bonding bonder 4 for inspection is bonded. The bare chip 1 and the bonding wire 4 for inspection are separated by cutting the wire 4 from the neck 4 e (see FIG. 8 (b)) of the wire-side connection 4 a on the element side.

なお、 ベアチップ 1のパッ ド 1 a上に素子側ワイヤ接合部 4 aを残留させて良 品のベアチップ 1すなわち K G Dを取得した場合においても、 このベアチップ 1 を図 1 に示したマルチチップモジュール 2に用いることも可能であり、 また、 図 9に示す素子搭載部材のタブ 5 cにべァチップ 1を搭載するタィプの半導体装置 などに用いることも可能である。  Note that even when a non-defective bare chip 1, that is, a KGD is obtained by leaving the element-side wire bonding portion 4a on the pad 1a of the bare chip 1, this bare chip 1 is used for the multi-chip module 2 shown in FIG. It is also possible to use it for a type of semiconductor device in which the base chip 1 is mounted on the tab 5c of the element mounting member shown in FIG.

この埸合、 図 8 ( a ) に示す検査用ボンディ ングワイヤ 4には金線を用い、 さ らに、 リー ド部 5 aとベアチップ 1のパッ ド 1 aとを接続するボンディ ングワイ ャ 8にも金線を用いることが好ましい。  In this case, a gold wire is used for the bonding wire 4 for inspection shown in FIG. 8 (a), and the bonding wire 8 for connecting the lead portion 5 a to the pad 1 a of the bare chip 1 is also used. It is preferable to use a gold wire.

つまり、 ベアチップ 1のパッ ド 1 aにボンディ ングワイヤ 8を接続する際に、 そこに残留したワイヤ接合部 4 aの上からワイヤボンディ ングを行って接続する これにより、 図 9に示すように、 リ一ド部 5 aとべァチップ 1のパッ ド 1 aと が素子側ワイヤ接合部 4 aを介しかつボンディ ングワイヤ 8によって電気的に接 続されて半導体装置を製造できる。  That is, when the bonding wire 8 is connected to the pad 1a of the bare chip 1, the wire bonding portion 4a remaining there is connected by performing wire bonding from above. As a result, as shown in FIG. The lead portion 5a and the pad 1a of the base chip 1 are electrically connected via the element-side wire bonding portion 4a and by the bonding wire 8, so that a semiconductor device can be manufactured.

本発明の実施の形態 3を、 図 1 0の検査用ボンディ ングワイヤとベアチップと の分離方法を示す断面図、 図 1 1の半導体装置の構造を示す断面図を用いて説明 する。  Embodiment 3 of the present invention will be described with reference to a cross-sectional view of FIG. 10 showing a method of separating a bonding wire for inspection and a bare chip, and a cross-sectional view showing the structure of a semiconductor device of FIG.

本実施の形態 3の半導体装置の製造方法は、 検査用ボンディ ングワイヤ 4のボ ンディ ングを超音波ボンディ ング以外の超音波熱圧着ボンディ ングによって行う ものである。  In the method for manufacturing a semiconductor device according to the third embodiment, the bonding of the inspection bonding wire 4 is performed by ultrasonic thermocompression bonding other than ultrasonic bonding.

つまり、 前記実施の形態 1においては、 検査用ボンディ ングワイヤ 4を接铳す る際に、 超音波ボンディ ングを行う場合を説明したが、 これに対して、 本実施の 形態 3は、 検査用ボンディ ングワイヤ 4の接続を超音波熱圧着ボンディ ングによ つて行うものである。  That is, in the first embodiment, the case where the ultrasonic bonding is performed when connecting the bonding wire for inspection 4 has been described. On the other hand, the bonding of the bonding for inspection according to the third embodiment is described. The bonding wire 4 is connected by ultrasonic thermocompression bonding.

この際、 図 1 0 ( a ) に示すように、 検査用ボンディ ングワイヤ 4にアルミ二 ゥム線ではなく、 金線もしくは銅線を用いる。  At this time, as shown in FIG. 10 (a), a gold wire or a copper wire is used for the bonding wire for inspection 4 instead of the aluminum wire.

さらに、 超音波熱圧着ボンディ ングを行う時のボンディ ング条件は、 素子支持 基板 1 0側の条件として、 例えば、 超音波パワーを装置の最大パワーの 2 5〜 4 0 %程度、 最適には 3 0 %、 荷重を 8 0〜 1 3 0 g程度、 最適には 1 2 0 g、 お よび時間を 2 5〜4 0 m s e c程度、 最適には 3 0 m s e cに設定し、 これによ り、 超音波熱圧着ボンディ ングを行う。 Further, the bonding conditions for performing the ultrasonic thermocompression bonding are as follows. For example, the ultrasonic power is set to 25 to 4 which is the maximum power of the device. Approximately 0%, optimally 30%, load approximately 80 to 130 g, optimally 120 g, and time approximately 25 to 40 msec, optimally set to 30 msec Thus, ultrasonic thermocompression bonding is performed.

また、 ベアチップ 1側の条件と して、 例えば、 超音波パワーを装置の最大パヮ 一の 2 5〜 4 0 %程度、 最適には 3 0 %、 荷重を 5 0 ~ 1 0 0 g程度、 最適には The conditions for the bare chip 1 include, for example, an ultrasonic power of about 25 to 40% of the maximum power of the apparatus, optimally about 30%, and a load of about 50 to 100 g, optimal. To

6 0 g、 および時間を 2 5〜4 0 m s e c程度、 最適には 3 0 m s e cに設定し、 これにより、 超音波熱圧着ボンディ ングを行う。 60 g and the time are set to about 25 to 40 msec, optimally to 30 msec, thereby performing ultrasonic thermocompression bonding.

さらに、 加熱温度は、 ペレツ ト温度で 2 0 0 °C程度である。  Furthermore, the heating temperature is about 200 ° C in pellet temperature.

その結果、 ベアチップ 1側の超音波パワーおよび荷重を超音波ボンディ ングの 場合より大きく したことにより、 ベアチップ 1 と検査用ボンディ ングワイヤ 4と の分離の際に、 ベアチップ 1上に素子側ワイヤ接合部 4 aを残留させることがで きる。  As a result, the ultrasonic power and load on the bare chip 1 side were made larger than those in the case of ultrasonic bonding, so that when the bare chip 1 and the bonding wire 4 for inspection were separated, the element side wire joint 4 was placed on the bare chip 1. a can be left.

すなわち、 バーンインなどの検査終了後、 ベアチップ 1 と検査用ボンディ ング ワイヤ 4とを分離する際に、 図 1 0 ( b ) に示すように、 ベアチップ 1のパッ ド 1 a上に検査用ボンディ ングワイヤ 4の突起状の素子側ワイヤ接合部 4 aを残留 させることができ、 これを半導体装置を製造する際にボール状バンプとして用い る。  That is, after the inspection such as burn-in, when the bare chip 1 and the bonding wire for inspection 4 are separated, the bonding wire for inspection 4 is placed on the pad 1a of the bare chip 1 as shown in FIG. 10 (b). The protruding element-side wire bonding portion 4a can be left, and is used as a ball-shaped bump when manufacturing a semiconductor device.

ここで、 図 1 1に示す半導体装置のように、 図 9に示す半導体装置と同様 （素 子搭載部材のタブ 5 cにベアチップ 1を搭載する半導体装置） のタイプの半導体 装置を製造する際に、 リード部 5 aとベアチップ 1のパッ ド 1 aとを接続するボ ンディ ングワイヤ 8に金線を用い、 かつベアチップ 1のパッ ド 1 aにボンディ ン グワイヤ 8を接続する時、 そこに残留した突起状の素子側ワイヤ接合部 4 aの上 からワイヤボンディ ングを行って接続する。  Here, as in the case of the semiconductor device shown in FIG. 11, when manufacturing a semiconductor device of the same type as the semiconductor device shown in FIG. 9 (a semiconductor device in which the bare chip 1 is mounted on the tab 5c of the device mounting member). When a gold wire is used as the bonding wire 8 for connecting the lead portion 5a to the pad 1a of the bare chip 1, and the bonding wire 8 is connected to the bonding wire 8 for the pad 1a of the bare chip 1, Bonding is performed by wire bonding from above the element-side wire joint 4a.

その結果、 リード部 5 aとべァチップ 1のパッ ド 1 aとが突起状のワイヤ接合 部 4 aを介しかつ金線のボンディ ングワイヤ 8によって電気的に接铳された図 1 1 に示す半導体装置を製造できる。  As a result, the semiconductor device shown in FIG. 11 in which the lead portion 5a and the pad 1a of the base chip 1 are electrically connected to each other through the protruding wire bonding portion 4a and by the bonding wire 8 of the gold wire. Can be manufactured.

本発明の実施の形態 4を、 図 1 2の半導体装置の構造を示す断面図を用いて説 明する。  Embodiment 4 of the present invention will be described with reference to a cross-sectional view showing the structure of the semiconductor device in FIG.

本実施の形態 4の半導体装置は、 ベアチップ 1のフリ ップチップ接続を行うも のであり、 前記実施の形態 3がベアチップ 1のパッ ド 1 a上に残留させた突起状 の素子側ワイヤ接合部 4 aにその上からボンディ ングワイヤ 8を接统して半導体 装置を製造したのに対して、 本実施の形態 4では、 ベアチップ 1のパッ ド 1 a上 に残留させた突起状のワイヤ接合部 4 aを用いてベアチップ 1のフリ ップチップ 接铳を行うものである。 In the semiconductor device of the fourth embodiment, the bare chip 1 is flip-chip connected. In the third embodiment, a semiconductor device is manufactured by connecting a bonding wire 8 from above to the protruding element-side wire bonding portion 4a left on the pad 1a of the bare chip 1. On the other hand, in the fourth embodiment, the flip chip connection of the bare chip 1 is performed using the protruding wire bonding portion 4 a left on the pad 1 a of the bare chip 1.

すなわち、 ベアチップ 1のパッ ド 1 a上に残留した突起状のワイヤ接合部 4 a をバンプ電極として用い、 プリ ン ト基板などの実装基板 1 7のリー ド部 i 7 aに 素子側ワイヤ接合部 4 aを介してベアチップ 1 をフリ ップチップ実装するもので ある。  That is, the projecting wire bonding portion 4a remaining on the pad 1a of the bare chip 1 is used as a bump electrode, and the element side wire bonding portion is connected to the lead portion i7a of the mounting substrate 17 such as a printed board. The bare chip 1 is flip-chip mounted via 4a.

なお、 図 9、 図 1 1および図 1 2に示した半導体装置を製造する際に、 これに 用いるベアチッブ 1の取得方法におけるその他の取得条件は、 前記実施の形態 1 の半導体装置の製造方法において説明した K G Dの所得方法と同様である。 本発明の実施の形態 5を、 図 1 3のベアチップキヤ リアの構造を示す断面図、 図 1 4の検査用ボンディ ングワイヤとベアチップとの接合伏態を示す拡大部分断 面図、 図 1 5の検査用ボンディ ングワイヤとベアチップとの分雜方法を示す断面 図を用いて説明する。  When manufacturing the semiconductor device shown in FIG. 9, FIG. 11 and FIG. 12, other acquisition conditions in the method of obtaining the bare chip 1 used for this It is similar to the KGD income method described. FIG. 13 is a cross-sectional view showing the structure of the bare chip carrier in FIG. 13; FIG. 14 is an enlarged partial cross-sectional view showing the bonding state between the bonding wire for inspection and the bare chip in FIG. This will be described with reference to a cross-sectional view illustrating a method of separating the bonding wire for inspection and the bare chip.

本実施の形態 5のべァチッブキャ リア 1 8は、 前記実施の形態 1のべァチップ キャ リア 1 8に対して、 上部蓋部材 1 5と下部蓋部材 1 2の形伏を変えたもので あり、 ベアチップキャリア 1 8の内部の気密性を向上させたものである。  The base carrier 18 of the fifth embodiment differs from the base chip carrier 18 of the first embodiment in that the upper lid member 15 and the lower lid member 12 have different shapes. The airtightness inside the bare chip carrier 18 is improved.

ここで、 本実施の形態 5のべァチップキャ リア 1 8の素子支持基板 1 0には、 貫通孔 1 0 dの周囲のチップ支持部 1 0 aとしてザグリである凹部 1 0 hが形成 され、 この凹部 1 0 hの表面に絶緣シート 1 4 aを介してべァチップ 1が搭載さ れる。  Here, in the element supporting substrate 10 of the bay chip carrier 18 of the fifth embodiment, a recessed portion 10h which is a counterbore is formed as a chip supporting portion 10a around the through hole 10d. The bay chip 1 is mounted on the surface of the recess 10h via the insulation sheet 14a.

さらに、 上部蓋部材 1 5と下部蓋部材 1 2とには、 それぞれ凸部 1 5 a、 1 2 aとが設けられている。  Further, the upper lid member 15 and the lower lid member 12 are provided with convex portions 15a and 12a, respectively.

また、 ベアチップ 1の裏面は、 絶縁シート 1 4 bを介して下部蓋部材 1 2の凸 部 1 2 aにより支持される。  In addition, the back surface of the bare chip 1 is supported by the convex portion 12a of the lower lid member 12 via the insulating sheet 14b.

つまり、 ベアチップ 1の回路形成面 1 bと非回路形成面 1 cとの両面に絶縁シ ート 1 4 a . 1 4 bを配置させ、 この状態のベアチップ 1を素子支持基板 1 0の チップ支持部 1 0 aと下部蓋部材 1 2の凸部 1 2 aとによって挟持している。 これにより、 ベアチップ 1はその回路形成面 1 bと非回路形成面 1 cの両面に おいて絶縁シート 1 4 a , bによって保護されている。 That is, the insulating sheets 14a and 14b are arranged on both the circuit forming surface 1b and the non-circuit forming surface 1c of the bare chip 1, and the bare chip 1 in this state is It is sandwiched between the chip supporting portion 10a and the convex portion 12a of the lower lid member 12. Thus, the bare chip 1 is protected by the insulating sheets 14a and 14b on both sides of the circuit forming surface 1b and the non-circuit forming surface 1c.

さらに、 素子支持基板 1 0の接続端子面 1 0 f には、 絶縁シート 1 4 cが配置 され、 上部蓋部材 1 5の凸部 1 5 aがこの接続端子面 1 0 f に配置された絶緣シ ート 1 4 cと密着している。  Further, an insulating sheet 14c is disposed on the connection terminal surface 10f of the element supporting substrate 10, and a projection 15a of the upper lid member 15 is provided on the connection terminal surface 10f. It is in close contact with sheet 14c.

これにより、 ベアチップキャリア 1 8の内部の気密性を高めている。  Thereby, the airtightness inside the bare chip carrier 18 is enhanced.

なお、 本実施の形態 5のベアチップキャリア 1 8の素子支持基板 1 0、 上部蓋 部材 1 5、 下部蓋部材 1 2および絶縁シー卜 1 4 a， 1 4 c (主に接続端子面 1 0 f と凹部 1 0 hに配置されるもの） は、 比較的柔らかく変形し易い、 例えば、 フッ素系樹脂 （P T F E ) によって形成されるものである。  In addition, the element supporting substrate 10 of the bare chip carrier 18 of the fifth embodiment, the upper lid member 15, the lower lid member 12, and the insulating sheets 14 a and 14 c (mainly the connection terminal surface 10 f And the recess 10h) are relatively soft and easily deformed, for example, formed of a fluorine-based resin (PTFE).

また、 前記絶縁シ一ト 1 4 bは、 前記フッ素系樹脂よりも硬いポリィ ミ ド系樹 脂シー卜により形成される。  Further, the insulating sheet 14b is formed of a polyimide resin sheet that is harder than the fluorine resin.

また、 素子支持基板 1 0にはその両面にピン部材 1 3が圧入などによって埋め 込まれて設けられており、 上部蓋部材 1 5および下部蓋部材 1 2の取り付けが、 このピン部材 1 3との嵌合によって行われ、 これにより、 ベアチップキャリア 1 8を組み立てることができるとともに、 各々を分離させてベアチップ 1を取り出 した後、 再組み立て可能なものである。  The element support substrate 10 is provided with pin members 13 embedded on both sides thereof by press-fitting or the like, and the upper cover member 15 and the lower cover member 12 are attached to the pin members 13. This allows the bare chip carrier 18 to be assembled, and allows the bare chips 1 to be separated and taken out, and then reassembled.

ここで、 本実施の形態 5における上部蓋部材 1 5と下部蓋部材 1 2のそれぞれ のピン部材 1 3との嵌合部 1 5 b . 1 2 bにはスナップリング 1 0 iが設けられ ている。  Here, a snap ring 10 i is provided at the fitting portion 15 b. 12 b of the upper lid member 15 and the lower lid member 12 in the fifth embodiment where the pin member 13 is fitted. I have.

つまり、 上部蓋部材 1 5または下部蓋部材 1 2を素子支持基板 1 0に取り付け る際には、 それぞれに設けられたスナップリング 1 0 i とピン部材 1 3とをそれ ぞれの嵌合部 1 5 b . 1 2 bにおいて嵌合させ、 これにより、 上部蓋部材 1 5を 素子支持基板 1 0に、 または、 下部蓋部材 1 2を素子支持基板〗 0に着脱自在に 取り付けることが可能になる。  In other words, when attaching the upper lid member 15 or the lower lid member 12 to the element supporting substrate 10, the snap ring 10 i and the pin member 13 provided respectively are fitted to the respective fitting portions. 1 2b, so that the upper lid member 15 can be detachably attached to the element support substrate 10 or the lower lid member 12 can be detachably attached to the element support substrate〗 0. Become.

なお、 スナップリング 1 0 iとピン部材 1 3とにおいては、 スナップリング 1 0 iの内周部がピン部材 1 3の外周部を適度な力 （両者が容易に動かない程度の 力） によって締めつける関係にあることは言うまでもない。 続いて、 図 1 4に示すように、 検査用ボンディ ングワイヤ 4を用いて素子支持 基板 1 0とベアチップ 1 とを電気的に接铙する。 In the snap ring 10 i and the pin member 13, the inner peripheral portion of the snap ring 10 i tightens the outer peripheral portion of the pin member 13 with an appropriate force (a force that does not allow the two to easily move). It goes without saying that they are in a relationship. Subsequently, as shown in FIG. 14, the element supporting substrate 10 and the bare chip 1 are electrically connected using the bonding wires 4 for inspection.

ここで、 本実施の形態 5における検査用ボンディ ングワイヤ 4の接合方法は、 前記実施の形態 1で説明した検査用ボンディ ングワイヤ 4の接合方法と同様のも のである。  Here, the bonding method of the bonding wire for inspection 4 in the fifth embodiment is the same as the bonding method of the bonding wire for inspection 4 described in the first embodiment.

すなわち、 検査用ボンディ ングワイヤ 4によってベアチップ 1のパッ ド 1 aと 素子支持基板 1 0のリー ド 1 0 cとを電気的に接铳する際に、 検査用ボンディ ン グワイヤ 4にアルミニウム線を用い、 かつ超音波ボンディ ングによって両者を接 続する。  That is, when the pad 1a of the bare chip 1 and the lead 10c of the element supporting substrate 10 are electrically connected by the bonding wire 4 for inspection, an aluminum wire is used for the bonding wire 4 for inspection. The two are connected by ultrasonic bonding.

また、 本実施の形態 5においても、 実施の形態 1 と同様に、 検査終了後にベア チップ 1 と検査用ボンディ ングワイヤ 4 とを剥離して分離する際に、 ベアチップ 1のパッ ド 1 a上に検査用ボンディ ングワイヤ 4の素子側ワイヤ接合部 4 aが残 留しないように分離する。  Also, in the fifth embodiment, as in the first embodiment, when the bare chip 1 and the bonding wire for inspection 4 are separated and separated after the inspection, the inspection is performed on the pad 1a of the bare chip 1. Separate so that the element-side wire joint 4a of the bonding wire 4 for use does not remain.

すなわち、 実施の形態 1で説明したボンディ ング条件 （素子側ワイヤ接合部 4 aを残留させないで容易に剝離する条件） と同様のボンディ ング条件によって超 音波ボンディ ングを行う。  That is, the ultrasonic bonding is performed under the same bonding conditions as those described in the first embodiment (the conditions for easily separating the element-side wire bonding portion 4a without leaving it).

その結果、 ベアチッブ 1のパッ ド 1 aと素子支持基板 1 0のリード 1 0 cとは、 検査用ボンディ ングワイヤ 4によって電気的に接続されるとともに、 検査用ボン デイ ングワイヤ 4 とベアチップ 1 とは、 ベアチップ 1のパッ ド 1 aで素子側ワイ ャ接合部 4 aが形成されて接铳されている。  As a result, the pad 1a of the bare chip 1 and the lead 10c of the element supporting board 10 are electrically connected by the bonding wire 4 for inspection, and the bonding wire 4 for inspection and the bare chip 1 are An element-side wire bonding portion 4a is formed and connected to the pad 1a of the bare chip 1.

その後、 バーンイン検査を行い、 ベアチップ 1を選別する。  After that, a burn-in inspection is performed and the bare chip 1 is selected.

続いて、 素子支持基板 1 0から上部蓋部材 1 5と下部蓋部材 1 2 とを取り外し、 吸着コレッ ト 1 6を用いてベアチップ 1を分離させる。  Subsequently, the upper lid member 15 and the lower lid member 12 are removed from the element supporting substrate 10, and the bare chip 1 is separated using the suction collet 16.

なお、 本実施の形態 5における検査用ボンディ ングワイヤ 4 とベアチップ 1の 分離方法についても、 前記実施の形態 1で説明した分離方法と同様のものである。 つまり、 図 1 5に示すように、 ベアチップ 1の非回路形成面 1 cを吸着コレツ ト 1 6によって吸引して両者を分離させる。  The method of separating the bonding wire for inspection 4 and the bare chip 1 in the fifth embodiment is the same as the separation method described in the first embodiment. That is, as shown in FIG. 15, the non-circuit forming surface 1c of the bare chip 1 is sucked by the suction collet 16 to separate them.

この際、 検査用ボンディ ングワイヤ 4が引っ張られた時、 素子側ワイヤ接合部 4 aとパッ ド 1 aとの接合強度が弱いため、 素子側ワイヤ接合部 4 aをパッ ド 1 a上に残留させずに剝離できる。 At this time, when the bonding wire 4 for inspection is pulled, the bonding strength between the element-side wire joint 4a and the pad 1a is weak, so the element-side wire joint 4a is connected to the pad 1 Can be separated without remaining on a.

なお、 ベアチップ 1を吸着コレツ 卜 1 6によって吸引する際、 素子支持基板 1 0のリード 1 0 cにおける検査用ボンディ ングワイヤ 4の接合箇所 4 cを上方か ら押さえ付けてベアチップ 1の非回路形成面 1 cを吸引することが好ましい。 すなわち、 検査用ボンディ ングワイヤ 4の接合箇所 4 cである基板側ワイヤ接 合部 4 dを上方から押さえ付けて固定しておく ことにより、 検査用ボンディ ング ワイヤ 4をベアチップ 1から確実に剝離させることができる。  When the bare chip 1 is sucked by the suction collet 16, the bonding portion 4 c of the bonding wire 4 for inspection on the lead 10 c of the element supporting substrate 10 is pressed down from above and the non-circuit forming surface of the bare chip 1 is pressed. Preferably, 1 c is aspirated. That is, the bonding wire 4 for inspection is securely separated from the bare chip 1 by pressing down and fixing the board-side wire connection portion 4 d which is the bonding portion 4 c of the bonding wire 4 for inspection from above. Can be.

本発明の実施の形態 6を、 図 1 6のボンディ ング方法を示す部分断面図、 図 1 7のボンディ ングゥエツジの構造を示す部分正面図を用いて説明する。  Embodiment 6 of the present invention will be described with reference to a partial sectional view showing a bonding method shown in FIG. 16 and a partial front view showing a structure of a bonding edge shown in FIG.

ここで、 本実施の形態 6は、 前記実施の形態 5におけるボンディ ング条件を具 体的に説明したものであるが、 前記ボンディ ング条件は、 実施の形態 1で説明し たボンディ ング条件と同様のものである。  Here, the sixth embodiment specifically describes the bonding conditions in the fifth embodiment, and the bonding conditions are the same as the bonding conditions described in the first embodiment. belongs to.

すなわち、 検査用ボンディ ングワイヤ 4とベアチップ 1のパッ ド 1 aとの接続 強度を検査用ボンディ ングワイヤ 4と素子支持基板 1 0のリード 1 0 cとの接続 強度より小さくするボンディ ング条件であり、 これらを図 1 6および図 1 7に示 すボンディ ングゥヱッジ 1 9を用いて実施の形態 1 と同様に、 超音波ボンディ ン グによって行うものである。  In other words, the bonding conditions are such that the connection strength between the bonding wire 4 for inspection and the pad 1a of the bare chip 1 is smaller than the connection strength between the bonding wire 4 for inspection and the lead 10c of the element supporting board 10. This is performed by ultrasonic bonding in the same manner as in the first embodiment using a bonding wedge 19 shown in FIGS. 16 and 17.

なお、 検査用ボンディ ングワイヤ 4によってベアチップ 1のパッ ド 1 aと素子 支持基板 1 0のリード 1 0 cとを電気的に接続する際に、 前記実施の形態 1の場 合と同様に、 素子支持基板 1 0のリード 1 0 cと検査用ボンディ ングワイヤ 4 と を接続した後、 ベアチップ 1のパッ ド 1 aと検査用ボンディ ングワイヤ 4 とを接 饥 o。  When the pad 1a of the bare chip 1 and the lead 10c of the element supporting substrate 10 are electrically connected to each other by the bonding wire 4 for inspection, the element support is carried out in the same manner as in the first embodiment. After connecting the lead 10c of the substrate 10 and the bonding wire 4 for inspection, the pad 1a of the bare chip 1 is connected to the bonding wire 4 for inspection.

つまり、 超音波ボンディ ング装置のボンディ ングゥエッジ 1 9によってワイヤ ボンディ ングを行う際に、 図 1 6に示すように、 まず、 素子支持基板 1 0のリー ド 1 0 cと検査用ボンディ ングワイヤ 4とを接铳し、 その後、 素子支持基板 1 0 の貫通孔 1 0 dに検査用ボンディ ングワイヤ 4を通して検査用ボンディ ングワイ ャ 4とベアチップ 1のパッ ド 1 aとを接続する。  In other words, when performing wire bonding with the bonding edge 19 of the ultrasonic bonding apparatus, first, as shown in FIG. 16, the lead 10c of the element supporting substrate 10 and the bonding wire 4 for inspection are connected. Then, the bonding wire 4 for inspection is connected to the pad 1 a of the bare chip 1 through the bonding wire 4 for inspection through the through hole 10 d of the element supporting substrate 10.

これは、 ワイヤが最初の圧着後にワイヤループを形成し、 この圧着部がワイヤ によって引っ張られて剝離する場合があるため、 素子支持基板 1 0側を最初にボ ンディ ングするものである。 This is because the wire forms a wire loop after the first crimping, and the crimped portion may be pulled apart by the wire and may be separated. It is a thing to do.

さらに、 ピックテールは、 最初にボンディ ングした方に形成されるため、 ベア チップ 1側を後からボンディ ングすることにより、 ベアチップ 1のパッ ド 1 a上 に前記ピックテールが形成されることを防止できる。  Furthermore, since the pick tail is formed on the side where the bonding is performed first, bonding the bare chip 1 side later prevents the pick tail from being formed on the pad 1 a of the bare chip 1. it can.

また、 図 1 6および図 1 7に示すように、 圧着部長さ 2 5〜 6 0 m、 圧着部 幅 7 0〜 1 1 0〃mのボンディ ングゥヱッジ 1 9で、 かつその先端部の形状が平 端なもの （図 1 7参照） を用いることにより、 前記圧着部に対して均一な荷重を 掛けることができる。  As shown in Fig. 16 and Fig. 17, a bonding wedge 19 with a crimping part length of 25 to 60 m and a crimping part width of 70 to 110 m, and the shape of the tip is flat. By using an endless material (see FIG. 17), a uniform load can be applied to the crimped portion.

これにより、 素子側ワイヤ接合部 4 aと基板側ワイヤ接合部 4 dとにおける接 合を安定させることができる。  This makes it possible to stabilize the bonding between the element-side wire bonding portion 4a and the substrate-side wire bonding portion 4d.

本発明の実施の形態 7を、 図 1 8のベアチップの構造を示す拡大部分平面図、 図 1 9および図 2 0のベアチップとボンディ ングワイヤとの接合伏態を示す拡大 部分平面図および拡大部分平面図を用いて説明する。  FIG. 18 is an enlarged partial plan view showing the structure of the bare chip shown in FIG. 18; FIG. 19 is an enlarged partial plan view showing the joint state between the bare chip and the bonding wire shown in FIG. 20; This will be described with reference to the drawings.

本実施の形態 7は、 バーンィン検査後に、 ベアチップキャリア 1 8 (図 1 3参 照） から取り出したベアチップ 1の使用方法を説明したものである。  In the seventh embodiment, a method of using the bare chip 1 taken out of the bare chip carrier 18 (see FIG. 13) after the burn-in inspection is described.

図 1 4に示す素子側ワイヤ接合部 4 aをベアチップ 1のパッ ド 1 a上に残留さ せない条件によってボンディ ングを行い、 かつバーンィン検査によって良品とし て得られた K G Dにおいては、 アルミニウム線の検査用ボンディ ングワイヤ 4の 剝離後、 図 1 8に示すように、 ベアチップ 1のパッ ド 1 a上に圧痕 4 bが形成さ れる。  In the KGD obtained by bonding under the condition that the element-side wire joint 4a shown in Fig. 14 does not remain on the pad 1a of the bare chip 1, and obtained as a non-defective product by burn-in inspection, the aluminum wire After the bonding wire 4 for inspection is separated, an indentation 4b is formed on the pad 1a of the bare chip 1, as shown in FIG.

その後、 このベアチップ 1 は半導体装置に搭載されるか、 あるいは図 1 8に示 すようなベアチップ 1の状態でチップ単体として出荷することも可能である。 なお、 前記半導体装置に搭載する場合、 素子搭載部材にベアチップ 1を搭載し た後 （ペレツ 卜付けした後） 、 例えば、 図 1 9に示すように、 金線のボンディ ン グワイヤ 8を用いる際には、 パッ ド 1 a上の圧痕 4 bの上に金線ボール 8 aを形 成し、 これに金線のボンディ ングワイヤ 8を用いてワイヤボンディ ングを行って 半導体装置を製造する。  Thereafter, the bare chip 1 can be mounted on a semiconductor device, or can be shipped as a single chip in a state of the bare chip 1 as shown in FIG. In the case of mounting on the semiconductor device, after mounting the bare chip 1 on the element mounting member (after attaching the pellet), for example, as shown in FIG. 19, when the bonding wire 8 of a gold wire is used. A semiconductor device is manufactured by forming a gold wire ball 8a on an impression 4b on a pad 1a and performing wire bonding on the gold ball 8a using a bonding wire 8 of a gold wire.

また、 前記同様、 素子搭載部材にベアチップ 1を搭載した後、 例えば、 図 2 0 に示すように、 アルミニゥム線のボンディ ングワイヤ 8を用いる場合、 パッ ド 1 a上の圧痕 4 の上にアルミニゥム線のボンディ ングワイヤ 8を圧着して半導体 装置を製造する。 Similarly to the above, after the bare chip 1 is mounted on the element mounting member, for example, as shown in FIG. 20, when the bonding wire 8 of an aluminum wire is used, the pad 1 a Bonding wire 8 of aluminum wire is crimped onto the indentation 4 on a to manufacture a semiconductor device.

本発明の実施の形態 8を、 図 2 1、 図 2 2および図 2 3の検査用ボンディ ング ワイヤとベアチップとの分離方法を示す断面図、 図 2 4、 図 2 5および図 2 6の 検査用ボンディ ングワイヤと素子支持基板との分離方法を示す断面図を用いて説 明する。  Embodiment 8 of the present invention will be described with reference to FIGS. 21, 22 and 23, which are sectional views showing a method of separating the bonding wire for inspection and the bare chip, and the inspections shown in FIGS. 24, 25 and 26. This will be described with reference to a cross-sectional view illustrating a method of separating a bonding wire for use from an element supporting substrate.

本実施の形態 8は、 実施の形態 5で説明したベアチップキヤ リア 1 8を用いて バーンイン検査を行った後の素子支持基板 1 0からのベアチップ 1の分離方法 （ ベアチップ 1の取り出し方法） を示すものであり、 素子支持基板 1 0からべァチ ップ 1を分離させる際に、 拈着テープ 2 0を用いるものである。  Embodiment 8 shows a method of separating the bare chip 1 from the element supporting substrate 10 (the method of taking out the bare chip 1) after performing the burn-in inspection using the bare chip carrier 18 described in Embodiment 5. When the tape 1 is separated from the element supporting substrate 10, a tape 20 is used.

なお、 本実施の形態 8では、 素子支持基板 1 0からベアチップ 1を分離させる 際に、 専用の自動剝離装置を用いて分離させる場合を説明する。  In the eighth embodiment, a case where the bare chip 1 is separated from the element supporting substrate 10 by using a dedicated automatic separation device will be described.

すなわち、 前記自動剝離装 Sは、 バーンイン検査を終え、 かつ検査用ボンディ ングワイヤ 4によって素子支持基板 1 0と接続されたベアチップ 1を検査用ボン デイ ングワイヤ 4から分離させるものである。  That is, the automatic mounting / dismounting unit S completes the burn-in inspection and separates the bare chip 1 connected to the element supporting substrate 10 by the inspection bonding wire 4 from the inspection bonding wire 4.

前記自動剝雜装置の構成は、 検査用ボンディ ングワイヤ 4によってベアチップ 1のパッ ド 1 aと電気的に接铳された素子支持基板 1 0を保持するステージ 2 1 と、 ベアチップ 1を保持しかっこのベアチップ 1を真空吸着して素子支持基板 1 0から離れる方向に移動させるチッブ保持手段である吸着コレッ ト 1 6と、 粘着 テープ 2 0を巻き取るローラ 2 5と、 刹離時に粘着テープ 2 0を押圧するテープ 押さえ 2 6と、 剝雜時に検査用ボンディ ングワイヤ 4を押圧するワイヤ押圧板 2 7とからなり、 ベアチップ 1を素子支持基板 1 0から離れる方向に移動させて検 査用ボンディ ングワイヤ 4 とベアチップ 1 とを分離するものである。  The configuration of the automatic communication device includes a stage 21 for holding an element supporting substrate 10 electrically connected to the pad 1a of the bare chip 1 by the bonding wire 4 for inspection, and a bare chip for holding the bare chip 1 Suction collet 16 which is a chip holding means for moving vacuum suction of element 1 away from element support substrate 10, roller 25 for winding adhesive tape 20, and pressing adhesive tape 20 when separated It consists of a tape retainer 26 that performs the inspection and a wire pressing plate 27 that presses the bonding wire 4 for inspection when the vehicle is in operation. The bare chip 1 is moved in a direction away from the element supporting board 10 to bond the inspection bonding wire 4 and the bare chip 1 is separated.

ここで、 本実施の形態 8で用いる粘着テープ 2 0は、 片方の面にのみ粘着性を 有したものであり、 例えば、 ダイシング工程などで使用しているダイシングテー プ （U Vテープともいう） などであるが、 前記ダイシングテープに限定されるも のではなく、 半導体装置の製造工程において半導体基板や半導体素子 （ベアチッ プ 1 ) などに悪影響を及ぼさないものであれば他のテープ部材であってもよい。 本実施の形態 8による素子支持基板 1 0からのべァチップ 1の取り出し方法に ついて説明する。 Here, the adhesive tape 20 used in the eighth embodiment has adhesiveness on only one side, such as a dicing tape (also referred to as a UV tape) used in a dicing step or the like. However, the tape is not limited to the dicing tape, and other tape members may be used as long as they do not adversely affect the semiconductor substrate and the semiconductor element (Bear Chip 1) in the semiconductor device manufacturing process. Good. The method for taking out the base chip 1 from the element supporting substrate 10 according to the eighth embodiment explain about.

まず、 バーンィン検査を終えた図 1 3に示すベアチッブキヤリア 1 8において、 下部蓋部材 1 2 と上部蓋部材 1 5とを素子支持基板 1 0から取り外す。  First, in the bare carrier 18 shown in FIG. 13 after the burn-in inspection, the lower lid member 12 and the upper lid member 15 are removed from the element supporting substrate 10.

つまり、 下部蓋部材 1 2と素子支持基板 1 0と上部蓋部材 1 5 とを分離させる c その後、 図 1 に示すように、 素子支持基板 1 0の裏面側 1 0 g (ベアチップ 1を支持している側） を上方に向け、 かつ前記自動剝雜装置のステージ 2 1上に 位置決めを行って素子支持基板 1 0を搭載する。 That is, the lower lid member 12, the element supporting substrate 10, and the upper lid member 15 are separated from each other.c Then, as shown in FIG. 1, 10 g of the back side of the element supporting substrate 10 (the bare chip 1 is supported). The device supporting substrate 10 is mounted with its side facing upwards and positioned on the stage 21 of the automatic communication device.

これにより、 ステージ 2 1の下方に配置された粘着テープ 2 0の粘着面 2 0 a と素子支持基板 1 0の接続端子面 1 0 ίとが対向して配置されている。  Thus, the adhesive surface 20a of the adhesive tape 20 disposed below the stage 21 and the connection terminal surface 10 # of the element supporting substrate 10 are disposed to face each other.

その後、 ベアチップ 1の上方からその非回路形成面 1 cに向けて吸着コレツ ト 1 6を下降させるとともに、 ステージ 2 1の下部においてテープ押さえ 2 6を上 昇させる。  Thereafter, the suction collet 16 is lowered from above the bare chip 1 toward the non-circuit forming surface 1c, and the tape retainer 26 is raised below the stage 21.

铳いて、 図 2 1 . 図 2 2に示すように、 テープ押さえ 2 6によって粘着テープ 2 0を押圧し、 これにより、 基板側ワイヤ接合部 4 d付近に粘着テープ 2 0を押 し当てかつ粘着テープ 2 0を素子支持基板 1 0の接続端子面 1 0 ίに貼付して基 板側ワイヤ接合部 4 dを固定する。  Then, as shown in Fig. 21. As shown in Fig. 22, the adhesive tape 20 is pressed by the tape retainer 26, thereby pressing the adhesive tape 20 near the board side wire joint 4 d and adhering it. Affix the tape 20 to the connection terminal surface 10 の of the element supporting substrate 10 to fix the substrate side wire bonding portion 4 d.

つまり、 粘着テープ 2 0を素子支持基板 1 0の接統端子面 1 0 f の貫通孔 1 0 dの周辺付近に貼付し、 これにより、 検査用ボンディ ングワイヤ 4の基板側ワイ ャ接合部 4 d付近を粘着テープ 2 0によって固定する。  That is, the adhesive tape 20 is adhered to the vicinity of the periphery of the through hole 10 d of the connection terminal surface 10 f of the element supporting substrate 10, thereby forming the bonding wire 4 d on the substrate side of the bonding wire 4 for inspection. The area is fixed with adhesive tape 20.

さらに、 吸着コレッ ト 1 6によってベアチップ 1の非回路形成面 1 cを真空吸 着し、 ベアチッブ 1を保持する。  Furthermore, the non-circuit forming surface 1 c of the bare chip 1 is vacuum-adsorbed by the suction collet 16, and the bare chip 1 is held.

その後、 図 2 3に示すように、 ベアチップ 1を吸着コレッ ト 1 6によって保持 し、 この伏態で吸着コレツ ト 1 6を素子支持基板 1 0の上方すなわち素子支持基 板 1 0から離れる方向に移動させてベアチップ 1 と検査用ボンディ ングワイヤ 4 とを分雜する。  Thereafter, as shown in FIG. 23, the bare chip 1 is held by the suction collet 16, and in this state, the suction collet 16 is held above the element supporting substrate 10, that is, in a direction away from the element supporting substrate 10. By moving it, the bare chip 1 and the bonding wire for inspection 4 are separated.

この際、 ベアチップ 1のパッ ド 1 a上に素子側ワイヤ接合部 4 aを残留させな いボンディ ング条件によって検査用ボンディ ングワイヤ 4 とベアチップ 1 とをボ ンディ ングしてあれば、 パッ ド 1 a上に素子側ワイヤ接合部 4 aが残留すること はない。 また、 素子側ワイヤ接合部 4 aを残留させるボンディ ング条件によって検査用 ボンディ ングワイヤ 4 とベアチップ 1 とをボンディ ングしてあれば、 ハ°ッ ド 1 a 上に素子側ワイヤ接合部 4 aが残留する。 At this time, if the bonding wire 4 for inspection and the bare chip 1 are bonded under bonding conditions that do not leave the element-side wire joint 4a on the pad 1a of the bare chip 1, the pad 1a The element-side wire joint 4a does not remain on the upper side. In addition, if the bonding wire for inspection 4 and the bare chip 1 are bonded according to the bonding conditions that leave the wire bonding portion 4a on the element side, the wire bonding portion 4a on the element side remains on the head 1a. I do.

その後、 取り出したベアチップ 1を吸着コレツ ト 1 6によって保持して移送し. 図示しないチップ収容部 （例えば、 卜レイ） に収容する。  Thereafter, the picked-up bare chip 1 is held and transported by the suction collet 16 and stored in a chip storage section (not shown) (for example, tray).

続いて、 図 2 4に示すように、 ワイャ押圧板 2 7を素子支持基板 1 0の上方か らその貫通孔 1 0 dに向けて下降させ、 ワイヤ押圧板 2 7によって検査用ボンデ ィ ングワイヤ 4を粘着テープ 2 0に対して押さえ付ける。  Subsequently, as shown in FIG. 24, the wire pressing plate 27 is lowered from above the element supporting substrate 10 toward the through hole 10 d, and the inspection bonding wire 4 is moved by the wire pressing plate 27. To the adhesive tape 20.

これにより、 検査用ボンディ ングワイヤ 4は粘着テープ 2 0に貼付される。 さらに、 図 2 5に示すように、 検査用ボンディ ングワイヤ 4がワイヤ押圧板 2 7によって粘着テープ 2 0に貼付された状態を維持して （ワイヤ押圧板 2 7とテ —プ押さえ 2 6とによって検査用ボンディ ングワイヤ 4と粘着テープ 2 0とを挟 んだ状態で） 、 テープ押さえ 2 6を下降すなわち素子支持基板 1 0から離れる方 向に移動させる。  As a result, the bonding wire for inspection 4 is attached to the adhesive tape 20. Further, as shown in FIG. 25, the state in which the bonding wire for inspection 4 is adhered to the adhesive tape 20 by the wire pressing plate 27 is maintained (by the wire pressing plate 27 and the tape retainer 26). While holding the bonding wire for inspection 4 and the adhesive tape 20), the tape retainer 26 is moved downward, that is, moved in a direction away from the element supporting substrate 10.

これにより、 粘着テープ 2 0に検査用ボンディ ングワイヤ 4を付着させて検査 用ボンディ ングワイヤ 4と素子支持基板 1 0とを分離でき、 かつ粘着テープ 2 0 を素子支持基板 1 0から離脱させることができる。  Thereby, the bonding wire 4 for inspection can be attached to the adhesive tape 20 to separate the bonding wire 4 for inspection from the element supporting substrate 10, and the adhesive tape 20 can be detached from the element supporting substrate 10. .

その後、 ワイヤ押圧板 2 7を上昇すなわち素子支持基板 1 0から離れる方向に 移動させる。  Thereafter, the wire pressing plate 27 is lifted, that is, moved in a direction away from the element supporting substrate 10.

さらに、 図 2 6に示すように、 テープ押さえ 2 6を下降させ、 これを粘着テー プ 2 0から離して粘着テープ 2 0を可動自在な伏態とし、 ローラ 2 5を所定の一 方向に回転させて粘着テープ 2 0を巻き取る。  Further, as shown in FIG. 26, the tape retainer 26 is lowered, separated from the adhesive tape 20 to make the adhesive tape 20 movable freely, and the roller 25 is rotated in one predetermined direction. Then take up the adhesive tape 20.

その結果、 使用済みとなった検査用ボンディ ングワイヤ 4を粘着テープ 2 0上 に付着させたまま飛散させることなく回収できる。  As a result, the used inspection bonding wire 4 can be collected without being scattered while being adhered to the adhesive tape 20.

ここで、 ローラ 2 5によって所定量の粘着テープ 2 0を巻き取ったことにより、 素子支持基板 1 0の貫通孔 1 0 d付近の下方には、 粘着テープ 2 0の未使用の粘 着面 2 0 aを配置させることができる。  Here, since a predetermined amount of the adhesive tape 20 is wound by the roller 25, the unused adhesive surface 2 of the adhesive tape 20 is located below the vicinity of the through hole 10d of the element supporting substrate 10. 0a can be arranged.

これにより、 検査用ボンディ ングワイヤ 4を粘着テープ 2 0に付着させて素子 支持基板 1 0と検査用ボンディ ングワイヤ 4とベアチップ 1 とを分離することが できる。 As a result, the bonding wire 4 for inspection is attached to the adhesive tape 20 to separate the element supporting substrate 10, the bonding wire 4 for inspection, and the bare chip 1. it can.

本実施の形態 8によって得られる作用効果について説明する。  The operation and effect obtained by the eighth embodiment will be described.

バーンィン検査の終了後、 ベアチップ 1 と検査用ボンディ ングワイヤ 4とを分 離する際に、 基板側ワイヤ接合部 4 d付近を固定して分離することにより、 素子 側ワイヤ接合部 4 aもしくはその近傍においてべァチップ 1 と検査用ボンディ ン グワイヤ 4 とを分離することができる。  After the burn-in inspection, when separating the bare chip 1 from the bonding wire 4 for inspection, by fixing and separating the vicinity of the board-side wire joint 4 d, the element-side wire joint 4 a or the vicinity thereof is fixed. The base chip 1 and the bonding wire 4 for inspection can be separated.

なお、 検査用ボンディ ングワイヤ 4の基板側ワイヤ接合部 4 d付近の固定の際 に、 粘着テープ 2 0を用いることにより、 容易に固定することができ、 かつ確実 にベアチップ 1 と検査用ボンディ ングワイヤ 4 とを分離することができる。 さらに、 粘着テープ 2 0を用いることにより、 自動剝雜装置の構造も容易な構 造のものとすることができる。  When the bonding wire 4 for inspection is fixed in the vicinity of the wire bonding portion 4 d on the substrate side, it can be easily fixed by using the adhesive tape 20, and the bare chip 1 and the bonding wire 4 for inspection can be securely fixed. And can be separated. Furthermore, the use of the adhesive tape 20 allows the automatic communication device to have a simple structure.

また、 粘着テープ 2 0を用いて検査用ボンディ ングワイヤ 4を剝離させること により、 ベアチップ 1 と検査用ボンディ ングワイヤ 4 とを分離した後、 粘着テー プ 2 0を素子支持基板 1 0から脱離させた際に、 粘着テープ 2 0に検査用ボンデ イ ングワイヤ 4を付着させることができる。  Further, by separating the bonding wire 4 for inspection using the adhesive tape 20 to separate the bare chip 1 and the bonding wire 4 for inspection, the adhesive tape 20 was detached from the element supporting substrate 10. At this time, the inspection bonding wire 4 can be attached to the adhesive tape 20.

これによつて、 粘着テープ 2 0に検査用ボンディ ングワイヤ 4を付着させて容 易にベアチッブ 1 と検査用ボンディ ングワイヤ 4と素子支持基板 1 0とを分離さ せることが可能になる。  This makes it possible to attach the bonding wire 4 for inspection to the adhesive tape 20 and easily separate the bare chip 1, the bonding wire 4 for inspection and the element supporting substrate 10.

その結果、 検査後の検査用ボンディ ングワイヤ 4を飛散させることなく、 粘着 テープ 2 0によって容易に素早く回収することができる。  As a result, the bonding wire 4 for inspection after the inspection can be easily and quickly collected by the adhesive tape 20 without scattering.

さらに、 粘着テープ 2 0に検査用ボンディ ングワイヤ 4を付着させて素子支持 基板 1 0と検査用ボンディ ングワイヤ 4 とを分離させることにより、 素子支持基 板 1 0のリー ド 1 0 cに検査用ボンディ ングワイヤ 4の基板側ワイヤ接合部 4 d を残留させずに検査用ボンディ ングワイヤ 4全てを剝がす （除去する） ことがで きる。  Further, the bonding wire 4 for inspection is attached to the adhesive tape 20 to separate the element supporting substrate 10 and the bonding wire 4 for inspection, so that the bonding bond 10 for inspection is attached to the lead 10 c of the element supporting substrate 10. The entire inspection bonding wire 4 can be removed (removed) without leaving the substrate-side wire joint 4 d of the bonding wire 4.

これにより、 素子支持基板 1 0のリード 1 0 cが損傷しにくいため、 素子支持 基板 1. 0を複数回繰り返して使用することができ、 これにより、 ベアチップキヤ リア 1 8 も再生キヤ リアとして緣り返して使用することが可能になる。  As a result, since the leads 10c of the element supporting substrate 10 are hardly damaged, the element supporting substrate 1.0 can be used multiple times, whereby the bare chip carrier 18 can also be used as a reproducing carrier. It can be used again.

本発明の実施の形態 9を、 図 2 7および図 2 8の半導体装置の製造手順を示す 断面図、 図 2 9の半導体装置の構造を示す断面図を用いて説明する。 The ninth embodiment of the present invention shows a manufacturing procedure of the semiconductor device of FIGS. 27 and 28. This will be described with reference to a cross-sectional view and a cross-sectional view showing the structure of the semiconductor device in FIG.

ここで、 本実施の形態 9で説明する半導体装置は、 バーンイン検査の桔果から 取得した良品のベアチップ 1を搭載した L 0 C構造のものである。  Here, the semiconductor device described in the ninth embodiment has an L0C structure in which a good bare chip 1 obtained from the result of burn-in inspection is mounted.

前記半導体装置の構成は、 検査用ボンディ ングワイヤ 4にアルミニウム線を用 いてバーンィン検査を行った結果から良品として選別されたべァチップ 1の回路 形成面 1 bとリー ドフレーム 5 (図 2 7参照） などの素子搭載部材のリ一ド部 5 aとが対向して配置されるとともに、 ベアチップ 1のパッ ド 1 aとリ一 ド部 5 a とが金からなるボンディ ングワイヤ 8によって霪気的に接铳されかつべァチップ 1 とボンディ ングワイヤ 8とが封止樹脂 7によって封止されている。  The configuration of the semiconductor device includes a circuit forming surface 1b and a lead frame 5 (see FIG. 27) of the base chip 1, which is selected as a non-defective product based on a result of performing a burn-in test using an aluminum wire as the test bonding wire 4. The lead portion 5a of the element mounting member is disposed so as to face the pad, and the pad 1a of the bare chip 1 and the lead portion 5a are connected with each other by a bonding wire 8 made of gold. The base chip 1 and the bonding wire 8 are sealed with a sealing resin 7.

ここで、 本実施の形態 9による前記 L O C構造の半導体装置の製造方法につい て説明する。  Here, a method of manufacturing the semiconductor device having the LOC structure according to the ninth embodiment will be described.

まず、 図 1 3に示す検査用ボンディ ングワイヤ 4にアルミニゥム線を用いてバ ーンィ ン検査を行った結果から良品として選別されたべァチップ 1を準備する。 続いて、 図 2 7に示すように、 ベアチップ 1の回路形成面 1 bと、 リードフレ ーム 5のリ一 ド部 5 aとを対向させるとともに、 ポリイ ミ ドなどからなる絶縁性 テープ 9を介してベアチップ 1をリー ド部 5 aに搭載する。  First, a bare chip 1 that is selected as a non-defective product based on the result of a burn-in inspection using an aluminum wire as the inspection bonding wire 4 shown in FIG. 13 is prepared. Subsequently, as shown in FIG. 27, the circuit forming surface 1 b of the bare chip 1 and the lead portion 5 a of the lead frame 5 are opposed to each other, and an insulating tape 9 made of polyimide or the like is interposed therebetween. The bare chip 1 is mounted on the lead section 5a.

その後、 ベアチッブ 1のパッ ド 1 aとリー ド部 5 aとを金からなるボンディ ン グワイヤ 8によって電気的に接铳する。  Thereafter, the pad 1a of the bare chip 1 and the lead portion 5a are electrically connected by a bonding wire 8 made of gold.

さらに、 図 2 8に示すように、 ベアチップ 1 とボンディ ングワイヤ 8とを封止 樹脂 7によって封止して前記 L O C構造の半導体装置を製造する。  Further, as shown in FIG. 28, the bare chip 1 and the bonding wire 8 are sealed with a sealing resin 7 to manufacture the semiconductor device having the LOC structure.

ここで、 樹脂封止を行う際には、 ボンディ ングを終了したベアチップ 1搭載済 みのリードフレーム 5を図示しないモールド金型内に搬入し、 例えば、 トランス ファーモールドによって樹脂封止を行う。  Here, when performing resin sealing, the lead frame 5 on which the bonded bare chip 1 has been mounted is loaded into a mold (not shown), and resin sealing is performed by, for example, transfer molding.

その後、 リードフレーム 5における図示しないダム部を切断し、 はんだメ ツキ 処理、 さらに、 マーク付けを行う。  After that, a dam portion (not shown) of the lead frame 5 is cut, and a solder plating process is performed, and a mark is formed.

铳いて、 図示しない成形金型によってァウタリー ド 5 bを形成し、 図 2 9に示 す L O Cを製造できる。  Then, the outer lead 5b is formed by a molding die (not shown), and the LOC shown in FIG. 29 can be manufactured.

なお、 本実施の形態 9による半導体装置は、 ベアチップ 1で予め選別およびェ 一ジングを行っているため、 ァウタリード 5 bの成形後の選別およびエージング は不要となり、 組み立て後、 直ぐに出荷させることができる。 In the semiconductor device according to the ninth embodiment, sorting and aging are performed in advance on the bare chip 1, so that sorting and aging after forming the outer leads 5b are performed. Is no longer required and can be shipped immediately after assembly.

本発明の実施の形態 1 0を、 図 3 0の半導体装置の製造手順を示す部分断面図- 図 3 1 の半導体装置の構造を示す部分断面図を用いて説明する。  Embodiment 10 of the present invention will be described with reference to a partial cross-sectional view showing a procedure for manufacturing the semiconductor device in FIG. 30-a partial cross-sectional view showing the structure of the semiconductor device in FIG. 31.

ここで、 本実施の形態 1 0で説明する半導体装置は、 バーンイン検査の桔果か ら取得した良品のベアチップ 1を直接実装基板 1 7に搭載した C 0 B ( Ch i p On Here, the semiconductor device described in the present embodiment 10 has a structure in which a good bare chip 1 obtained from the result of burn-in inspection is directly mounted on a mounting board 17.

Board)構造である。 Board) structure.

前記半導体装臛の榱成は、 図 3 1 に示すように、 検査用ボンディ ングワイヤ 4 (図 1 3参照） にアルミニウム線を用いてバーンイ ン検査を行った結果から良品 として選別されたベアチップ 1が実装基板 1 7に実装されるとともに、 ベアチッ プ 1のパッ ド 1 aと実装基板 1 7の電極であるリード部 1 7 aとが金からなるボ ンディ ングワイヤ 8によつて電気的に接続され、 かつベアチップ 1 とボンディ ン グワイヤ 8とが封止樹脂 7によって封止されている。  As shown in FIG. 31, the bare chip 1 which was selected as a non-defective product from the result of burn-in inspection using an aluminum wire for the inspection bonding wire 4 (see FIG. 13) was performed as shown in FIG. While being mounted on the mounting board 17, the pad 1 a of the bare chip 1 and the lead portion 17 a which is an electrode of the mounting board 17 are electrically connected by bonding wires 8 made of gold, Further, the bare chip 1 and the bonding wire 8 are sealed with a sealing resin 7.

ここで、 本実施の形態 1 0による前記 C O Bの製造方法について説明する。 まず、 図 1 3に示す検査用ボンディ ングワイヤ 4にアルミニウム線を用いてバ —ンィ ン検査を行った結果から良品と して選別されたべァチップ 1を準備する。 続いて、 図 3 0に示すように、 ベアチップ 1を A gペース 卜または絶縁性接着 剤などを用いて実装基板 1 7に搭載する。  Here, a method of manufacturing the COB according to the tenth embodiment will be described. First, a bare chip 1 that is selected as a non-defective product based on the result of a burn-in inspection performed using an aluminum wire as the inspection bonding wire 4 shown in FIG. 13 is prepared. Subsequently, as shown in FIG. 30, the bare chip 1 is mounted on the mounting board 17 using an Ag paste or an insulating adhesive.

その後、 ベアチップ 1のパッ ド 1 aと実装基板 1 7のリー ド部 1 7 aとを金か らなるボンディ ングワイヤ 8によって霜気的に接続する。  After that, the pad 1a of the bare chip 1 and the lead portion 17a of the mounting board 17 are connected in a frosty manner by bonding wires 8 made of gold.

さらに、 図 3 1 に示すように、 ベアチップ 1 とボンディ ングワイヤ 8とを封止 樹脂 7によって封止して前記 C 0 B構造の半導体装置を製造する。  Further, as shown in FIG. 31, the bare chip 1 and the bonding wire 8 are sealed with a sealing resin 7 to manufacture the semiconductor device having the C0B structure.

ここで、 本実施の形態 1 0による樹脂封止は、 例えば、 ポッティ ングなどによ つて行い、 硬化させる。  Here, the resin sealing according to the tenth embodiment is performed by, for example, potting or the like, and is cured.

なお、 本実施の形態 1 0による半導体装置 （C O B ) は、 ベアチップ 1で予め 選別およびエージングを行っているため、 実装基板 1 7への搭載後の不良をなく すことができ、 その拮果、 C O Bの歩留りを向上させることができる。  In the semiconductor device (COB) according to the tenth embodiment, since sorting and aging are performed in advance with the bare chip 1, defects after mounting on the mounting board 17 can be eliminated. COB yield can be improved.

本発明の実施の形態 1 1 を、 図 3 2の素子支持基板の構造を示す平面図、 図 3 3の素子支持基板の構造を示す拡大平面図を用いて説明する。  Embodiment 11 of the present invention will be described with reference to a plan view showing the structure of the element support substrate in FIG. 32 and an enlarged plan view showing the structure of the element support substrate in FIG.

本実施の形態 1 1 は、 実施の形態 1で説明した素子支持基板 1 0に対してその 構造を変えたものである。 The present embodiment 11 is different from the element supporting substrate 10 described in the first embodiment. It has a different structure.

すなわち、 図 3 2に示す素子支持基板 1 0は、 中央付近に形成された貫通孔 1 0 dの長手方向周辺の一方にのみリード 1 0 cが設けられており、 検査用ボンデ ィ ングワイヤ 4がー方向にのみ取り出されるようになつている。  That is, in the element supporting substrate 10 shown in FIG. 32, the lead 10c is provided only on one side of the longitudinal direction periphery of the through hole 10d formed near the center, and the inspection bonding wire 4 is provided. -It can be taken out only in the direction.

これにより、 力一ドエツジコネクタ 1 0 bが貫通孔 I 0 dの片側端部のみに設 けられている。  Thus, the force edge connector 10b is provided only at one end of the through hole I 0d.

また、 素子支持基板 1 0のリー ド 1 0 cは、 素子支持基板 1 0を再利用したと きにボンディ ング位置を移動させることを考慮し、 検査用ボンディ ングワイヤ 4 が他の検査用ボンディ ングワイヤ 4と接触することなどを防止するため、 例えば、 図 3 3に示すように、 リード 1 0 cを匱くエリアの外側の線 （A ) へベアチップ 1のパッ ド 1 aの位置から直線を引き （a〜a ' ) 、 その直線上にリー ド 1 0 c が配置され、 リード 1 0 cのボンディ ングェリアは、 検査用ボンディ ングワイヤ 4の延在方向と同一方向に長く形成されている。  In addition, considering that the bonding position is moved when the element supporting substrate 10 is reused, the bonding wire 4 for the inspection is used as the bonding wire 10c for the inspection. For example, as shown in Fig. 33, a straight line is drawn from the position of pad 1a of bare chip 1 to the line (A) outside (A-a '), the lead 10c is arranged on the straight line, and the bonding area of the lead 10c is formed to be long in the same direction as the extending direction of the bonding wire 4 for inspection.

ここで、 素子支持基板 1 0の外部との接続においては、 図 3 2に示すように、 素子支持基板 1 0の一端部がカー ドエッジコネクタ 1 0 bとされ、 このカードエ ッジコネクタ 1 0 bを通じてバーンィンボード 3 (図 7参照） に搭載された一般 的なカー ドエッジ型のソケッ ト 1 1 (図 7参照） に、 ベアチップキャ リア 1 8 ( 図 1 3参照） が垂直状態で挿し込まれるようになつている。 なお、 この挿入に際 しては、 逆挿しを防止するためにカードエツジコネクタ 1 0 bが配置される側の 一方に凸部 2 2が設けられている。  Here, in connection with the outside of the element supporting board 10, as shown in FIG. 32, one end of the element supporting board 10 is used as a card edge connector 10 b, and through the card edge connector 10 b. The bare chip carrier 18 (see Fig. 13) is inserted vertically into the general card-edge socket 11 (see Fig. 7) mounted on the burn-in board 3 (see Fig. 7). It has become. In this insertion, a convex portion 22 is provided on one of the sides where the card edge connector 10b is arranged in order to prevent reverse insertion.

また、 この素子支持基板 1 0において、 カードエッジコネクタ 1 0 bが配置さ れていない両端部には切り欠き 2 3と開孔 2 4とが設けられており、 この切り欠 き 2 3および開孔 2 4に嵌合される治具などを用いてベアチップキヤ リア 1 8を バーンィンボー ド 3上のソケッ ト 1 1から容易に抜き取ることが可能となってい る。  Further, in the element supporting board 10, a notch 23 and an opening 24 are provided at both ends where the card edge connector 10 b is not disposed, and the notch 23 and the opening 24 are provided. The bare chip carrier 18 can be easily removed from the socket 11 on the burn-in board 3 by using a jig or the like fitted into the hole 24.

以上、 本発明者によってなされた発明を発明の実施の形態 1 ~ 1 1に基づき具 体的に説明したが、 本発明は前記実施の形態に限定されるものではなく、 その要 旨を逸脱しない範囲で種々変更可能であることは言うまでもない。  As described above, the invention made by the inventor has been specifically described based on Embodiments 1 to 11 of the invention. However, the invention is not limited to the embodiment and does not depart from the gist of the invention. It goes without saying that various changes can be made within the range.

例えば、 実施の形態 1〜 1 1 における素子支持基板 1 0はプリ ン ト配線基板で あるが、 素子支持基板 1 0は、 これに限らず、 ベアチップ 1を支持しかつバーン ィ ンボード 3と電気的に接続するカードエツジコネクタ 1 0 bなどの外部接铳端 子を有していれば、 箱形などの他の形状のものであってもよい。 For example, the element supporting substrate 10 in the first to eleventh embodiments is a printed wiring board. However, the element support substrate 10 is not limited to this, and may have an external connection terminal such as a card edge connector 10 b that supports the bare chip 1 and electrically connects to the burn-in board 3. It may have another shape such as a box shape.

さらに、 実施の形態 1〜 1 1 においては、 下部蓋部材 1 2と上部蓋部材 1 5と によって、 ベアチップ 1 と検査用ボンディ ングワイヤ 4との周囲を密閉した雰囲 気でバーンイン検査を行う場合について説明したが、 下部蓋部材 1 2および上部 蓋部材 1 5は必ずしも用いるものではなく、 ベアチップ 1 と検査用ボンディ ング ワイヤ 4とを露出させた伏態で検査を行ってもよい。  Further, in the first to eleventh embodiments, the burn-in inspection is performed in an atmosphere in which the periphery of the bare chip 1 and the bonding wire 4 for inspection is sealed by the lower lid member 12 and the upper lid member 15. As described above, the lower lid member 12 and the upper lid member 15 are not necessarily used, and the inspection may be performed in a state where the bare chip 1 and the bonding wire for inspection 4 are exposed.

また、 実施の形態 1〜 1 1 においては、 素子支持基板 1 0のリー ド 1 0 cと検 査用ボンディ ングワイヤ 4 とを接続した後、 ベアチップ 1のパッ ド 1 aと検査用 ボンディ ングワイヤ 4 とを接铳する場合について説明したが、 ボンディ ングの順 序は、 これに限定されるものではなく、 ベアチップ 1のパッ ド 1 aと検査用ボン ディ ングワイヤ 4とを接続した後、 素子支持基板 1 0のパッ ド 1 aと検査用ボン デイ ングワイヤ 4とを接続してもよい。  In the first to eleventh embodiments, after the lead 10 c of the element supporting substrate 10 is connected to the bonding wire 4 for inspection, the pad 1 a of the bare chip 1 is connected to the bonding wire 4 for inspection. However, the order of bonding is not limited to this. After connecting the pad 1a of the bare chip 1 and the bonding wire 4 for inspection, the bonding order of the element supporting board 1 is determined. The pad 1 a of No. 0 may be connected to the bonding wire 4 for inspection.

なお、 実施の形態 1〜 1 1においては、 吸着コレッ ト 1 6によってベアチヅプ 1 を吸引して検査用ボンディ ングワイヤ 4とベアチップ 1 とを分離させる場合に ついて説明したが、 検査用ボンディ ングワイヤ 4 とべァチップ 1 との分離につい ては、 フック部材などを検査用ボンディ ングワイヤ 4に引っかけ、 かつそれを引 つ張って分離させてもよく、 あるいは、 カッター部材などを用いて検査用ボンデ イ ングワイヤ 4を切断してもよい。  In the first to eleventh embodiments, the description has been given of the case where the bonding chip 4 is suctioned by the suction collet 16 to separate the bonding wire 4 for inspection from the bare chip 1, but the bonding wire 4 for inspection and the bare chip 1 are described. For the separation from 1, the hook member or the like may be hooked on the inspection bonding wire 4 and pulled and separated, or the inspection bonding wire 4 may be cut using a cutter member or the like. You may.

また、 吸着コレツ ト 1 6によりベアチップ 1 と絶縁シート 1 4または絶緣シ一 ト 1 4 aとを同時に吸引し、 絶緣シート 1 4または絶緣シ一 ト 1 4 aごと素子支 持基板 1 0から分離させた後、 ベアチップ 1 と絶縁シー ト 1 4または絶縁シ一 ト 1 4 aとを分離することも可能である。  Also, the bare chip 1 and the insulating sheet 14 or the insulating sheet 14a are simultaneously sucked by the suction collet 16 and separated from the element supporting board 10 together with the insulating sheet 14 or the insulating sheet 14a. After that, the bare chip 1 and the insulating sheet 14 or the insulating sheet 14a can be separated.

さらに、 実施の形態 1〜 1 1で説明した検査用ボンディ ングワイヤ 4を用いて ベアチップ 1 とキャリア 1 0とを電気的に接続させる際の種々のボンディ ング条 件は、 これに限定されるものではなく、 検査用ボンディ ングワイヤ 4 とべァチッ プ 1 とにおいて、 あるいは、 検査用ボンディ ングワイヤ 4と素子支持基板 1 0と において所望の接続状態を满たすものであれば、 他のボンディ ング条件であって もよい。 Furthermore, various bonding conditions for electrically connecting the bare chip 1 and the carrier 10 using the inspection bonding wires 4 described in the first to eleventh embodiments are not limited thereto. If the bonding wire 4 for inspection and the bonding tape 1 or the bonding wire 4 for inspection and the element supporting board 10 can achieve a desired connection state, the other bonding conditions may be satisfied. Is also good.

また、 実施の形態 1 ~ 1 1において、 検査時の検査用ボンディ ングワイヤ 4に アルミ二ゥム線を用い、 かつ半導体装置のワイヤボンディ ングに金からなるボン ディ ングワイヤ 8を用いることにより、 検査用ボンディ ングワイヤ 4をべァチッ プ 1から分離させる際には、 ベアチップ 1のパッ ド 1 aを損傷させることなくか つ容易に分離させることができ、 さらに、 前記半導体装置においてボンディ ング ワイヤ 8の腐食などを防止することができる。  Further, in the first to eleventh embodiments, the inspection bonding wire 4 is formed by using an aluminum wire as the inspection bonding wire 4 and using the bonding wire 8 made of gold for the wire bonding of the semiconductor device. When the bonding wire 4 is separated from the base 1, the pad 1 a of the bare chip 1 can be easily separated without damaging the bonding wire 4, and the bonding wire 8 is corroded in the semiconductor device. Can be prevented.

これにより、 KGDによって良品のベアチップ 1を取得する際にも、 ベアチッ プ 1の品質を向上させることが可能になり、 さらに、 前記半導体装置の品質も向 上させることができる。  This makes it possible to improve the quality of the bare chip 1 even when a good bare chip 1 is obtained by KGD, and also to improve the quality of the semiconductor device.

その結果、 高性能および高信頼性を有する KG Dを容易に取得することが可能 になる。  As a result, it is possible to easily obtain a KGD having high performance and high reliability.

なお、 ベアチップキャ リア 1 8の構造、 形状、 材質などについては、 実施の形 態 1 ~ 1 1のような場合に限定されるものではなく、 本発明においては、 特に素 子支持基板 1 0の再利用およびワイヤボンディ ングによる接铳の組み合わせにつ いては広く適用させることができる。  The structure, shape, material, and the like of the bare chip carrier 18 are not limited to those in Embodiments 1 to 11, and in the present invention, in particular, the device support substrate 10 Combinations of reuse and wire bonding can be widely applied.

また、 実施の形態 1〜 1 1において説明したベアチップキヤ リア 1 8の構造、 検査用ボンディ ングワイヤ 4の材質とそのボンディ ング方法、 ベアチップ 1と素 子支持基板 1 0と検査用ボンディ ングワイヤ 4との分離方法、 および、 ボンディ ングワイヤ 8の材質については、 前記実施の形態 1 ~ 1 1で説明した組み合わせ に限定されるものではなく、 それぞれをどのように組み合わせても良いことは言 うまでもない。  In addition, the structure of the bare chip carrier 18 described in the first to eleventh embodiments, the material of the bonding wire 4 for inspection and the bonding method thereof, and the bonding of the bare chip 1, the element supporting substrate 10 and the bonding wire 4 for inspection. The separation method and the material of the bonding wire 8 are not limited to the combinations described in the first to eleventh embodiments, and it goes without saying that any combination may be used.

以上のようなベアチップ 1の信頼性の高い KGD技術によって、 DRAM、 S RAM、 F LASH, MCM、 PDA (携帯情報端末） 、 ハンディパソコン、 簡 易型携帯電話、 携帯電話、 モジュールなどを搭載するための容量に限界のある小 型機器などに用いて効果が期待でき、 例えばベアチップ価格およびモジュール価 格の低减による製品価格の低下、 信頼性の高いベアチップ 1が供袷できるように なることで、 ベアチップ 1を用いた実装密度の高いモジュールを構成することが でき、 これにより機器を小型、 軽置化することが可能となる。 産業上の利用可能性 With the reliable KGD technology of bare chip 1 as described above, DRAM, SRAM, FLASH, MCM, PDA (Personal Digital Assistant), Handy PC, simple mobile phone, mobile phone, module, etc. It can be expected to be effective for small equipment with limited capacity, such as lower product prices due to lower bare chip prices and module prices, and the availability of highly reliable bare chips1. A module with a high mounting density using the bare chip 1 can be configured, thereby making it possible to reduce the size and weight of the device. Industrial applicability

以上のように、 本発明の半導体装置の製造方法は、 高性能および高信頼性のべ ァチップを安価、 容易かつ安定して取得する KGD技術に好適であり、 これによ つて得られたベアチップを搭載する本発明の半導体装置は、 高信頼性かつ安価で あるとともに、 DRAM、 S RAMs F LASH、 MCM、 PDA (携帯情報端 末） 、 ハンディパソコン、 PHS、 携帯 ¾話、 モジュールなどを搭載するための 容量に限界のある小型機器などに適し、 特に積層 DRAM汎用メモリモジュール などのベアチップを用いた実装密度の高いモジュールに好適である。  As described above, the method of manufacturing a semiconductor device according to the present invention is suitable for the KGD technology for obtaining a high-performance and high-reliability base chip at low cost, easily, and stably. The semiconductor device of the present invention to be mounted is not only highly reliable and inexpensive but also includes DRAM, SRAMs FLASH, MCM, PDA (portable information terminal), handy personal computer, PHS, mobile phone, module, etc. It is suitable for small devices with limited capacity, especially for modules with a high mounting density using bare chips such as stacked DRAM general-purpose memory modules.

Claims

請 求 の 範 囲 The scope of the claims 1 . 貫通孔が形成されかっこの貫通孔の周囲の第 1主面に接続端子が設けられた 素子支持基板を準備し、 前記第 1主面と反対側の第 2主面にベアチップを配置す る工程と、 1. Prepare an element supporting substrate having a through hole formed therein and a connection terminal provided on a first main surface around the through hole, and disposing a bare chip on a second main surface opposite to the first main surface. Process, 前記素子支持基板の第 2主面側に配置させるカバー部材と前記素子支持基板と によつて前記べァチップを挟持する工程と、  Clamping the bay chip by a cover member arranged on the second main surface side of the element support substrate and the element support substrate; 前記べァチップの素子電極と前記素子支持基板の接铳端子とを前記貫通孔に通 した検査用ボンディ ングワイヤによって電気的に接続する工程と、  Electrically connecting an element electrode of the bay chip and a connection terminal of the element support substrate by a bonding wire for inspection passed through the through hole; 前記素子支持基板の接練端子と検査基板の基板電極とを電気的に接続して前記 ベアチップを検査する工程と、  Inspecting the bare chip by electrically connecting the kneading terminals of the element support substrate and the substrate electrodes of the inspection substrate; 検査後、 前記検査用ボンディ ングワイヤの基板側ワイヤ接合部付近を固定して 前記ベアチップと前記検査用ボンディ ングワイヤとを分離し、 前記ベアチップを 前記素子支持基板から取り外す工程とを含み、  After the inspection, fixing the vicinity of the substrate-side wire bonding portion of the bonding wire for inspection, separating the bare chip and the bonding wire for inspection, and removing the bare chip from the element supporting substrate. 前記検査によって良品のベアチップを選別することを特徴とする半導体装置の 製造方法。  A method for manufacturing a semiconductor device, wherein non-defective bare chips are selected by the inspection. 2 . 請求の範囲第 1項記載の半導体装置の製造方法であって、 検査後に前記ベア チップと前記検査用ボンディ ングワイヤとを分離する際、 前記ベアチップの素子 電極上に前記検査用ボンディ ングワイヤの素子側ワイヤ接合部が残留しないよう に両者を剝雜させて分離することを特徴とする半導体装置の製造方法。  2. The method for manufacturing a semiconductor device according to claim 1, wherein, when separating the bare chip and the bonding wire for inspection after inspection, an element of the bonding wire for inspection is provided on an element electrode of the bare chip. A method for manufacturing a semiconductor device, comprising enclosing and separating both such that a side wire joint does not remain. 3 . 請求の範囲第 1項記載の半導体装置の製造方法であって、 前記検査用ボンデ ィ ングワイヤと前記ベアチップの素子電極との接続強度を前記検査用ボンディ ン グワイヤと素子支持基板の接铳端子との接続強度より小さく して接続し、 検査後 に前記ベアチップと前記検査用ボンディ ングワイヤとを分離する際、 前記べァチ ップの素子電極上に前記検査用ボンディ ングワイヤの素子側ワイヤ接合部が残留 しないように両者を剝離させて分離することを特徴とする半導体装置の製造方法。  3. The method for manufacturing a semiconductor device according to claim 1, wherein a connection strength between the inspection bonding wire and an element electrode of the bare chip is determined by a connection terminal between the inspection bonding wire and an element support substrate. When the bare chip and the bonding wire for inspection are separated after the inspection, and the bare wire is separated from the bonding wire for inspection, an element-side wire bonding portion of the bonding wire for inspection is provided on the device electrode of the base. A method for manufacturing a semiconductor device, comprising separating a semiconductor device and a semiconductor device so as not to remain. 4 . 中心部に貫通孔が形成されかっこの貫通孔の周囲に接続端子が設けられた素 子支持基板のチップ支持部にベアチップを配置する工程と、 4. a step of disposing a bare chip on a chip supporting portion of a device supporting substrate in which a through hole is formed in the center and connection terminals are provided around the through hole; 前記素子支持基板のチップ支持側に配置させるカバー部材と前記素子支持基板 とによって前記ベアチップを挟持する工程と、 A cover member arranged on the chip supporting side of the element support substrate and the element support substrate Clamping the bare chip by and 前記べァチップの素子電極と前記素子支持基板の接続端子とを前記貫通孔に通 した検査用ボンディ ングワイヤによって電気的に接続する工程と、  Electrically connecting an element electrode of the bay chip and a connection terminal of the element support substrate by a bonding wire for inspection passed through the through hole; 前記素子支持基板の接続端子と検査基板の基板電極とを電気的に接続して前記 ベアチップを検査する工程と、  Inspecting the bare chip by electrically connecting a connection terminal of the element support substrate and a substrate electrode of an inspection substrate; 検査後、 前記検査用ボンディ ングワイヤの基板側ワイヤ接合部付近を固定する とともに前記ベアチップの素子電極上に前記検査用ボンディ ングワイヤの素子側 ワイヤ接合部を残留させて前記べァチップと前記検査用ボンディ ングワイヤとを 分離し、 前記べァチップを前記素子支持基板から取り外す工程とを含み、  After the inspection, the vicinity of the board-side wire bonding portion of the bonding wire for inspection is fixed, and the element-side wire bonding portion of the bonding wire for testing is left on the device electrode of the bare chip so that the bare chip and the bonding wire for testing are left. Separating the base chip from the element supporting substrate. 前記検査によって良品のベアチップを選別することを特徴とする半導体装置の 製造方法。  A method for manufacturing a semiconductor device, wherein non-defective bare chips are selected by the inspection. 5 . 請求の範囲第 1項記載の半導体装置の製造方法であって、 検査後に前記ベア チップと前記検査用ボンディ ングワイヤとを分離する際、 前記基板側ワイヤ接合 部付近に粘着テープを押し当てかつ前記粘着テープを前記素子支持基板の接铳端 子面に貼付して前記基板側ワイヤ接合部を固定した後、 前記素子支持基板から前 記べァチップを移動させて前記べァチップと前記検査用ボンディ ングワイヤとを 分雜し、 分離後、 前記粘着テープを前記素子支持基板から離脱させることにより、 板と前記検査用ボンディ ングワイヤと前記べァチップとを分離することを特徴と する半導体装置の製造方法。  5. The method for manufacturing a semiconductor device according to claim 1, wherein when separating the bare chip and the bonding wire for inspection after inspection, an adhesive tape is pressed against a vicinity of the wire bonding portion on the substrate side. After sticking the adhesive tape to the contact terminal surface of the element supporting substrate to fix the substrate-side wire bonding portion, the above-mentioned bare chip is moved from the element supporting substrate, and the bare chip and the inspection bonder are moved. A method of manufacturing a semiconductor device, comprising: separating a bonding wire from a board, the bonding wire for inspection, and the chip by separating the adhesive tape from the element supporting substrate after separating the bonding wire from the element supporting substrate. 6 . 請求の範囲第 2項記載の半導体装置の製造方法であって、 検査後に前記ベア チップと前記検査用ボンディ ングワイヤとを分離する際、 前記基板側ワイヤ接合 部付近に粘普テープを押し当てかつ前記粘着テープを前記素子支持基板の接铳端 子面に貼付して前記基板側ワイヤ接合部を固定した後、 前記素子支持基板から前 記べァチップを移動させて前記べァチップと前記検査用ボンディ ングワイヤとを 分雜し、 分離後、 前記粘着テープを前記素子支持基板から離脱させることにより、 板と前記検査用ボンディ ングワイヤと前記べァチップとを分離することを特徴と する半導体装置の製造方法。 6. The method for manufacturing a semiconductor device according to claim 2, wherein when separating the bare chip and the bonding wire for inspection after inspection, a sticky tape is pressed against the vicinity of the wire bonding portion on the substrate side. Further, after the adhesive tape is attached to the contact terminal surface of the element support substrate to fix the substrate-side wire bonding portion, the bay chip is moved from the element support substrate, and the base chip and the inspection chip are moved. A method of manufacturing a semiconductor device, comprising: separating a bonding wire from a bonding wire for inspection by separating the bonding tape from the element supporting substrate after separating and bonding the bonding wire from the element supporting substrate. . 7 . 請求の範囲第 4項記載の半導体装置の製造方法であって、 検査後に前記ベア チップと前記検査用ボンディ ングワイヤとを分離する際、 前記基板側ワイヤ接合 部付近に粘着テープを押し当てかつ前記粘着テープを前記素子支持基板の接続端 子面に貼付して前記基板側ワイャ接合部を固定した後、 前記素子支持基板から前 記べァチップを移動させて前記べァチップと前記検査用ボンディ ングワイヤとを 分雜し、 分離後、 前記粘着テープを前記素子支持基板から雜脱させることにより、 前記検査用ボンディ ングワイヤを前記粘着テープに付着させて前記素子支持基板 と前記検査用ボンデイ ングワイヤと前記ベアチップとを分離することを特徴とす る半導体装置の製造方法。 7. The method for manufacturing a semiconductor device according to claim 4, wherein the substrate-side wire bonding is performed when the bare chip and the inspection bonding wire are separated after inspection. After pressing the adhesive tape near the portion and attaching the adhesive tape to the connection terminal surface of the element support substrate to fix the substrate-side wire bonding portion, the above-mentioned bay chip is moved from the element support substrate. The bay chip and the bonding wire for inspection are separated, and after separation, the adhesive tape is unbonded from the element supporting substrate, so that the bonding wire for inspection is attached to the adhesive tape and the element supporting substrate is separated. And separating the inspection bonding wire and the bare chip from each other. 8 . 請求の範囲第 1項記載の半導体装置の製造方法であって、 前記検査用ボンデ イ ングワイヤによつて前記ベアチップの素子電極と前記素子支持基板の接铳端子 とを電気的に接続する際に、 前記検査用ボンディ ングワイヤにアルミニウム線を 用い、 かつ超音波ボンディ ングによって両者を接続することを特徴とする半導体 装置の製造方法。  8. The method for manufacturing a semiconductor device according to claim 1, wherein the element electrodes of the bare chip and the connection terminals of the element support board are electrically connected by the bonding wires for inspection. In addition, a method of manufacturing a semiconductor device, wherein an aluminum wire is used as the bonding wire for inspection, and the both are connected by ultrasonic bonding. 9 . 請求の範囲第 2項記載の半導体装贋の製造方法であって、 前記検査用ボンデ ィ ングワイヤによって前記べァチップの素子電極と前記素子支持基板の接続端子 とを電気的に接続する際に、 前記検査用ボンディ ングワイヤにアルミニウム線を 用い、 かつ超音波ボンディ ングによって両者を接铳することを特徴とする半導体 装置の製造方法。  9. The method for manufacturing a semiconductor device according to claim 2, wherein when the device electrode of the bay chip is electrically connected to the connection terminal of the device support substrate by the bonding wire for inspection. A method for manufacturing a semiconductor device, comprising using an aluminum wire as the bonding wire for inspection, and connecting the both by ultrasonic bonding. 1 0 . 請求の範囲第 1項記載の半導体装置の製造方法であって、 前記検査用ボン ディ ングワイヤにアルミニゥム線を用いて前記検査を行った結果から良品として 選別されたベアチップの素子電極と、 前記ベアチップを搭載する素子搭載部材の リ一 ド部または実装基板のリード部とを金からなるボンディ ングワイヤによって 電気的に接続して半導体装置を製造することを特徴とする半導体装置の製造方法。 10. The method for manufacturing a semiconductor device according to claim 1, wherein a bare chip element electrode selected as a non-defective product from a result of performing the inspection using an aluminum wire as the bonding wire for inspection, A method for manufacturing a semiconductor device, comprising: manufacturing a semiconductor device by electrically connecting a lead portion of an element mounting member on which the bare chip is mounted or a lead portion of a mounting substrate with a bonding wire made of gold. 1 1 . 請求の範囲第 2項記載の半導体装置の製造方法であって、 前記検査用ボン ディ ングワイヤにアルミニウム線を用いて前記検査を行った結果から良品として 選別されたベアチップの素子電極と、 前記ベアチップを搭載する素子搭載部材の リ一ド部または実装基板のリ一ド部とを金からなるボンディ ングワイヤによって 電気的に接続して半導体装置を製造することを特徴とする半導体装置の製造方法。11. The method for manufacturing a semiconductor device according to claim 2, wherein a bare chip element electrode selected as a non-defective product from a result of the inspection performed using an aluminum wire as the inspection bonding wire, Manufacturing a semiconductor device by electrically connecting a lead portion of an element mounting member on which the bare chip is mounted or a lead portion of a mounting substrate with a bonding wire made of gold. . 1 2 . 躋求の範囲第 1項記載の半導体装置の製造方法であって、 前記検査用ボン ディ ングワイヤにアルミニウム線を用いて前記検査を行った結果から良品として 選別されたべァチップの回路形成面と、 素子搭載部材のリ一ド部とを対向させて 前記ベアチップを前記リ一ド部に搭載した後、 前記ベアチップの素子電極と前記 リ一ド部とを金からなるボンディ ングワイヤによって電気的に接铳し、 前記ベア チップと前記ボンディ ングワイヤとを封止樹脂によって封止して半導体装置を製 造することを特徵とする半導体装置の製造方法。 12. The method of manufacturing a semiconductor device according to item 1, wherein the inspection is performed using an aluminum wire as the bonding wire for inspection, and the result is obtained as a non-defective product. The bare chip is mounted on the lead portion with the circuit forming surface of the selected base chip and the lead portion of the device mounting member facing each other, and then the device electrode of the bare chip and the lead portion are gold-plated. A method for manufacturing a semiconductor device, comprising: electrically contacting with a bonding wire formed of a semiconductor chip; and sealing the bare chip and the bonding wire with a sealing resin to manufacture a semiconductor device. 1 3 . 請求の範囲第 2項記載の半導体装置の製造方法であって、 前記検査用ボン ディ ングワイヤにアルミニゥム線を用いて前記検査を行った結果から良品として 選別されたベアチップの回路形成面と、 素子搭載部材のリー ド部とを対向させて 前記ベアチップを前記リ一ド部に搭載した後、 前記ベアチップの素子電極と前記 リ一ド部とを金からなるボンディ ングワイヤによって霪気的に接統し、 前記ベア チップと前記ボンディ ングワイヤとを封止樹脂によって封止して半導体装置を製 造することを特徴とする半導体装置の製造方法。  13. The method for manufacturing a semiconductor device according to claim 2, wherein a circuit forming surface of a bare chip selected as a non-defective product from a result of the inspection performed using an aluminum wire as the inspection bonding wire. After the bare chip is mounted on the lead part with the lead part of the element mounting member facing the element part, the element electrode of the bare chip and the lead part are in air contact with each other by a bonding wire made of gold. And manufacturing the semiconductor device by sealing the bare chip and the bonding wire with a sealing resin. 1 4 . 請求の範囲第 1項記載の半導体装置の製造方法であって、 前記検査用ボン ディ ングワイヤにアルミニウム線を用いて前記検査を行った結果から良品として 選別されたベアチップを実装基板に搭載し、 前記ベアチップの素子電極と前記実 装基板のリ一ド部とを金からなるボンディ ングワイヤによって電気的に接続した 後、 前記ベアチップと前記ボンディ ングワイヤとを封止樹脂によって封止して半 導体装置を製造することを特徴とする半導体装置の製造方法。  14. The method for manufacturing a semiconductor device according to claim 1, wherein a bare chip selected as a non-defective product from a result of the inspection performed using an aluminum wire as the bonding wire for inspection is mounted on a mounting board. After electrically connecting the element electrodes of the bare chip and the lead portions of the mounting substrate with bonding wires made of gold, the bare chip and the bonding wires are sealed with a sealing resin to obtain a semiconductor. A method for manufacturing a semiconductor device, comprising manufacturing the device. 1 5 . 請求の範囲第 2項記載の半導体装置の製造方法であって、 前記検査用ボン デイ ングワイヤにアルミニゥム線を用いて前記検査を行った結果から良品として 選別されたベアチップを実装基板に搭載し、 前記ベアチップの素子電極と前記実 装基板のリ一ド部とを金からなるボンディ ングワイヤによって電気的に接続した 後、 前記ベアチップと前記ボンディ ングワイヤとを封止樹脂によって封止して半 導体装置を製造することを特徴とする半導体装 Sの製造方法。  15. The method for manufacturing a semiconductor device according to claim 2, wherein a bare chip selected as a non-defective product from a result of performing the inspection using an aluminum wire as the bonding wire for inspection is mounted on a mounting board. After electrically connecting the element electrodes of the bare chip and the lead portions of the mounting substrate with bonding wires made of gold, the bare chip and the bonding wires are sealed with a sealing resin to obtain a semiconductor. A method for manufacturing a semiconductor device S, comprising manufacturing a device. 1 6 . 請求の IS囲第 1項記載の半導体装置の製造方法であって、 前記検査用ボン ディ ングワイヤによって前記べァチップの素子霉極と前記素子支持基板の接続端 子とを電気的に接続する際に、 前記素子支持基板の接続端子と前記検査用ボンデ ィ ングワイヤとを接続した後、 前記ベアチップの素子電極と前記検査用ボンディ ングワイヤとを接続することを特徴とする半導体装置の製造方法。 16. The method for manufacturing a semiconductor device according to claim 1, wherein the element bonding electrode of the bay chip is electrically connected to a connection terminal of the element supporting board by the bonding wire for inspection. A method of manufacturing a semiconductor device, comprising: connecting a connection terminal of the element support substrate to the bonding wire for inspection, and then connecting the element electrode of the bare chip and the bonding wire for inspection. 1 7 . 請求の範囲第 2項記載の半導体装置の製造方法であって、 前記検査用ボン ディ ングワイヤによって前記べァチップの素子電極と前記素子支持基板の接続端 子とを電気的に接铳する際に、 前記素子支持基板の接铳端子と前記検査用ボンデ ィ ングワイヤとを接続した後、 前記ベアチップの素子電極と前記検査用ボンディ ングワイヤとを接続することを特徴とする半導体装置の製造方法。 17. The method for manufacturing a semiconductor device according to claim 2, wherein an element electrode of the bay chip is electrically connected to a connection terminal of the element support substrate by the bonding wire for inspection. At this time, a method for manufacturing a semiconductor device, comprising: connecting a contact terminal of the element supporting substrate to the bonding wire for inspection, and then connecting the element electrode of the bare chip to the bonding wire for inspection. 1 8 . 請求の範囲第 1項記載の半導体装置の製造方法であって、 検査後、 前記べ ァチップと前記検査用ボンディ ングワイヤとを分離する際に、 前記ベアチップの 素子電極が形成された回路形成面と反対側の非回路形成面を吸引して両者を分離 することを特徴とする半導体装置の製造方法。  18. The method for manufacturing a semiconductor device according to claim 1, wherein, after the inspection, when separating the bare chip and the bonding wire for inspection, a circuit forming device element of the bare chip is formed. A method for manufacturing a semiconductor device, wherein a non-circuit forming surface opposite to a surface is suctioned to separate them. 1 9 . 請求の範囲第 2項記載の半導体装置の製造方法であって、 検査後、 前記べ ァチップと前記検査用ボンディ ングワイヤとを分離する際に、 前記ベアチップの 素子霍極が形成された回路形成面と反対側の非回路形成面を吸引して両者を分離 することを特徴とする半導体装置の製造方法。  19. The method for manufacturing a semiconductor device according to claim 2, wherein the bare chip and the bonding wire for inspection are separated from each other after the inspection, and wherein the element of the bare chip is formed. A method of manufacturing a semiconductor device, wherein a non-circuit forming surface opposite to a forming surface is suctioned to separate them. 2 0 . 予め電気的な検査を行って良品として選別されたベアチップを搭載した半 導体装置であって、 前記検査時に用いる素子支持基板の貫通孔に通した検査用ボ ンデイ ングワイヤによつて前記ベアチップと前記素子支持基板とを接続して前記 検査を行った後、 前記検査用ボンディ ングワイヤの基板側ワイヤ接合部付近を固 定して前記ベアチップと前記検査用ボンディ ングワイヤとを分離して取得した 1 つまたは複数のベアチップが搭載され、 前記べァチップの素子電極上に前記検査 用ボンディ ングワイヤの素子側ワイヤ接合部を残留させずに前記ベアチップと前 記検査用ボンディ ングワイヤとを分離した際には、 素子搭載部材のリー ド部また は実装基板のリ一ド部と前記素子電極とが霍気的に接続され、 前記べァチップの 素子電極上に前記素子側ワイヤ接合部を残留させて前記べァチッブと前記検査用 ボンディ ングワイヤとを分離した際には、 前記素子側ワイヤ接合部を介して前記 リ一ド部と前記素子電極とが電気的に接続されていることを特徽とする半導体装 歡。  20. A semiconductor device on which a bare chip that has been subjected to an electrical inspection in advance and that has been selected as a non-defective product is mounted. After performing the inspection by connecting the device bonding substrate and the element supporting substrate, the vicinity of the substrate-side wire bonding portion of the bonding wire for inspection was fixed, and the bare chip and the bonding wire for inspection were separated and obtained. When one or more bare chips are mounted, and the bare chip and the bonding wire for inspection are separated without leaving the element-side wire bonding portion of the bonding wire for inspection on the device electrode of the bay chip, The lead portion of the element mounting member or the lead portion of the mounting board and the device electrode are connected in a fluid manner, and the device electrode of the base chip is connected. When the element and the bonding wire for inspection are separated with the element-side wire joint remaining on the upper side, the lead portion and the element electrode are electrically connected via the element-side wire joint. Semiconductor equipment that is specially connected to the Internet. 2 に 請求の範囲第 2 0項記載の半導体装置であって、 前記検査用ボンディ ング ワイヤにアルミニウム線を用いて前記検査を行った結果から良品として選別され たべァチップの素子電極と、 前記べァチッブを搭載する素子搭載部材のリ一ド部 または実装基板のリ一ド部とが金からなるボンディ ングワイヤによって霍気的に 接続されていることを特徴とする半導体装置。 22. The semiconductor device according to claim 20, wherein the element electrodes of a base chip selected as non-defective products based on the result of the inspection performed using an aluminum wire as the inspection bonding wire; and Of the element mounting member for mounting Alternatively, the semiconductor device is characterized in that the lead portion of the mounting board is electrically connected to a bonding wire made of gold. 2 2 . 請求の範囲第 2 0項記載の半導体装置であって、 前記検査用ボンディ ング ワイヤにアルミ二ゥム線を用いて前記検査を行った結果から良品として選別され たべァチップの回路形成面と素子搭載部材のリ一ド部とが対向して配置されると ともに、 前記べァチップの素子電極と前記リ一ド部とが金からなるボンディ ング ワイヤによって鸳気的に接続されかつ前記べァチップと前記ボンディ ングワイヤ とが封止樹脂によって封止されていることを特徵とする半導体装置。  22. The semiconductor device according to claim 20, wherein a circuit-forming surface of a bay chip selected as a non-defective product based on a result of performing the inspection using an aluminum wire as the bonding wire for inspection. And the lead portion of the element mounting member are arranged to face each other, and the element electrode of the base chip and the lead portion are electrically connected to each other by a bonding wire made of gold, and A semiconductor device, characterized in that a chip and a bonding wire are sealed with a sealing resin. 2 3 . 請求の範囲第 2 0項記載の半導体装置であって、 前記検査用ボンディ ング ワイヤにアルミニゥム線を用いて前記検査を行った結果から良品として選別され たベアチップが実装基板に実装されるとともに、 前記ベアチップの素子罨極と前 記実装基板のリ一ド部とが金からなるボンディ ングワイヤによって電気的に接続 され、 かつ前記ベアチップと前記ボンディ ングワイヤとが封止樹脂によって封止 されていることを特徴とする半導体装置。 23. The semiconductor device according to claim 20, wherein a bare chip selected as a non-defective product from a result of performing the inspection using an aluminum wire as the bonding wire for inspection is mounted on a mounting board. In addition, the element compressing electrode of the bare chip and the lead portion of the mounting board are electrically connected by a bonding wire made of gold, and the bare chip and the bonding wire are sealed with a sealing resin. A semiconductor device characterized by the above-mentioned.
PCT/JP1997/000095 1996-09-18 1997-01-20 Process for producing semiconductor device and semiconductor device Ceased WO1998012568A1 (en)

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