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WO1998011660A1 - Circuit d'alimentation basse tension - Google Patents

Circuit d'alimentation basse tension Download PDF

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Publication number
WO1998011660A1
WO1998011660A1 PCT/US1996/014712 US9614712W WO9811660A1 WO 1998011660 A1 WO1998011660 A1 WO 1998011660A1 US 9614712 W US9614712 W US 9614712W WO 9811660 A1 WO9811660 A1 WO 9811660A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
node
low voltage
circuit
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1996/014712
Other languages
English (en)
Inventor
Ray-Lin Wan
Chun-Hsiung Hung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Macronix International Co Ltd
Original Assignee
Macronix International Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Macronix International Co Ltd filed Critical Macronix International Co Ltd
Priority to PCT/US1996/014712 priority Critical patent/WO1998011660A1/fr
Priority to US08/849,676 priority patent/US5877616A/en
Publication of WO1998011660A1 publication Critical patent/WO1998011660A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only

Definitions

  • the present invention relates to the generation of an internal supply voltage on integrated circuits; and more particularly to internal supply voltages having a lower potential than power supply potentials provided to the integrated circuit, and which consume very little stand-by power.
  • a circuit that supplies a supply voltage in an integrated circuit must be capable of sustaining substantial on demand current, in order to maintain the voltage potential at its output under varying load conditions.
  • Prior art designs for generating internal supply voltages of this type therefore have been relatively high power consumers.
  • Dix, et al. patent cited above a low voltage supply circuit is described which is used for the so-called source inhibit function in a flash memory integrated circuit having the architecture described in Dix, et al.
  • the supply circuits of Dix, et al. operate to provide a relatively stable internal supply voltage, they suffer the disadvantage that they consume substantial current even in the stand-by mode.
  • As the design of integrated circuits has evolved toward uses in which low current stand-by modes are important, a need has arisen to provide internal supply voltages with much less stand-by current consumption than has been available in the prior art.
  • the present invention provides a low voltage supply circuit that supplies an internal supply voltage in an integrated circuit, which consumes very little stand-by current, yet provides substantial driving power to maintain the internal supply node at the desired voltage level.
  • the low voltage supply circuit of the present invention can be characterized as having a first branch which is connected to a first power supply node on an integrated circuit, and includes a pull-up circuit, a first transistor, a second transistor, and a reference circuit connected in series.
  • the first transistor has a drain, a source and a gate; the drain and the gate of the first transistor being connected to a first node.
  • the pull-up circuit in the first branch is coupled between the first node and the first power supply node.
  • the second transistor has a drain, a source and a gate; the drain and the gate of the second transistor being connected to a second node.
  • the reference circuit is connected between the ground supply node of the integrated circuit and the second node, supplying a reference potential to the second node.
  • a second branch of the low voltage supply circuit includes a third transistor and a fourth transistor.
  • the third transistor has a drain, a source and a gate; the drain of the third transistor being coupled to the second power supply node, the gate of the third transistor being connected to the first node in the first branch, and the source of the third transistor being connected to an output node for the low voltage supply circuit.
  • the fourth transistor in the second branch has a drain, a source and a gate. The drain of the fourth transistor is coupled to the ground supply node; the gate of the fourth transistor is connected to the second node in the first branch; and the source of the fourth transistor is connected to the output node.
  • the transistors in the first and second branches of the low voltage supply circuit are biased by circuits that induce a larger body effect in the fourth transistor than in the second transistor, so that the fourth transistor has a threshold voltage higher in absolute value than the second transistor.
  • the bias circuits also induce a larger body effect in the third transistor than in the first transistor, so that the third transistor has a threshold voltage higher in absolute value than the first transistor.
  • the internal supply voltage is provided at the output node on the second branch.
  • the level of the low supply voltage at the output node is determined by the reference voltage generated by the reference circuit in the first branch of the low voltage supply circuit, plus the threshold voltage on the fourth transistor. Because of the bias circuits, when the output node of the circuit reaches the desired level, both the third and the fourth transistors in the second branch are off. Thus, the stand-by current consumed by this circuit is limited essentially to that in the first branch of the circuit, which can be very small. Only when the output voltage is pulled downward by a load on the circuit do the transistors in the output branch turn on, to supply the needed drive current.
  • the stand-by current consumed according to one preferred embodiment of the present invention is in the range of 10 microamps, while the drive current capability of the circuit at the output node is several orders of magnitude higher, such as 5 milliamps or more.
  • the first and third transistors are n-channel field effect transistors
  • the second and fourth transistors are p-channel field effect transistors.
  • the p-channel transistors are formed in n-type wells on the integrated circuit.
  • the well of the second transistor is coupled to its source, to limit the body effect within the transistor. This establishes a threshold level for the second transistor which is near the intrinsic level for the device.
  • the n-type well of the fourth transistor is coupled to the supply potential, such as 5 volts, or another voltage level which is higher than the voltage generated at the output node.
  • the threshold voltage of the fourth transistor causes the threshold voltage of the fourth transistor to be increased by the body effect, to a level which is higher than the threshold voltage of the second transistor. Because the threshold voltage of the second transistor is less than the threshold voltage of the fourth transistor, the potential at the third node in the first branch of the circuit is less than the potential at the output node in the second branch of the circuit. This causes the source voltage on the first transistor to be lower than the source voltage on the third transistor. The lower source voltage causes a lesser body effect in the first transistor, than occurs on the third transistor. Thus the threshold of the first transistor is less than the threshold of the third transistor. In operation, the first branch of the circuit operates to generate steady reference voltages at the first and second nodes, which are connected respectively to the gates of the third and fourth transistors.
  • the fourth transistor When the voltage on the output node of the circuit is higher than the sum of the reference potential at the second node and the threshold of the fourth transistor, then the fourth transistor turns on and pulls the voltage potential down. When the voltage reaches a value equal to the sum of the reference potential at the second node plus the threshold voltage of the fourth transistor, then the fourth transistor turns off.
  • the third transistor turns on and pulls the voltage level at the output node up, until the output voltage reaches a value equal to the reference potential generated at the first node in the first branch of the circuit less the threshold of the third transistor. At this time, the third transistor turns off. Accordingly, the output branch of low voltage supply circuit of the present invention is normally off, and only generates current in response to loading on the output node. Stand-by current of the circuit is essentially limited to the first branch, which can be maintained at very low current levels.
  • resistive element connected between the first power supply node and the first node of the circuit.
  • resistive element comprises a p-channel field effect transistor in one alternative, having a gate coupled to a reference potential such as ground where it acts as a resistive element.
  • the reference circuit which is connected between ground and the second node of the first branch, comprises a p-channel field effect transistor having its gate coupled to a reference potential such as ground.
  • the reference circuit may comprise a low resistance connection between the second node and ground so that the reference potential at the second node of the circuit is substantially the ground potential.
  • switches for enabling and disabling the circuit are included.
  • a first switch is connected between the reference circuit and ground
  • a second switch is connected between the fourth transistor and ground.
  • the first and second switches enable the low voltage supply circuit when they are closed, and disable the low voltage supply circuit when they are open.
  • a third switch is coupled between the output node and the second supply potential.
  • the third switch enables the low voltage supply circuit when it is open, and disables the low voltage supply circuit when it is closed. Also, when closed, the third switch pulls up the voltage at the output node to the supply potential, providing an initialization value, and preventing the floating of the node.
  • a third switch is coupled between the third transistor and the second power supply node, which enables the circuit when it is closed, and disables the circuit when it is open.
  • the switches are implemented using transistors having their gates connected to a control signal in a preferred embodiment.
  • the first and second supply nodes as discussed above, are coupled to the first and second branches of the circuit.
  • the first branch of the circuit is used for generating constant reference voltages to control the operation of the second.
  • the standard power supply voltage is coupled to both the first and second power supply nodes on the integrated circuit.
  • a 5 volt +/- 10% power supply may be coupled to both branches of the circuit, resulting in lower power consumption, but less tight control over the output voltage node.
  • a more tightly regulated supply voltage can be utilized for the first branch of the circuit, such as supply voltages generated by voltage regulators, or otherwise tightly controlled.
  • the present invention provides a low voltage supply circuit for implementation on an integrated circuit, which consumes very little stand-by current yet provides substantial supply drive current for use in complex integrated circuits, such as flash memory devices.
  • FIG. 1 is a simplified diagram of the low voltage supply circuit of the present invention.
  • Fig. 2 is a more detailed circuit diagram of a preferred embodiment of the low voltage supply circuit of the present invention.
  • the low voltage supply circuit of the present invention includes a first branch 10 and a second branch 30.
  • the first branch 10 includes a pull-up element 11, such as a resistor which is connected between a supply node 12 and a first node 13 in the circuit.
  • a referenced circuit 14 is coupled between a second node 15 and ground terminal 16 in the first branch
  • a control switch 17 is connected between the reference circuit 14 and ground 16
  • a first transistor 18 and a second transistor 19 are connected between the first node 13 and the second node 15
  • the drain and gate of the first transistor 18 are connected to the first node 13
  • the drain and gate of the second transistor 19 are connected to the second node 15
  • the source of the first transistor 18 and the source of the second transistor 19 are coupled in common to a third node 20
  • the first transistor 18 is an n-channel field effect transistor.
  • the second transistor 19 is a p-channel field effect transistor which is implemented in a n-type well in the integrated circuit substrate
  • the n-type well 21 of the second transistor 19 is coupled to the third node 20 of the circuit.
  • the second branch of the circuit includes a third transistor 31 and a fourth transistor 32 which are connected between a supply node 33 and ground 34
  • a control switch 35 is connected between the fourth transistor 32 and ground 34
  • a control switch 36 is connected between the third transistor 31 and the supply potential 33
  • the third transistor 31 is a n-channel field effect transistor which has its gate connected to the first node 13 in the first branch 10 of the circuit, its source coupled to an output node 37 for the low voltage supply circuit, and its drain coupled to the supply potential 33 (optionally through switch 36).
  • the fourth transistor 32 is a p-channel field effect transistor implemented in a n-type well
  • the n-type well 38 is coupled to a supply potential such as about 5 volts, or another voltage which is higher than the potential at node 37.
  • the drain of transistor 32 is coupled to the ground potential 34 (optionally through switch 35).
  • the low voltage supply circuit of Fig. 1 generates the low supply potential AVX at node 37.
  • This supply potential is used for example in a flash memory device for the purpose of biasing wordline drivers on the device.
  • the low supply potential on line 37 is connected to a multiplexer 40.
  • Other inputs to the multiplexer include, for examples, the supply potential VDD on line 41, the output on line 42 of a charge pump circuit 43, or other voltage sources used for biasing the wordline driver.
  • the control signal on line 44 controls the multiplexer 40 to supply one of the input supply potentials on line 45 to the wordline driver.
  • the first branch 10 of the low voltage supply circuit is a low current leg which produces a reference potential VREF at node 15, and a reference potential VREF1 at node 13.
  • the reference circuit 15 is determined by the reference circuit 14.
  • the reference circuit 14 may take a variety of implementations, including a resistive element, a transistor biased as a resistive element, or a low resistance connection, such as a short circuit, directly to ground.
  • the reference potential at node 15 can be specified by design parameters of the reference circuit 14 as suits the needs of the particular implementation.
  • the reference potential VREF1 at node 13 is equal to the sum of the reference potential VREF at node 15, the absolute value of the threshold voltage I Vtp21 of transistor 19, and the threshold voltage
  • the pull-up circuit 11 is a resistive element which serves to limit the current through the first branch 10 preferably, in the microamp range such as about 10 microamps.
  • the second branch 30 of the low voltage supply circuit operates to supply current to node 37 which maintains the potential at the AVX level.
  • AVX level is equal to the sum of the reference potential VREF at node 15 plus the threshold voltage
  • the low voltage supply circuit of Fig. 1 includes bias circuits which take advantage of the body effect to control the threshold voltages of the first transistor 18, the second transistor 19, the third transistor 31, and the fourth transistor 32.
  • the n-well 21 of the second transistor is coupled to its source, substantially reducing the body effect, and establishing the threshold voltage I Vtp21 near the intrinsic threshold voltage for the device.
  • the n-well 38 of the fourth transistor 32 is coupled to the supply potential, or another potential higher than the source potential for the transistor 32.
  • the body effect increases the threshold
  • the threshold voltage Vtp2 of the second transistor 19 is less than the threshold potential
  • the third transistor 31 turns on when the voltage on its gate VREF1 is greater than its threshold plus the output voltage AVX as set out in equation (2):
  • VREF1 VREF1
  • the potential VREF1 is equal to the sum of the reference potential at node 15 plus the absolute value of the thresholds across the first and second transistors 18, 19, as set out in equation (3):
  • VREF1 VREF +
  • transistor 32 is likewise off.
  • the condition for turning on transistor 32 is set out in equation (5):
  • transistor 32 turns on pulling it down to the steady state condition. If the voltage on the output node 37 falls, then the transistor 31 turns on pulling it up to the steady state condition.
  • the low voltage supply circuit of the present invention has a very low stand-by current yet provides substantial drive when needed.
  • the supply voltage nodes 12 and 33 on the first branch 10 and second branch 30 respectively are typically supplied by one or more external power supplies for the integrated circuit.
  • the supply voltage node 12 on the first branch 10 can be coupled to the standard supply voltage which generates about 5 volts +/- 10%, or lower voltages, typically referred to as VDD. Alternatively, it may be coupled to the more tightly regulated potential which is typically 12 volts +/- 5%, referred to as VPP. More tightly regulated voltage at the supply node 12 results in better regulation of the level of AVX during operation. Thus, it may be preferable to provide a more tightly regulated voltage at node 12 than is available from the standard 5 volt VDD supply.
  • the supply node 33 on the second branch 30 may be less regulated, and is preferably coupled directly to the external supply voltage so that substantial drive current is available.
  • Fig. 2 provides a more detailed circuit diagram of a preferred embodiment of the present invention.
  • the embodiment of Fig. 2 is implemented on a single integrated circuit which has an external voltage supply VDD coupled to the power supply nodes 100, 130, 150, and 170 in the figure.
  • Ground supply nodes 160 and 161 are coupled to the external ground potential.
  • the ground supply node 162 is coupled to the external ground supply.
  • the external supply voltage VDD is about 5 volts +/- 10% in a preferred embodiment. Alternative systems may utilize lower VDD voltages as desired.
  • the first branch of the low voltage supply circuit in Fig. 2 includes p- channel transistor 101 having its source coupled to the supply node 100, its gate coupled to the ground supply node 162, and its drain connected to the first node 102 at which the potential VREF1 is generated.
  • the p-channel transistor 101 acts as a resistive element, and has a width of about 4 microns and a length of about 30 microns in the example of Fig. 2.
  • a n-channel transistor 103 has its drain and gate connected to node 102, and its source connected to node 104.
  • the n-channel transistor 103 corresponds to the first transistor 18 of Fig. 1.
  • Transistor 103 in this example has a width of about 20 microns and a length of about 1 micron.
  • a p-channel transistor 105 has its source connected to node 104, its gate connected to node 106, and its drain connected to node 106
  • the p-channel transistor 105 is formed in a n-well 107 which is coupled to the node 104.
  • Transistor 105 corresponds to the second transistor 19 in Fig. 1. In this example it has a width of about 20 microns and a length of about 1 micron.
  • P-channel transistor 108 has its source connected to node 106, and its gate and drain connected in common to node 109.
  • Transistor 108 acts as the reference circuit 14 of Fig. 1, establishing a voltage potential VREF at node 106 which is equal to its threshold voltage.
  • transistor 108 has a width of about 20 microns and a length of about 1 micron.
  • N-channel transistor 110 is connected between node 109 and the ground node 160
  • Transistor 1 10 has its gate connected to a control signal CTL on line 1 11
  • Transistor 1 10 acts as a switch for enabling and disabling the circuit in response to the control signal CTL online 1 1 1.
  • transistor 1 10 has a width of about 20 microns and a length of about 0.8 microns.
  • the p-channel transistors 101 and 108 are formed in n-wells which are coupled to the supply potential VDD (not shown).
  • the second branch of the circuit is coupled to the supply node 130.
  • the second branch includes n-channel transistor 131 having its drain connected to the supply potential 130, its gate connected to node 102, and its source connected to output node 132.
  • Transistor 131 corresponds to the third transistor 31 in Fig. 1.
  • N-channel transistor 131 in this example has a width of about 200 microns, and a length of about 1 micron.
  • P-channel transistor 133 has its source connected to node 132, its gate connected to node 106, and its drain coupled through switch transistor 134 to the ground potential 161.
  • Transistor 133 corresponds to the fourth transistor 32 in Fig. 1.
  • transistor 133 has a width of about 300 microns, and a length of about 1 micron.
  • the switch transistor 134 is a n-channel transistor having its drain connected to the drain of transistor 133, its gate connected to receive the control signal CTL on line 111, and its source coupled to the ground node 161.
  • the switch transistor 134 has a width of about 100 microns, and a length of about 0.8 microns.
  • the p-channel transistor 133 is formed in a n-type well, which is coupled to the supply potential VDD (not shown in the figure).
  • transistor 151 connected between the supply potential 150 and the output node 132.
  • Transistor 151 has its gate and drain coupled to the supply node 150, and its source connected to the output node 132.
  • Transistor 151 acts as a weak leaking transistor which prevents the output node 132 from floating in the event that the first branch of the circuit generating the reference potentials VREF1 and VREF does not operate properly.
  • Device 151 may or may not be necessary depending on a particular implementation of the circuit.
  • transistor 151 is a n- channel device having a width of about 3 microns, and a length of about 10 microns.
  • a control switch transistor 171 is coupled between the supply node 170 and the output node 132.
  • Switch transistor 171 is a p-channel transistor having its source connected to the supply potential 170, its drain connected to the output node 132, and its gate connected to the control signal CTL on line 1 1 1.
  • the transistor 171 is a p-channel transistor having a width of about 200 microns and a length of about 0.8 microns.
  • the circuit is enabled and disabled in response to the control signal CTL on line 1 1 1.
  • the control signal CTL When the control signal CTL is high, transistors 1 10 and 134 are on, and transistor 171 is off. This enables the circuit to generate the low voltage at node 132.
  • the control signal CTL When the control signal CTL is low, transistors 1 10 and 134 are off, and transistor 171 is on. This results in pulling up the node 132 to the supply potential, and turning off the low voltage supply circuit.
  • the circuit of Fig. 2 generates an output voltage which ranges from about 2.7 volts to about 3.2 volts.
  • the output voltage is achieved and stabilized for a 20,000 picoFarad loading in less than 30 microseconds.
  • the current through first branch including transistors 101, 103, 105, 108 and 110 is 12 microamps or less.
  • the current through the second branch including transistors 131, 133, and 134 is about 2 microamps or less.
  • Current through the weak pull-up transistor 151 is about 5 microamps or less. More typically, the current through the combination of the branches is less than
  • the drive current capable at node 132 from the supply potential 130 reaches the milliamp range very quickly when needed.
  • the circuit of Fig. 2 is capable of sourcing and sinking more than 5 milliamps of current.
  • the circuits described in Figs. 1 and 2 are used for generating a positive output voltage between the supply potential VDD and ground. Similar circuits can be utilized for generating a negative output voltage between a higher negative supply voltage and ground. To do so, the transistor types are changed from n- to p-channel, and from p- to n-channel as appropriate.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

L'invention porte sur un circuit d'alimentation basse tension qui fournit une tension interne à un circuit intégré tout en consommant en veilleuse une faible quantité de courant et en fournissant une puissance d'excitation importante de façon à maintenir les noeuds d'alimentation interne au niveau de tension désiré. Le circuit d'alimentation basse tension comprend une première et une seconde dérivation. La première dérivation comprend un circuit d'excursion haute (11), un premier transistor (18), un second transistor (19) et un circuit de référence (14) connectés en série. Le drain et la grille du transistor (18) sont raccordés à un premier noeud (13). Le circuit d'excursion haute (11) de la première dérivation est couplé entre le premier noeud (13) et le noeud d'alimentation (12). Le drain et la grille du second transistor (19) sont connectés à un second noeud (15). Le circuit de référence (14) est connecté entre le noeud d'alimentation au sol (34) du circuit intégré et le second noeud (15), fournissant ainsi un potentiel de référence au second noeud (15).
PCT/US1996/014712 1996-09-11 1996-09-11 Circuit d'alimentation basse tension Ceased WO1998011660A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/US1996/014712 WO1998011660A1 (fr) 1996-09-11 1996-09-11 Circuit d'alimentation basse tension
US08/849,676 US5877616A (en) 1996-09-11 1996-09-11 Low voltage supply circuit for integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1996/014712 WO1998011660A1 (fr) 1996-09-11 1996-09-11 Circuit d'alimentation basse tension

Publications (1)

Publication Number Publication Date
WO1998011660A1 true WO1998011660A1 (fr) 1998-03-19

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Family Applications (1)

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PCT/US1996/014712 Ceased WO1998011660A1 (fr) 1996-09-11 1996-09-11 Circuit d'alimentation basse tension

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5204612A (en) * 1990-10-29 1993-04-20 Eurosil Electronic Gmbh Current source circuit
US5315230A (en) * 1992-09-03 1994-05-24 United Memories, Inc. Temperature compensated voltage reference for low and wide voltage ranges
US5446397A (en) * 1992-02-26 1995-08-29 Nec Corporation Current comparator
US5481179A (en) * 1993-10-14 1996-01-02 Micron Technology, Inc. Voltage reference circuit with a common gate output stage
US5506543A (en) * 1994-12-14 1996-04-09 Texas Instruments Incorporated Circuitry for bias current generation
US5512855A (en) * 1990-10-24 1996-04-30 Nec Corporation Constant-current circuit operating in saturation region

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5512855A (en) * 1990-10-24 1996-04-30 Nec Corporation Constant-current circuit operating in saturation region
US5204612A (en) * 1990-10-29 1993-04-20 Eurosil Electronic Gmbh Current source circuit
US5446397A (en) * 1992-02-26 1995-08-29 Nec Corporation Current comparator
US5315230A (en) * 1992-09-03 1994-05-24 United Memories, Inc. Temperature compensated voltage reference for low and wide voltage ranges
US5481179A (en) * 1993-10-14 1996-01-02 Micron Technology, Inc. Voltage reference circuit with a common gate output stage
US5506543A (en) * 1994-12-14 1996-04-09 Texas Instruments Incorporated Circuitry for bias current generation

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