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WO1998010873A1 - Montage amplificateur pour la lecture d'une entree capacitive - Google Patents

Montage amplificateur pour la lecture d'une entree capacitive Download PDF

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Publication number
WO1998010873A1
WO1998010873A1 PCT/DE1996/001757 DE9601757W WO9810873A1 WO 1998010873 A1 WO1998010873 A1 WO 1998010873A1 DE 9601757 W DE9601757 W DE 9601757W WO 9810873 A1 WO9810873 A1 WO 9810873A1
Authority
WO
WIPO (PCT)
Prior art keywords
control signal
switch
amplifier circuit
field effect
effect transistor
Prior art date
Application number
PCT/DE1996/001757
Other languages
German (de)
English (en)
Inventor
Michael Schmidt
Original Assignee
Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. filed Critical Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
Priority to PCT/DE1996/001757 priority Critical patent/WO1998010873A1/fr
Publication of WO1998010873A1 publication Critical patent/WO1998010873A1/fr

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/52—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00
    • G01S7/523—Details of pulse systems
    • G01S7/526—Receivers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/52—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00
    • G01S7/523—Details of pulse systems
    • G01S7/524—Transmitters

Definitions

  • Amplifier circuit for reading out a capacitive input
  • the present invention relates to an amplifier circuit for reading out a capacitive input and in particular to such an amplifier circuit which can advantageously be used in a device which can be switched over between transmit and receive operation, for example an ultrasound system.
  • an ultrasound element In the field of ultrasound diagnostics, it is common to use an ultrasound element as a transmitter and receiver at the same time. For this purpose it must be ensured that the reflected signals can be selected by switching on the readout electronics after a very short settling time in the range of a few 100 nanoseconds. In many ultrasound systems, the time until the reflected signals arrive at the receiving electronics, i.e. the amplifier circuit for reading out the received signals, large, in the range of a few microseconds, since this time span is extended by a coupling-in link. This coupling section serves to acoustically adapt the ultrasound elements to the medium to be examined.
  • the state of the art for integrated miniaturized ultrasound readout amplifiers is the CMOS amplifier shown in FIG. 6.
  • the ultrasound signal source 10 formed by an ultrasound transducer element is in FIG. 6 by a current source I ⁇ s and a capacitance connected in parallel therewith Cus models.
  • the ultrasound transducer element thus represents a capacitive source.
  • the output of this ultrasound signal source is connected to the gate electrode of a field effect transistor.
  • a resistor Rf which is used to set the operating point of the amplifier, is connected between the gate electrode and the drain electrode of the transistor 12. This resistance together with the capacitance C ⁇ JS determines a time constant T, which determines the settling time of the amplifier.
  • the drain of transistor 12 is further connected to a bias current source modeled by a current source Ifc, ias.
  • An output node 14 of the ultrasound readout amplifier is also connected to the drain electrode of transistor 12.
  • the settling time can be set by setting the bias current I b as .
  • a high bias current I b ias is required to enable a sufficiently rapid settling.
  • a high bias current results in a negative increase in power loss.
  • the bias current is further switched off in the transmission mode, ie when the ultrasound element is pulsed to generate ultrasound waves, in order to reduce the total power loss.
  • the amplifier is only active in the receive mode, ie when receiving the reflected acoustic waves, with an ultrasonic transducer serving as a sensor.
  • the available power loss is often limited, since the surroundings must not be heated.
  • the object of the present invention is to provide an amplifier circuit for reading out a capacitive input and a method for operating the amplifier circuit which enable a very short switchover time from transmission to reception mode with a very low power loss.
  • the present invention provides an amplifier circuit for reading out a capacitive input with the following features: a field effect transistor, the gate electrode of which is connected to the capacitive input, the drain electrode of which is connected to a bias current source, and the source electrode of which is connected to ground, one Output node, which is connected to the drain electrode of the field effect transistor, a resistor, which is connected between the gate and the drain electrode, and a switch, with which the resistance between the gate and the drain electrode can be bridged.
  • the switch for bridging the gate and drain electrodes of the field effect transistor is preferably carried out as a function of a control signal which controls the switchover between a transmit and a receive mode.
  • the present invention makes it possible to implement control and readout electronics, for example for transmitting and receiving ultrasonic signals, with a very short switchover time to the receive mode and a very low power loss.
  • the amplifier circuit of the readout electronics can be followed by a powerful output driver for driving low-resistance transmission lines.
  • the powerful output driver preferably consists of an amplifier whose non-inverting input gang is connected directly to the output node, and its inverting input is connected to the output node via a low-pass filter.
  • FIG. 1 shows an amplifier circuit according to the present invention
  • FIG. 2 shows an output driver which can be connected downstream of the amplifier circuit from FIG. 1;
  • FIG. 3 shows signal diagrams of a control signal for switching between transmission and reception mode and a control pulse for closing the switch of the amplification circuit of the present invention
  • Fig. 4 is a diagram of a delay circuit
  • FIG. 5 is a circuit diagram showing an exemplary embodiment for generating the control current I INV1 shown in FIG. 4 from the control signal for switching between a transmit and a receive mode;
  • Fig. 6 shows a known ultrasonic readout amplifier.
  • FIG. 1 shows a basic circuit diagram of an amplifier circuit of the present invention.
  • An ultrasound element 100 is in turn modeled as an ultrasound signal source by the current source Ius unc * a capacitance Cus.
  • the output of the signal source 100 is connected to the gate electrode of a field effect transistor 110.
  • the field effect transistor 110 can be a CMOS transistor, for example.
  • the source electrode of the field effect transistor 110 is grounded.
  • a resistor Rf is connected between the drain electrode and the gate electrode of transistor 110 to set the operating point.
  • a bias current source is also connected to the drain electrode of the field effect transistor.
  • the bias current source is modeled by a current source that generates the current Ibias.
  • the resistor Rf can now be bridged by a switch 120.
  • This switch 120 can be implemented by a transistor.
  • the switch 120 is closed at the time of switching from the transmission mode to the reception mode.
  • the resistor R f is thereby bridged, as a result of which the ultrasound capacitance Cys can be charged more quickly to the input potential of the amplifier.
  • a pulse with a defined width and a defined delay with regard to the changeover time that is used to close the switch 120 can be generated at the time of switching from the transmit mode to the receive mode.
  • the settling time can also be shortened by the fact that the bias current I b ias is not completely switched off during the transmission operation in order to enable the greatest possible power loss reduction, but is reduced to a minimum current.
  • the amplifier is kept at its operating point by means of this minimal current. In the receive mode, the pre-flow is then increased to the required operating current. The fact that the amplifier also during the transmission mode is kept in its operating point, the transient response of the amplifier circuit is further improved.
  • An output node 130 is also shown in FIG. 1, from which the amplified signal of the signal source 100 can be taken.
  • FIG. 2 shows an output stage which can be connected downstream of the amplifier circuit shown in FIG. 1 for driving low-resistance transmission lines.
  • the output stage of the amplifier circuit which is shown in FIG. 1, is connected downstream at point 130.
  • the output stage must supply the signals detected and amplified by the amplifier to an external signal processing system via a low-resistance transmission line.
  • the output stage has an AB operation amplifier 200 with a differential input.
  • the non-inverting input of amplifier 200 is connected directly to output node 130.
  • the inverting input of amplifier 200 is connected to output node 130 via a low-pass filter, which is formed by a resistor R and a capacitor C.
  • the resistor R can be bridged by means of a switch 210.
  • the switch 210 can be implemented by a transistor.
  • An offset signal is generated by the low-pass filter, which is formed by the resistor R and the capacitor C. Due to the difference between the offset signal and the amplified signal, only the detected signal is transmitted.
  • the output of the AB output stage is connected to a low-resistance transmission line.
  • the output of the AB output stage is kept at the center potential of the stage by the low-resistance resistor ZL of the transmission line.
  • the output stage is also operated with a reduced bias current. As a result, the stage remains at its operating point even in transmission mode.
  • the short settling time required for this stage is achieved by closing the switch 210 and bridging the resistor R, and by virtue of the fact that this stage remains in its operating point during the transmission operation.
  • the number of connecting lines to external signal processing electronics is limited. It is thus advantageous that the to improve the settling time, i.e. pulse signals required for closing the switch 120 and the switch 210 are generated from existing signals.
  • an existing signal that is used to switch between the transmit and receive operation of the ultrasonic transducer can be used.
  • control signal shown has two voltage level ranges, high and low.
  • the voltage level of the control signal in these areas, high and low can vary in a potential band for reliable detection. This area is used to control a delay line.
  • a control pulse is generated in each case in response to the falling edges of the control signal associated with the switchover from the high to the low level range, ie, the switchover from the transmit mode to the receive mode.
  • the delay of the control pulse with respect to the falling edge depends on the level of the control signal within the high level range.
  • a control signal level 300 in the upper range of the high level range results in a smaller delay than a lower level 310 within the high level range has a delay time of t 2 .
  • a lower signal level during the reception mode within the low 320 level range results in a smaller pulse width T- ⁇ , while a higher level of the control signal in the reception mode within the low level range low 330 results in a larger pulse width T 2 .
  • FIG. 4 shows a circuit implementation for generating the control pulse.
  • the control signal is fed to two inverters INV1 and INV2 connected in series.
  • the output of each inverter is connected to ground via a capacitor 400, 402.
  • the output of the inverter INV1 is connected to a first input of an inverting OR gate 404, while the output of the inverter INV2 is connected to a second input of the OR gate 404.
  • the output of the OR gate is connected to an inverter 406 in the example shown.
  • the control pulse for switching the switch 120 or the switch 210 is then present at the output 410.
  • the inverter INVL and INV2 each have through a controllable supply current IJNVI and INV2 I i ne adjustable slew rate (slew rate).
  • the capacitors 400 and 402 and the rate of rise generate a pulse of a defined width with a defined delay with respect to the negative edge on each negative edge of the control signal, ie on each switchover from transmit to receive mode.
  • a circuit diagram is explained below with reference to FIG. 5, which represents a possibility for generating the control current IINVI of the inverter INV1 from the control signal for switching the ultrasound system from the transmit mode to the receive mode.
  • a Schmitt trigger 500 to which the control signal is coupled opens a switch 502 when the control signal reaches the low level range low.
  • a first terminal of switch 502 is connected to the input line on which the control signal is supplied.
  • a second connection of the switch 502 is connected to a resistor 506 via a capacitance 504.
  • the resistance can be modeled by a transistor with a constant gate-source potential.
  • the "high" potential remains on the capacitor 504 after the switch has been opened (node 510).
  • the node 510 is connected to the gate electrode of a transistor 530.
  • a current flows through a transistor 530 depending on the high level. This current is fed through the transistor 520 to the inverter INV1 as a supply current.
  • the current IJNV2 for the inverter INV2 can be controlled by the "low" potential by means of a stage which is complementary to the stage shown in FIG.
  • the present invention thus provides an amplifier circuit for reading out a capacitive input, in which the settling behavior of an amplifier, for example for an ultrasound transducer, is improved by a switched feedback.
  • Power management to reduce the total power loss ensures that the amplifier stage, or the plurality of amplifier stages, remains at the operating point during the transmission mode of the ultrasound system. This increases the settling time of the amplifiers additionally improved.
  • the described output stage represents a transition from a "single-ended" amplifier to a "differential-in" AB output stage.
  • Another advantage of the present invention is that the required control pulse is generated from existing signals by means of a controllable delay line is produced.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)
  • Investigating Or Analyzing Materials By The Use Of Ultrasonic Waves (AREA)

Abstract

Un montage amplificateur pour la lecture d'une entrée capacitive possède un transistor à effet de champ dont la grille est reliée à l'entrée capacitive, le drain à une source de courant de polarisation et la source à la masse. Un noeud de sortie est également relié au drain tandis qu'une résistance est montée entre la grille et le drain du transistor à effet de champ. Cette résistance peut être pontée au moyen d'un interrupteur. La fermeture commandée de cet interrupteur permet d'améliorer le comportement de rétablissement du montage amplificateur.
PCT/DE1996/001757 1996-09-12 1996-09-12 Montage amplificateur pour la lecture d'une entree capacitive WO1998010873A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/DE1996/001757 WO1998010873A1 (fr) 1996-09-12 1996-09-12 Montage amplificateur pour la lecture d'une entree capacitive

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/DE1996/001757 WO1998010873A1 (fr) 1996-09-12 1996-09-12 Montage amplificateur pour la lecture d'une entree capacitive

Publications (1)

Publication Number Publication Date
WO1998010873A1 true WO1998010873A1 (fr) 1998-03-19

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Application Number Title Priority Date Filing Date
PCT/DE1996/001757 WO1998010873A1 (fr) 1996-09-12 1996-09-12 Montage amplificateur pour la lecture d'une entree capacitive

Country Status (1)

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WO (1) WO1998010873A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4277978A (en) * 1980-01-17 1981-07-14 General Electric Company Adaptive input circuit
JPH02185238A (ja) * 1989-01-11 1990-07-19 Aloka Co Ltd 超音波診断装置
US5271403A (en) * 1991-09-05 1993-12-21 Paulos John J Ultrasound imaging system
US5483963A (en) * 1994-07-22 1996-01-16 Loral Infrared & Imaging Systems, Inc. Two dimensional transducer integrated circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4277978A (en) * 1980-01-17 1981-07-14 General Electric Company Adaptive input circuit
JPH02185238A (ja) * 1989-01-11 1990-07-19 Aloka Co Ltd 超音波診断装置
US5271403A (en) * 1991-09-05 1993-12-21 Paulos John J Ultrasound imaging system
US5483963A (en) * 1994-07-22 1996-01-16 Loral Infrared & Imaging Systems, Inc. Two dimensional transducer integrated circuit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 014, no. 458 (C - 0766) 3 October 1990 (1990-10-03) *

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