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WO1998009225A1 - Systeme logiciel temps reel - Google Patents

Systeme logiciel temps reel Download PDF

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Publication number
WO1998009225A1
WO1998009225A1 PCT/US1997/013182 US9713182W WO9809225A1 WO 1998009225 A1 WO1998009225 A1 WO 1998009225A1 US 9713182 W US9713182 W US 9713182W WO 9809225 A1 WO9809225 A1 WO 9809225A1
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WO
WIPO (PCT)
Prior art keywords
operating system
time
cpu
standard
time slice
Prior art date
Application number
PCT/US1997/013182
Other languages
English (en)
Inventor
Frank G. Logan, Iii
Jeffrey M. Achesinski
Teddy M. Davis
Original Assignee
Nematron Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nematron Corporation filed Critical Nematron Corporation
Priority to EP97939349A priority Critical patent/EP1008054A1/fr
Priority to AU41457/97A priority patent/AU4145797A/en
Publication of WO1998009225A1 publication Critical patent/WO1998009225A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G06F9/4887—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues involving deadlines, e.g. rate based, periodic

Definitions

  • the present invention relates generally to a method and apparatus for operating computer systems and, in particular, to a method and apparatus for operating a computer system on a real time basis.
  • I/O input/output
  • devices such as timers and memory controllers generate events which require service.
  • an I/O bus can be connected to peripheral devices requiring service such as a network communication adapter card, a printer interface, a keyboard interface, a mouse interface, a floppy drive, a hard drive, a CD-ROM drive, a tape drive, etc.
  • Two common techniques for servicing events are polling and interrupt.
  • a processor utilizing the polling technique regularly reads the status of devices that may need service. This checking is done during the normal execution of the operating system program and any applications program.
  • polling may not be sufficiently responsive to events which occur asynchronously.
  • Devices which generate a relatively large quantity of data may exceed the available buffer memory between the regular polling times in successive processor polling cycles.
  • polling can result in a large number of processor cycles during which no service operations are necessary.
  • the interrupt technique is utilized to solve some of the real time disadvantages of the polling technique.
  • a device When a device requires service, it generates an interrupt signal that causes the processor to execute an interrupt service routine.
  • the processor stops execution of program instructions, stores the current status information for the program, executes the interrupt service routine and restores the current status information.
  • the processor becomes less efficient at running the current program due to the extra time required to store and reload the current status information at each interrupt.
  • U.S. Patent No. 4,228,495 discloses a typical multiprocessor solution for a numerical control system.
  • the system includes a main microprocessor, a programmable interface with an I/O microprocessor and a front panel microprocessor.
  • the main microprocessor performs the functions of interpolation and outputing of motion command signals
  • the I/O microprocessor operates as a programmable controller to control the process equipment
  • the front panel microprocessor services the I/O devices associated with the front control panel.
  • the main microprocessor operates under the direction of a scheduler routine which is clocked at 1.6 msec intervals and has a 25.6 msec cycle.
  • the scheduler routine allocates 1.6 msec slices to various processes to be performed including a timed interrupt process that outputs motion commands to the servomechanism interface and exchanges data with the programmable interface.
  • the timed interrupt process is always executed to completion during a scheduler cycle such that the number of 1.6 msec intervals required by it will vary from cycle to cycle.
  • the U.S. Patent No. 5,163,146 discloses a computer which has an operating system program that includes an interrupt handler module.
  • the program changes the speed of the computer clock to maintain the computer in synchronism with an I/O adapter or to speed up the operation when slower speed circuits are not being utilized. Circuits and programs which require like cycle times are associated with a common interrupt level and the operating program changes the clock speed in response to the current interrupt level.
  • the U.S. Patent No. 5,437,039 discloses a system management interrupt handler comprising a plurality of service tasks which are executed interleavingly with normal execution.
  • a prior art non-maskable transparent system management interrupt (SMI) is described in connection with Fig. 1 wherein a SMI places the computer system into an execution mode that is transparent to the operating system. A dedicated memory area not mapped in the computer's memory address space is swapped in to store the system state before the interrupt handler is given control. Interrupt latency in this prior art system is reduced by providing a reserved trigger timer (Fig. 6). If the SMI was not caused by the timer, service tasks associated with the SMI are queued and the computer returns to the normal execution. If the SMI was caused by the timer, the next queued service task is executed and the computer returns to the normal execution.
  • SMI non-maskable transparent system management interrupt
  • the present invention concerns a method and an apparatus for operating a computer system, the computer system having a memory for storing an operating system and a CPU for executing program instructions under control of the operating system.
  • the method according to the present invention includes the steps of: storing a first operating system in a first portion of the memory; operating the CPU under the control of the first operating system to generate a plurality of standard time slices; storing a second operating system in a second portion of the memory; operating the CPU under the control of the second operating system concurrently with the first operating system to generate at least one first time slice and at least one second time slice during each of the standard time slices; executing at least one program instruction in accordance with the first operating system during the first time slice; and executing at least one other program instruction in accordance with the second operating system during the second time slice.
  • the computer system includes a CPU connected to a memory for executing program instructions according to an operating system and comprises: the memory having a first portion in which a first operating system is stored and a second portion in which a second operating system is stored; and the CPU operating under control of the first operating system to sequentially generate standard time slices and concurrently operating under control of said second operating system to divide the standard time slices into at least one first time slice and at least one second time slice, the CPU executing first program instructions during the first time slice and executing second program instructions during the second time slice.
  • the present invention overcomes the disadvantages of prior art process controllers by utilizing a standard personal computer running a commercially available operating system to control a manufacturing process requiring "hard" real time interrupts.
  • a further advantage of the present invention is that the portion of the standard time slice devoted to "hard” real time operation can be selectively varied to maximize the performance of the control system.
  • FIG. 1 is a schematic block diagram of a typical microprocessor based computer system
  • Fig. 2 is schematic memory map diagram of a prior art generic operating system in the random access memory shown in the Fig. 1 ;
  • Fig. 3 is schematic memory map diagram of a prior art Windows NT operating system in the random access memory shown in the Fig. 1 ;
  • Fig. 4 is a timing diagram of a typical instruction cycle for the computer system shown in the Fig. 1 ;
  • Fig. 5 is a flow diagram of the operating system instruction cycle shown in the Fig. 4 and an interrupt service routine for the computer system shown in the Fig. 1 ;
  • Fig. 6 is a timing diagram of the time slices for the operating systems shown in the Fig. 2 and the Fig. 3;
  • Fig. 7 is a plot of time slice length versus overhead for the computer system shown in the Fig. 1 ;
  • Fig. 8 is schematic memory map diagram similar to the Fig. 3 configured to include a real time software system in accordance with the present invention;
  • Fig. 9 is a timing diagram of the operating system time slices generated by the real time software system shown in the Fig. 8;
  • Fig. 10 is a timing diagram similar to the Fig. 9 with the operating system time slices modified in accordance with the present invention.
  • the system 10 includes an expanded central processing unit 12, an input/output unit 14 and a graphics interface unit 16 each connected to a main bus 18.
  • the expanded central processing unit 12 has a central processing unit (CPU) 20 connected to a CPU bus 22.
  • the expanded central processing unit 12 also includes a bus control 24, a cache control 26 and a RAM control 28 each connected to the bus 22.
  • the bus 22 is connected for communication to the main bus 18 through a plurality of line buffers 30.
  • a cache memory 32 external to the expanded central processing unit 12, is connected to and controlled by the cache control 26.
  • a random access memory (RAM) 34 is located external to the expanded central processing unit 12 and is connected to and controlled by the RAM control 28.
  • the input/output unit 14 includes parallel I/O ports 36 and serial I/O ports 38 connected to an I/O bus 40 which in turn is connected to the main bus 18.
  • the input/output unit 14 further includes a programmable interrupt control 42, a programmable timer 44, a direct memory access control 46, a real time clock unit 48 and a hard drive control 50 all connected to the input/output unit bus 40.
  • a hard drive 52 External to the input/output unit 14 and connected to the main bus 18 is a hard drive 52 which is controlled by the hard drive control 50.
  • the hard drive 52 and the associated control 50 represent any type of mass storage device suitable for use with a microprocessor based computer.
  • the graphics interface unit 16 includes a video graphics control 54 and a video memory control 56 connected to a graphics bus 58 which in turn is connected to the main bus 18. External to the graphics interface unit 16 is a video memory 60 which is connected to the video memory control 56 and to the main bus 18. The video memory 60 can be accessed by the video memory control 56 and through the main bus 18. A monitor interface 62 is connected between the video memory 60 and a video monitor 64. Also connected to the main bus 18 are one or more device controls 66 which in turn are connected to associated devices 68. The controls 66 and the devices 68 can include a network communication adapter card, a printer interface, a keyboard interface, a mouse interface, a floppy drive, a CD- ROM drive, a tape drive, etc.
  • the CPU 20 includes logic for executing a plurality of program instructions and for executing a plurality of hardware and software interrupts.
  • the hardware and software interrupts occur as the result of external events and system traps. Interrupts are serviced after execution of the current instruction in accordance with an interrupt service routine.
  • the interrupts are classified into two types: maskable and non-maskable. Maskable interrupts are typically used to respond to asynchronous external hardware events and non-maskable interrupts are typically used to service very high priority events.
  • Fig. 2 a schematic memory map diagram of the RAM 34 when hardware 70 (the various components shown in the Fig. 1) of the computer system 10 is under the control of a generic or standard operating system.
  • Typical standard operating systems include MS-DOS, Windows 3.x and Windows 95 (from Microsoft), DOS (various versions), OS/2 (from IBM Corporation), Unix (various versions) and NetWare (from Novell).
  • MS-DOS Windows 3.x and Windows 95
  • DOS variable versions
  • OS/2 from IBM Corporation
  • Unix variant versions
  • NetWare from Novell
  • a kernel which is that portion of the operating system which remains continuously in main memory and consists of the most frequently used part of the operating system.
  • the kernel is responsible for the creation, deletion and state-switching of the many processes that define the computer's behavior by quickly responding to a steady flow of interrupt requests.
  • the kernel is stored in a kernel portion 72 of the RAM 34.
  • a user application which is stored in a user applications portion 74 of the RAM 34.
  • a hardware abstraction layer (HAL) portion 78 At the most basic level is a hardware abstraction layer (HAL) portion 78. Above the HAL 78 is the kernel portion 72 and the user applications portion 74.
  • a timer portion 80 of the operating system which defines times at which various operating system events occur.
  • the CPU 20 In order to execute the instructions of a program such as an operating system or a user application, the CPU 20 must first fetch the instruction from the memory 34.
  • the sequence of operations involved in processing an instruction constitutes an instruction cycle which is subdivided into a fetch cycle and an execution cycle.
  • the instruction is obtained from main memory during the fetch cycle and the instruction cycle includes decoding the instruction, fetching any required operands and performing the operation specified by the instruction's opcode.
  • the instruction cycle is defined by a sequence of microoperations with CPU cycle time being the time for the shortest well-defined such microoperation.
  • the CPU cycle time is the basic unit for measuring CPU actions and the reciprocal of this time is the CPU clock rate.
  • a typical CPU running at a 100 Mhz cycle rate will have a 10 nsec CPU cycle duration.
  • a typical instruction cycle 82 includes in sequence a first CPU cycle "Fetch Instruction” 82a, a second CPU cycle “Decode Instruction” 82b, a third CPU cycle “Fetch Operand” 82c, a fourth CPU cycle “Execute Instruction” 82d and a fifth CPU cycle "Store Result” 82e.
  • a DMA (direct memory access) breakpoint 82f or 82g At the end of any CPU cycle is a DMA (direct memory access) breakpoint 82f or 82g at which point the CPU 20 will yield control of the main bus 18 to a device in response to a DMA request received during that CPU cycle.
  • the DMA breakpoint 82g at the end of the fifth CPU cycle also is an interrupt breakpoint at which point the CPU 20 tests for the presence of an interrupt signal. If the interrupt signal test is positive, the CPU 20 stores the current status information and executes an interrupt service routine to process the interrupt signal received during the instruction cycle 82.
  • some instructions are longer and require an instruction cycle with more CPU cycles.
  • Fig. 5 a flow diagram of the operation of the operating systems shown in the memory maps of the Fig. 2 and the Fig. 3.
  • the operating system begins at "START" 84 and enters a decision point "INST. ?" 86 wherein it is determined whether an instruction is to be executed. If no instruction is to be executed, the program branches at "NO” and re-enters the decision point 86 to again look for an instruction. If an instruction is to be executed, the program branches at "YES” to an instruction set "FETCH INSTRUCTION” 88 which corresponds to the CPU cycle 82a shown in the Fig. 4. The program next moves to an instruction set "EXECUTE INSTRUCTION” 90 wherein the CPU cycles 82b through 82e of the instruction cycle 82 are performed.
  • the program then enters a decision point "INT ?" 92 to test for an interrupt. If no interrupt has occurred, the program branches from the decision point 92 at "NO” and enters an instruction set "STORE CURRENT STATUS INFORMATION" 94. Now the program has entered the interrupt service portion of the operating system and the information currently being processed by the computer is stored as the current status information. The program enters an instruction set "EXECUTE INTERRUPT SERVICE ROUTINE” 96 wherein the interrupt is serviced in accordance with an associated set of stored interrupt service instructions executed during subsequent cycles. After the interrupt has been serviced, the program enters an instruction set "RECALL CURRENT STATUS INFORMATION" 98 wherein the previously stored program information is recalled into the computer memory.
  • the program then returns to decision point 86 to look for the next program instruction to be executed.
  • the basic unit of computing managed by an operating system is a process or task which can be defined as a self-contained program module in the course of execution.
  • the operating system must allocate multiple resources to and schedule the tasks.
  • a clock such as the real time clock 48 of the Fig. 1 , generates an interrupt which can be used to define the duration of a time slice in which the operating system can execute instructions to perform a task.
  • the use of time slices permits the CPU to multiplex tasks so that two or more tasks appear to be running at the same time.
  • a typical hardware timer circuit defines a time slice duration of approximately 10 msec. Although the time slice duration can be reduced, computer system operating requirements usually dictate a lower limit of approximately one msec.
  • a first standard time slice 100 extends from time zero to a time tl
  • a second standard time slice 100 extends from the time tl to a time t2
  • a third standard time slice 100 begins at the time t2.
  • the time slices 100 and subsequent such time slices are of equal length or duration as defined by the timer.
  • Each of the standard time slices 100 includes a processing portion 102 having a plurality of the instruction cycles 82 for executing program instructions.
  • a part of the standard time slice 100 must be used to switch to the next time slice and the task to be performed therein which part is known as a CPU "overhead" portion "OH" 104.
  • the duration of the "overhead" portion 104 remains relatively constant as the duration of the time slice 100 is decreased.
  • hard real time In process control systems, data exchange cycle times of less than one millisecond are known as "hard real time.”
  • the hardware timer used in a typical computer system is set to limit the time slice duration to approximately ten milliseconds, but could be set faster.
  • the time slice duration is selected based upon the operating system performance and the CPU speed. If the clock rate is increased to a "hard” real time rate, the increase in CPU “overhead” would seriously impact the performance of the standard operating system and the user programs.
  • commonly used operating systems do not run in a deterministic manner. That is, they do not run programs in a repeatable fashion which is required for real time control. Therefore, although the standard computer system 10 running a commercially available operating system has the computing power to run real time control programs, the interrupt response rate and non- deterministic operating system cannot provide the level of control required for many real time processes.
  • CNC equipment and manufacturing robots typically require data exchange on the order of every 250 microseconds.
  • Servoactuators typically require data exchange on the order of every 100 microseconds. Therefore, the method and apparatus according to the present invention provides the precise control required by such manufacturing equipment while allowing the use of a standard operating system and standard computer hardware.
  • the method and apparatus according to the present invention solves the real time environment problems by reserving a portion of the standard microprocessor random access memory for running a real time software system program.
  • the real time software system decreases the duration of the time slices to provide deterministic services and control the external data exchange at a "hard" real time interrupt rate permitting precise control of process equipment such as robot servomotors.
  • the real time software system also provides time slices in which the regular operating system runs.
  • a real time control application must be able to service interrupts in "hard” real time and run "normal” control algorithms (i.e. non-interrupt driven) in a deterministic fashion.
  • the standard operating system does not perform in this manner.
  • the RTSS according to the present invention solves this problem by running a concurrent operating system with the same physical hardware as the standard operating system.
  • the RTSS shares the CPU 20 with the standard operating system in a deterministic manner to provide deterministic services to the user.
  • RTSS can provide libraries for implementing "hard" real time interrupt routines, libraries for high speed deterministic inter-task communication, libraries for high speed deterministic inter-task synchronization, prioritized high speed deterministic task management, libraries for direct hardware access and libraries for communication with vendor specific hardware for process control.
  • FIG. 8 a schematic memory map diagram of a computer memory configuration including a real time software system in accordance with the present invention.
  • the user applications portion 74 of the RAM 34 shown in the Fig. 3 has had two sections of memory divided therefrom.
  • a first section or RTSS portion 76a is available for an alternate operating system in accordance with the present invention and a second section or micro-kernel portion 76b stores the kernel for the RTSS.
  • the portions 76a and 76b can be smaller than the corresponding portions 74 and 72 for the standard operating system due to the relative size of the software programs.
  • the portions 72, 74, 78 and 80 can be a total of 30 MB and the portions 76a and 76b can be a reserved 2 MB portion of the total memory capacity.
  • FIG. 9 a timing diagram of the time slices for the configuration shown in the Fig. 8.
  • a first RTSS time slice 108 is utilized to run the real time software system and a second OS time slice 110 is utilized to run the standard operating system.
  • the RTSS takes over the system timer or the external non-maskable interrupt clock and utilizes the clock pulses which define the standard time slice 100 in the Fig. 6 to subdivide into shorter duration time slices by a high speed interrupt.
  • the time slices 108 and 110 can each be one half millisecond in duration.
  • the time slices 108 and 110 can be generated with durations in the microsecond range. For example, a time slice duration of 25 microseconds means that any real time interrupt to be serviced by the RTSS is delayed no more than the 25 microseconds duration of the OS time slice 110.
  • Such operation has the advantage of not changing the CPU "overhead" since the standard operating system still runs on the standard time slice 100, but with one half of the processing time.
  • the time slices 108 and 110 do not have to be equal in number such that a duty cycle (the number the portions 108 divided by the sum of the number of the portions 108 and the number of the portions 110 in a predetermined period) can be varied to optimize the performance of the computer system 10.
  • a duty cycle the number the portions 108 divided by the sum of the number of the portions 108 and the number of the portions 110 in a predetermined period
  • the number of the RTSS time slices 108 can be increased to accommodate more processing time as long as the degradation in the response time of the program being executed during the standard operating system time slices 110 can be tolerated.
  • a method of changing the duty cycle is shown in the Fig. 10 wherein two RTSS time slices 108 are generated for each OS time slice 110. This ratio can be selected to provide the desired performance.
  • the duration of the time slices 108 and 110 can be determined by an optional external timer circuit that utilizes a non-maskable interrupt to generate a timing signal for the real time software system task switcher to use to divide the standard time slice 100.
  • an RTSS timer 112 can be connected to the main bus 18 to respond to the interrupt generated by the real time clock 48 for determining the duration of the standard time slice 100.
  • the timer 112 is setable or programmable for generating non-maskable interrupts at a rate which defines the duration of the time slices 108 and 110.
  • the timer 112 can be connected to the computer system 10 in any suitable manner in order to generate the non-maskable interrupts.
  • the method of operating the computer system 10 comprising the steps of: a. storing a first operating system in the first portion 72 of the memory; b. operating the CPU under the control of the first operating system to generate a plurality of standard time slices 100; the method characterized by the steps of: c. storing a second operating system in the second portion 76a, 76b of the memory; d. operating the CPU under the control of the second operating system concurrently with the first operating system to generate at least one first time slice 110 and at least one second time slice 108 during each of the standard time slices; e. executing at least one program instruction in accordance with the first operating system during the first time slice; and f. executing at least one other program instruction in accordance with the second operating system during the second time slice.
  • the computer system 10 includes the
  • CPU 20 connected to the memory 34 for executing program instructions according to an operating system comprising: the memory having the first portion 72 in which the first operating system is stored and the second portion 76a,76b in which the second operating system is stored; and the CPU operating under control of the first operating system to sequentially generate the standard time slices 100 and operating concurrently under control of the second operating system to divide the standard time slices into at least one of the first time slices 110 and at least one of the second time slices 108, the CPU executing first program instructions during the first time slice and executing second program instructions during the second time slice.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

L'invention concerne un système informatique (10) et son procédé de préparation, ce système comprenant une mémoire (34) dans une première partie (72) de laquelle est stocké un système d'exploitation standard et dans une seconde partie (76a, 76b) de laquelle est stocké un système logiciel temps réel, et une unité centrale (20) connectée à la mémoire. Le système d'exploitation standard commande l'unité centrale (20) en vue de générer des tranches de temps standards (100) possédant chacune une pluralité de cycles d'instructions (82), et le système logiciel temps réel commande l'unité centrale en vue de diviser les tranches de temps standards en tranches de temps (108) du système logiciel temps réel et en tranches de temps (110) du système d'exploitation standard. Des instructions du programme temps réel s'exécutent durant les tranches de temps (108) du système logiciel temps réel, et d'autres instructions du programme s'exécutent durant les tranches de temps (110) du système d'exploitation standard. Le système logiciel temps réel peut sélectionner un cycle de services applicable au rapport existant entre le nombre de tranches de temps (108, 110) et la tranche de temps standard. Une pluralité d'interruptions entrée/sortie peuvent être satisfaites sur une base temps réel dans les tranches de temps du système logiciel temps réel.
PCT/US1997/013182 1996-08-29 1997-07-28 Systeme logiciel temps reel WO1998009225A1 (fr)

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Application Number Priority Date Filing Date Title
EP97939349A EP1008054A1 (fr) 1996-08-29 1997-07-28 Systeme logiciel temps reel
AU41457/97A AU4145797A (en) 1996-08-29 1997-07-28 Real time software system

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US70528596A 1996-08-29 1996-08-29
US08/705,285 1996-08-29

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002001348A3 (fr) * 2000-06-28 2003-05-22 Intel Corp Procede et dispositif pour exploitation en temps reel dans un systeme d'ordinateur personnel
EP1164483A3 (fr) * 2000-06-14 2006-01-25 Siemens Aktiengesellschaft Système et méthode pour réduire la gigue dans un signal
GB2423843A (en) * 2005-03-02 2006-09-06 Symbian Software Ltd Providing real time performance with memory paging by providing a real time and a non-real time version of the operating system.
EP1574940A3 (fr) * 2004-03-11 2008-11-26 Samsung Electronics Co., Ltd. Appareil de gestion de données et procédé pour une mémoire flash.
US8719836B2 (en) 2003-10-16 2014-05-06 Kuka Laboratories Gmbh Method and device for operating a secondary operating system auxiliary to a primary operating system

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4736318A (en) * 1985-03-01 1988-04-05 Wang Laboratories, Inc. Data processing system having tunable operating system means
US5222215A (en) * 1991-08-29 1993-06-22 International Business Machines Corporation Cpu expansive gradation of i/o interruption subclass recognition
US5394547A (en) * 1991-12-24 1995-02-28 International Business Machines Corporation Data processing system and method having selectable scheduler
US5437039A (en) * 1992-05-21 1995-07-25 Intel Corporation Servicing transparent system interrupts and reducing interrupt latency
US5528513A (en) * 1993-11-04 1996-06-18 Digital Equipment Corp. Scheduling and admission control policy for a continuous media server

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4736318A (en) * 1985-03-01 1988-04-05 Wang Laboratories, Inc. Data processing system having tunable operating system means
US4908750A (en) * 1985-03-01 1990-03-13 Wang Laboratories, Inc. Data processing system having tunable operating system means
US5222215A (en) * 1991-08-29 1993-06-22 International Business Machines Corporation Cpu expansive gradation of i/o interruption subclass recognition
US5394547A (en) * 1991-12-24 1995-02-28 International Business Machines Corporation Data processing system and method having selectable scheduler
US5437039A (en) * 1992-05-21 1995-07-25 Intel Corporation Servicing transparent system interrupts and reducing interrupt latency
US5528513A (en) * 1993-11-04 1996-06-18 Digital Equipment Corp. Scheduling and admission control policy for a continuous media server

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
DR. DOBB'S JOURNAL, January 1993, Vol. 18, No. 1, SHAH K., "Windows DDE for Real-Time Applications", p.58(4). *
DR. DOBB'S JOURNAL, November 1992, Vol. 17, No. 11, POTTER D., "Designing a Real-Time Debugger, The Best of Both Worlds", p. 70(7). *
SILBERSCHATZ A. et al., "Operating System Concepts", ADDISON-WESLEY PUBLISHING COMPANY, 1994, pages 143-145. *
SPRUNT B: "Exploring Unused Periodic Time for Aperiodic Services Using The Extended Priority Exchange Algorithm", IEEE ONDISC, pages 251 - 258 *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1164483A3 (fr) * 2000-06-14 2006-01-25 Siemens Aktiengesellschaft Système et méthode pour réduire la gigue dans un signal
WO2002001348A3 (fr) * 2000-06-28 2003-05-22 Intel Corp Procede et dispositif pour exploitation en temps reel dans un systeme d'ordinateur personnel
US7165134B1 (en) 2000-06-28 2007-01-16 Intel Corporation System for selectively generating real-time interrupts and selectively processing associated data when it has higher priority than currently executing non-real-time operation
US8719836B2 (en) 2003-10-16 2014-05-06 Kuka Laboratories Gmbh Method and device for operating a secondary operating system auxiliary to a primary operating system
EP1574940A3 (fr) * 2004-03-11 2008-11-26 Samsung Electronics Co., Ltd. Appareil de gestion de données et procédé pour une mémoire flash.
GB2423843A (en) * 2005-03-02 2006-09-06 Symbian Software Ltd Providing real time performance with memory paging by providing a real time and a non-real time version of the operating system.
GB2423843B (en) * 2005-03-02 2009-04-22 Symbian Software Ltd Dual mode operating system for a computing device
US8332856B2 (en) 2005-03-02 2012-12-11 Nokia Corporation Dual mode operating system for a computing device

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