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WO1998006031A1 - Procedes et appareil d'addition a virgule flottante - Google Patents

Procedes et appareil d'addition a virgule flottante Download PDF

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Publication number
WO1998006031A1
WO1998006031A1 PCT/RU1996/000209 RU9600209W WO9806031A1 WO 1998006031 A1 WO1998006031 A1 WO 1998006031A1 RU 9600209 W RU9600209 W RU 9600209W WO 9806031 A1 WO9806031 A1 WO 9806031A1
Authority
WO
WIPO (PCT)
Prior art keywords
sep
result
operands
rounding
subunit
Prior art date
Application number
PCT/RU1996/000209
Other languages
English (en)
Inventor
Valery Yakovlevich Gorshtein
Anatoly Ivanovich Grushin
Sergei Rudolfovich Shevtsov
Original Assignee
Valery Yakovlevich Gorshtein
Anatoly Ivanovich Grushin
Sergei Rudolfovich Shevtsov
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Valery Yakovlevich Gorshtein, Anatoly Ivanovich Grushin, Sergei Rudolfovich Shevtsov filed Critical Valery Yakovlevich Gorshtein
Priority to PCT/RU1996/000209 priority Critical patent/WO1998006031A1/fr
Publication of WO1998006031A1 publication Critical patent/WO1998006031A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G06F7/485—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding
    • G06F7/49957—Implementation of IEEE-754 Standard

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)

Abstract

Cette invention concerne une unité d'addition à virgule flottante, laquelle comprend deux sous-unités qui vont chacune effectuer l'addition. L'une des sous-unités (sous-unité d'arrondissement) va arrondir le résultat de l'addition, à l'inverse de l'autre sous-unité (sous-unité de non-arrondissement). Le résultat de la sous-unité d'arrondissement est ensuite sélectionné et considéré comme le résultat de l'addition lorsque l'une des conditions suivantes (R1), (R2) ou (R3) est remplie. En ce qui concerne (R1), l'opération consiste en une addition réelle. En ce qui concerne (R2), l'opération consiste en une soustraction réelle, étant entendu que la magnitude ED de la différence entre les exposants des opérandes est égale à 1, et qu'aucune normalisation du résultat n'est nécessaire. Enfin, en ce qui concerne (R3), l'opération consiste en une soustraction réelle et ED > 1. Dans les autres cas, le résultat de l'addition est choisi à partir de la sous-unité de non-arrondissement. Dans certains modes de réalisation, la sous-unité d'arrondissement va chevaucher l'arrondissement en ajoutant les significandes des opérandes. Enfin, dans certains modes de réalisation, l'unité d'addition correspond aux normes ANSI/IEEE 754-1985.
PCT/RU1996/000209 1996-08-05 1996-08-05 Procedes et appareil d'addition a virgule flottante WO1998006031A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/RU1996/000209 WO1998006031A1 (fr) 1996-08-05 1996-08-05 Procedes et appareil d'addition a virgule flottante

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/RU1996/000209 WO1998006031A1 (fr) 1996-08-05 1996-08-05 Procedes et appareil d'addition a virgule flottante

Publications (1)

Publication Number Publication Date
WO1998006031A1 true WO1998006031A1 (fr) 1998-02-12

Family

ID=20130019

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/RU1996/000209 WO1998006031A1 (fr) 1996-08-05 1996-08-05 Procedes et appareil d'addition a virgule flottante

Country Status (1)

Country Link
WO (1) WO1998006031A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008510229A (ja) * 2004-08-13 2008-04-03 アナログ・デバイセズ・インコーポレイテッド 効率的浮動小数点式ａｌｕのための方法及び装置
GB2492173A (en) * 2011-06-29 2012-12-26 Advanced Risc Mach Ltd Generating a sticky bit for a floating point adder by appending the difference between the exponents and a trailing zero count to the mantissas to be added

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2941594A1 (de) * 1978-10-18 1980-04-30 Honeywell Inc Gleitkomma-verarbeitungseinheit
SU763892A1 (ru) * 1978-05-03 1980-09-15 Киевский Ордена Трудового Красного Знамени Завод Вычислительных И Управляющих Машин Арифметическое устройство
SU809169A1 (ru) * 1978-05-03 1981-02-28 Киевский Ордена Трудового Красногознамени Завод Вычислительных И Управ-Ляющих Машин Арифметическое устройство
SU1259248A1 (ru) * 1985-03-21 1986-09-23 Предприятие П/Я М-5769 Арифметическое устройство с плавающей точкой
US4839846A (en) * 1985-03-18 1989-06-13 Hitachi, Ltd. Apparatus for performing floating point arithmetic operations and rounding the result thereof
US5136536A (en) * 1990-05-04 1992-08-04 Weitek Corporation Floating-point ALU with parallel paths
FR2689989A1 (fr) * 1992-03-31 1993-10-15 Intel Corp Calcul parallèle d'un bit adhérent et de produits partiels dans une unité multiplicatrice à virgule flottante.

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU763892A1 (ru) * 1978-05-03 1980-09-15 Киевский Ордена Трудового Красного Знамени Завод Вычислительных И Управляющих Машин Арифметическое устройство
SU809169A1 (ru) * 1978-05-03 1981-02-28 Киевский Ордена Трудового Красногознамени Завод Вычислительных И Управ-Ляющих Машин Арифметическое устройство
DE2941594A1 (de) * 1978-10-18 1980-04-30 Honeywell Inc Gleitkomma-verarbeitungseinheit
US4839846A (en) * 1985-03-18 1989-06-13 Hitachi, Ltd. Apparatus for performing floating point arithmetic operations and rounding the result thereof
SU1259248A1 (ru) * 1985-03-21 1986-09-23 Предприятие П/Я М-5769 Арифметическое устройство с плавающей точкой
US5136536A (en) * 1990-05-04 1992-08-04 Weitek Corporation Floating-point ALU with parallel paths
FR2689989A1 (fr) * 1992-03-31 1993-10-15 Intel Corp Calcul parallèle d'un bit adhérent et de produits partiels dans une unité multiplicatrice à virgule flottante.

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008510229A (ja) * 2004-08-13 2008-04-03 アナログ・デバイセズ・インコーポレイテッド 効率的浮動小数点式ａｌｕのための方法及び装置
EP1782268A4 (fr) * 2004-08-13 2008-11-26 Analog Devices Inc Procede pour unite arithmetique et logique en virgule flottante efficace
US7707236B2 (en) 2004-08-13 2010-04-27 Analog Devices, Inc. Methods and apparatus for an efficient floating point ALU
GB2492173A (en) * 2011-06-29 2012-12-26 Advanced Risc Mach Ltd Generating a sticky bit for a floating point adder by appending the difference between the exponents and a trailing zero count to the mantissas to be added
CN102855117A (zh) * 2011-06-29 2013-01-02 Arm有限公司 浮点加法器
US9009208B2 (en) 2011-06-29 2015-04-14 Arm Limited Floating-point adder
GB2492173B (en) * 2011-06-29 2020-04-22 Advanced Risc Mach Ltd Floating point adder

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