WO1998042010A1 - Bonded soi wafers using high energy implant - Google Patents
Bonded soi wafers using high energy implant Download PDFInfo
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- WO1998042010A1 WO1998042010A1 PCT/US1998/004695 US9804695W WO9842010A1 WO 1998042010 A1 WO1998042010 A1 WO 1998042010A1 US 9804695 W US9804695 W US 9804695W WO 9842010 A1 WO9842010 A1 WO 9842010A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
Definitions
- the present invention relates to Silicon-On-Insulator (SOI) wafers, and to a method of manufacture thereof.
- SOI Silicon-On-Insulator
- Silicon-On-Insulator (SOI) technology is a well-known technology which has been disclosed various publications, such as the article by Subramanian S. Iyer, Thomas 0. Sedgwick, Philip M. Pitner and Manu J. Tejwani entitled "Silicon-on- Insulator Technology - Outlook for Bonded Wafers" appearing at pages 391-407 of J. Electrochem. Soc . , PV 94-10, 1994.
- SOI Silicon-On-Insulator
- the current method starts with a p- wafer 20 such as that shown in Fig. 1.
- a blanket p+ etch stop layer is created in the p- wafer by one of the following two methods.
- a thin p+ epilayer 24 (I0 19 /cm 3 ) is grown on the p- wafer 20.
- a p+ layer 24 is produced on the p- wafer 20 by low energy/high dose boron implantation at less than 100 keV and I0 14 -l0 15 /cm 2 .
- step 2 of the current method shown in Fig.
- a buried p+ layer 24 and high quality SOI surface layer 26 is formed by growing a high quality p-epilayer 26 over the p+ etch stop layer 24 without autodoping and misfit dislocation.
- the present invention provides alternatives to these steps 1 and 2.
- step 3 wafer bonding, shown in Fig. 5
- the wafer 20 with the buried p+ layer 24 is placed in direct contact with a wafer 30 having an SOI insulating layer 32 of Si0 2 , and annealing is performed to provide bonding.
- the wafer 20 with the buried p+ layer 24 may have native oxide at its surface; if not, an oxide can be grown there.
- step 4 shown in Fig. 6, a thin SOI layer 26 is formed by selective chemical etching and polishing the back of the p-wafer 20 to the p+ buried layer 24 and then to the p- SOI layer 26.
- reference numerals 20, 24, 26 and 28 correspond to the "seed wafer" of Figs. 1 and 3 of said U.S. Patent No. 5,103,681; and reference numerals 30 and 32 correspond to the "handle wafer” of Figs. 2 and 3 of said U.S.
- numeral 20 designates a silicon wafer, p- or n- doped
- numeral 22 designates an optional silicon buffer layer
- numeral 24 designates an etch stop layer
- 26 designates a silicon cap layer (wherein the device to be fabricated is formed)
- 28 designates the insulating layer which may be a native oxide or which may be grown.
- Numeral 30 designates the oxide wafer (i.e. the "handle wafer") and numeral 32 designates the SOI insulating layer of Si0 2 _
- p- means a p-type impurity concentration of I0 14 /cm 3 or less; the term “p” means a p-type impurity concentration of between I0 15 /cm 3 and I0 16 /cm 3 ; the term “p+” means a p-type impurity concentration of between I0 17 /cm 3 and I0 18 /cm 3 ; and the term “p++” means a p-type impurity concentration of I0 19 /cm 3 or more.
- the present invention comprehends a new method of forming a p+ buried layer SOI wafer which eliminates the single epi growth of a p- surface layer over a p+ blanket implant according to the second of the aforementioned current methods, and eliminates the double epi growth of a first p+ epilayer and then a p- epilayer according to the first of the aforementioned current methods .
- the present invention achieves a high-quality epi -equivalent bulk Czochralski (Cz) wafer SOI layer by using low oxygen wafer or by optimized denuding (such as with Ar, N 2 , H 2 or 0 2 ) .
- Fig. 1 is a diagrammatic view of a p- wafer used in carrying out the current method
- Fig. 2 is a diagram showing one manner of carrying out step 1 of the current method
- Fig. 3 is a diagram showing another manner of carrying out step 1 of the current method
- Fig. 4 is a diagram showing step 2 of the current method
- Fig. 5 is a diagram showing step 3 of the current method
- Fig. 6 is a diagram showing step 4 of the current method
- Fig. 7 is a diagram showing step 1 of the method ot the present invention.
- Fig. 8 is a diagram showing step 2 of the method of the present invention.
- a high quality top surface region is formed on the p- wafer by denuding the wafer at 1000°C - 1200° C in an ambient of Ar, H 2 , N 2 or 0 2 to deplete the surface of oxygen and microdefects .
- Suitable denuding methods are disclosed, for example, in J.O.Borland, Semiconductor International April 1989 pages 144-148 and May 1989 pages 154- 157 and references cited therein, such as J.O. Borland, J.Electrochem.Soc. , PV 83-9, 1983, p. 194; J.O.Borland, J. Electrochem. Soc .
- a buried p+ etch stop layer is then formed by High Energy (0.2 to 2 MeV) implantation of boron at high dose (10 14 to I0 15 /cm 2 to form a uniform buried p+ layer 0.5 to 3 microns deep with a peak concentration of 10 19 - 10 20 /cm 3 .
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Element Separation (AREA)
Abstract
In the manufacture of SOI substrates for the fabrication of CMOS circuits by the bond and etchback approach, a blanket impurity ion high energy is used to produce the etch-stop layer (24).
Description
"BONDED SOI WAFERS USING HIGH ENERGY IMPLANT"
BACKGROUND OF THE INVENTION
1. Field of the Invention The present invention relates to Silicon-On-Insulator (SOI) wafers, and to a method of manufacture thereof.
2. Description of the Related Art
Silicon-On-Insulator (SOI) technology is a well-known technology which has been disclosed various publications, such as the article by Subramanian S. Iyer, Thomas 0. Sedgwick, Philip M. Pitner and Manu J. Tejwani entitled "Silicon-on- Insulator Technology - Outlook for Bonded Wafers" appearing at pages 391-407 of J. Electrochem. Soc . , PV 94-10, 1994. As stated in that article, research on Silicon-On-Insulator (SOI) wafers has been steadily increasing over the last few years, and the advantages of fabricating CMOS circuits on SOI substrates has been seriously addressed by several development labs worldwide. For the thickness range being considered for digital CMOS applications, there are two main SOI materials approaches that have received serious consideration: These are SIMOX (separation by implantation of Oxygen) and the bonded wafer approach. The bonded wafer approach to SOI using an etch stop was proposed by Lasky et al (J.B. Lasky, Applied Phys . Lett. 48 p 78 (1986) . Since then improvements have been made, and the current method is shown in Figs. 1 through 6 of the accompanying drawings .
Referring to Fig. 1, the current method starts with a p- wafer 20 such as that shown in Fig. 1. In step 1 of the current method, a blanket p+ etch stop layer is created in the p- wafer by one of the following two methods. In the first method, shown in Fig. 2, a thin p+ epilayer 24 (I019/cm3) is grown on the p- wafer 20. In the second, alternative, method, shown in Fig. 3, a p+ layer 24 is produced on the p- wafer 20 by low energy/high dose boron implantation at less than 100 keV and I014-l015/cm2. In step 2 of the current method, shown in Fig. 4, a buried p+ layer 24 and high quality SOI surface layer 26 is formed by
growing a high quality p-epilayer 26 over the p+ etch stop layer 24 without autodoping and misfit dislocation. The present invention provides alternatives to these steps 1 and 2.
The current method then proceeds with further steps which provide bonding to an oxide wafer and which are also used in the present invention. In step 3 (wafer bonding, shown in Fig. 5) the wafer 20 with the buried p+ layer 24 is placed in direct contact with a wafer 30 having an SOI insulating layer 32 of Si02, and annealing is performed to provide bonding. The wafer 20 with the buried p+ layer 24 may have native oxide at its surface; if not, an oxide can be grown there. In step 4, shown in Fig. 6, a thin SOI layer 26 is formed by selective chemical etching and polishing the back of the p-wafer 20 to the p+ buried layer 24 and then to the p- SOI layer 26. Various examples of current methods are disclosed in the aforementioned article by Iyer et al . , the disclosure of which is hereby incorporated herein by this reference thereto. One such example is disclosed in U.S. Patent No. 5,013,681 to Godbey et al . , the disclosure of which is hereby incorporated herein by this reference thereto. Said U.S. Patent No. 5,013,681 discloses a representative sequence of steps making use of an etch-stop layer. The primary object of the instant invention is to provide a new and improved method of forming an etch-stop layer of this nature. In the foregoing description of Figs. 1-6 of the instant application, reference numerals correspond to those of said U.S. Patent No. 5,103,681. Thus, reference numerals 20, 24, 26 and 28 correspond to the "seed wafer" of Figs. 1 and 3 of said U.S. Patent No. 5,103,681; and reference numerals 30 and 32 correspond to the "handle wafer" of Figs. 2 and 3 of said U.S.
Patent No. 5,103,681. In particular, numeral 20 designates a silicon wafer, p- or n- doped, numeral 22 designates an optional silicon buffer layer, numeral 24 designates an etch stop layer
(the improved method of formation of which is the subject of the present invention) , 26 designates a silicon cap layer (wherein the device to be fabricated is formed) , and 28 designates the insulating layer which may be a native oxide or which may be
grown. Numeral 30 designates the oxide wafer (i.e. the "handle wafer") and numeral 32 designates the SOI insulating layer of Si02_
Throughout this specification and claims, the term "p-" means a p-type impurity concentration of I014/cm3 or less; the term "p" means a p-type impurity concentration of between I015/cm3 and I016/cm3; the term "p+" means a p-type impurity concentration of between I017/cm3 and I018/cm3; and the term "p++" means a p-type impurity concentration of I019/cm3 or more.
SUMMARY OF THE INVENTION
The present invention comprehends a new method of forming a p+ buried layer SOI wafer which eliminates the single epi growth of a p- surface layer over a p+ blanket implant according to the second of the aforementioned current methods, and eliminates the double epi growth of a first p+ epilayer and then a p- epilayer according to the first of the aforementioned current methods .
In addition, the present invention achieves a high-quality epi -equivalent bulk Czochralski (Cz) wafer SOI layer by using low oxygen wafer or by optimized denuding (such as with Ar, N2, H2 or 02) .
BRIEF DESCRIPTION OF THE DRAWINGS
The invention may best be understood from the following detailed description thereof, having reference to the accompanying drawings, in which:
Fig. 1 is a diagrammatic view of a p- wafer used in carrying out the current method
Fig. 2 is a diagram showing one manner of carrying out step 1 of the current method; Fig. 3 is a diagram showing another manner of carrying out step 1 of the current method;
Fig. 4 is a diagram showing step 2 of the current method;
Fig. 5 is a diagram showing step 3 of the current method;
Fig. 6 is a diagram showing step 4 of the current method;
Fig. 7 is a diagram showing step 1 of the method ot the present invention; and
Fig. 8 is a diagram showing step 2 of the method of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to the drawings, and first to Fig. 7 thereof, in accordance with the present invention a high quality top surface region is formed on the p- wafer by denuding the wafer at 1000°C - 1200° C in an ambient of Ar, H2, N2 or 02 to deplete the surface of oxygen and microdefects . Suitable denuding methods are disclosed, for example, in J.O.Borland, Semiconductor International April 1989 pages 144-148 and May 1989 pages 154- 157 and references cited therein, such as J.O. Borland, J.Electrochem.Soc. , PV 83-9, 1983, p. 194; J.O.Borland, J. Electrochem. Soc . , PV 83-9, 1983, p.236; and J.O.Borland and T. Deacon, Solid State Technology, Aug. 1984, p.123; and in U.S. Patent No. 4,548,654 to Tobin. If the oxygen level in the p- wafer is low enough, this step may be omitted. As shown in Fig. 8, a buried p+ etch stop layer is then formed by High Energy (0.2 to 2 MeV) implantation of boron at high dose (1014 to I015/cm2 to form a uniform buried p+ layer 0.5 to 3 microns deep with a peak concentration of 1019 - 1020/cm3. Ion implantation at MeV energies is well known and disclosed in various publications, such as the article by the present inventor and Ron Koelsch entitled "MeV implantation technology: Next- generation manufacturing with current -generation equipment" appearing at pages 1-8 of the December 1993 issue of "Solid State Technology" , the disclosure of which is hereby incorporated herein by this reference thereto. Thereafter, steps 3 and 4 of the current method, as described hereinabove with reference to Figs. 5 and 6, are carried out .
In the foregoing description, the carrying out of the invention by means of buried layer implantation of boron has been described, and this is a preferred embodiment of the invention. However, the invention is not limited to the use of
boron, but includes buried layer implantation ot otner p-type materials, and even n-type materials, as well a species such as hydrogen, helium, argon and other suitable buried layer implant species . Having thus described the principles of the invention, together with several illustrative embodiments thereof, it is to be understood that, although specific terms are employed, they are used in a generic and descriptive sense, and not for purposes of limitation, the scope of the invention being set forth in the following claims: I claim:
Claims
1. Method of manufacturing an SOI wafer, which method comprises the following steps: forming a buried etch stop layer in a low-oxygen wafer having a front and a back by implanting impurity ions in the front of said wafer at an energy of 0.2 to 2 MeV at a dose of
1014 to I015/cm2 to form a uniform buried etch stop layer 0.5 to
3 microns deep with a peak concentration of 1019 to 1020/cm3, placing said front of said wafer having said buried etch stop layer in direct contact with an oxide surface of an oxide wafer and annealing to cause bonding between the surfaces thus contacted, and selectively chemically etching and polishing said back of said wafer to said etch stop layer and then to the low-oxygen SOI layer.
2. Method in accordance with claim 1, wherein said low- oxygen wafer is (p-) -type, wherein said etch stop layer is (p+) - type, and wherein said impurity ions are p-type.
3. Method in accordance with claim 2, wherein said impurity ions are boron ions.
4. Method in accordance with claim 1, wherein said low- oxygen wafer is (n-) -type, wherein said etch stop layer is (n+) - type, and wherein said impurity ions are n-type.
5. Method in accordance with claim 3, wherein, prior to said implantation step, a high quality top surface region is formed on said front of said p- wafer by denuding said front at 1000° - 1200° C in ambients of Ar, H2, N2 or 02 to deplete said surface region of oxygen and microdefects .
6. Method of manufacturing a silicon member suitable for bonding to an oxide member in the bonded-wafer manufacture of
SOI material, which method comprises the following step: forming a buried etch stop layer in a low-oxygen wafer having a front and a back by implanting impurity ions in the front of said wafer at an energy of 0.2 to 2 MeV at a dose of 1014 to 1015/cm2 to form a uniform buried etch stop layer 0.5 to
3 microns deep with a peak concentration of 1019 to 100/cm3.
7. Method in accordance with claim 6, wherein saiα ow- oxygen wafer is (p-)-type, wherein said etch stop layer is (p+) - type, and wherein said impurity ions are p-type.
8. Method in accordance with claim 7, wherein said impurity ions are boron ions .
9. Method in accordance with claim 6, wherein said low- oxygen wafer is (n-) -type, wherein said etch stop layer is (n+) - type, and wherein said impurity ions are n-type.
10. Method in accordance with claim 8, wherein, prior to said implantation step, a high quality top surface region is formed on said front of said p- wafer by denuding said front at 1000° - 1200° C in ambients of Ar, H2, N2 or 02 to deplete said surface region of oxygen and microdefects.
11. Method in accordance with claim 3, wherein said front of said p- wafer has native oxide formed thereon.
12. Method in accordance with claim 3, wherein, prior to placement in direct contact with said oxide surface, oxide is grown or deposited on said front .
13. Method in accordance with claim 8, wherein said front of said p- wafer has native oxide formed thereon.
14. Method in accordance with claim 8, wherein oxide is grown or deposited on said front .
15. A p- wafer suitable for formation of a SOI wafer by annealing a surface thereof to a silicon oxide layer, comprising a p- wafer having an etch-stop below and spaced from said surface, said etch-stop being formed by high energy ion implantation .
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US81892097A | 1997-03-17 | 1997-03-17 | |
| US08/818,920 | 1997-03-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO1998042010A1 true WO1998042010A1 (en) | 1998-09-24 |
Family
ID=25226756
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US1998/004695 Ceased WO1998042010A1 (en) | 1997-03-17 | 1998-03-11 | Bonded soi wafers using high energy implant |
Country Status (1)
| Country | Link |
|---|---|
| WO (1) | WO1998042010A1 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2163410C1 (en) * | 1999-07-21 | 2001-02-20 | Физико-технический институт им. А.Ф. Иоффе РАН | Silicon structure manufacturing process |
| RU2164719C1 (en) * | 1999-09-28 | 2001-03-27 | Институт физики полупроводников СО РАН | Method for manufacturing silicon-on-insulator structure |
| WO2004010505A1 (en) * | 2002-07-18 | 2004-01-29 | Shin-Etsu Handotai Co.,Ltd. | Soi wafer and production method therefor |
| WO2007012290A1 (en) * | 2005-07-29 | 2007-02-01 | Shanghai Simgui Technology Co., Ltd | Method for manufacturing silicon on insulator |
| US8080482B2 (en) | 2006-01-31 | 2011-12-20 | Memc Electronic Materials, Inc. | Methods for preparing a semiconductor structure for use in backside illumination applications |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4548654A (en) * | 1983-06-03 | 1985-10-22 | Motorola, Inc. | Surface denuding of silicon wafer |
| US4666532A (en) * | 1984-05-04 | 1987-05-19 | Monsanto Company | Denuding silicon substrates with oxygen and halogen |
| JPH01226167A (en) * | 1988-03-07 | 1989-09-08 | Seiko Epson Corp | Method for manufacturing semiconductor device substrate |
| US4897362A (en) * | 1987-09-02 | 1990-01-30 | Harris Corporation | Double epitaxial method of fabricating semiconductor devices on bonded wafers |
| US5013681A (en) * | 1989-09-29 | 1991-05-07 | The United States Of America As Represented By The Secretary Of The Navy | Method of producing a thin silicon-on-insulator layer |
| US5147808A (en) * | 1988-11-02 | 1992-09-15 | Universal Energy Systems, Inc. | High energy ion implanted silicon on insulator structure |
| US5234535A (en) * | 1992-12-10 | 1993-08-10 | International Business Machines Corporation | Method of producing a thin silicon-on-insulator layer |
| US5462883A (en) * | 1991-06-28 | 1995-10-31 | International Business Machines Corporation | Method of fabricating defect-free silicon on an insulating substrate |
-
1998
- 1998-03-11 WO PCT/US1998/004695 patent/WO1998042010A1/en not_active Ceased
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4548654A (en) * | 1983-06-03 | 1985-10-22 | Motorola, Inc. | Surface denuding of silicon wafer |
| US4666532A (en) * | 1984-05-04 | 1987-05-19 | Monsanto Company | Denuding silicon substrates with oxygen and halogen |
| US4897362A (en) * | 1987-09-02 | 1990-01-30 | Harris Corporation | Double epitaxial method of fabricating semiconductor devices on bonded wafers |
| JPH01226167A (en) * | 1988-03-07 | 1989-09-08 | Seiko Epson Corp | Method for manufacturing semiconductor device substrate |
| US5147808A (en) * | 1988-11-02 | 1992-09-15 | Universal Energy Systems, Inc. | High energy ion implanted silicon on insulator structure |
| US5013681A (en) * | 1989-09-29 | 1991-05-07 | The United States Of America As Represented By The Secretary Of The Navy | Method of producing a thin silicon-on-insulator layer |
| US5462883A (en) * | 1991-06-28 | 1995-10-31 | International Business Machines Corporation | Method of fabricating defect-free silicon on an insulating substrate |
| US5234535A (en) * | 1992-12-10 | 1993-08-10 | International Business Machines Corporation | Method of producing a thin silicon-on-insulator layer |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2163410C1 (en) * | 1999-07-21 | 2001-02-20 | Физико-технический институт им. А.Ф. Иоффе РАН | Silicon structure manufacturing process |
| RU2164719C1 (en) * | 1999-09-28 | 2001-03-27 | Институт физики полупроводников СО РАН | Method for manufacturing silicon-on-insulator structure |
| WO2004010505A1 (en) * | 2002-07-18 | 2004-01-29 | Shin-Etsu Handotai Co.,Ltd. | Soi wafer and production method therefor |
| WO2007012290A1 (en) * | 2005-07-29 | 2007-02-01 | Shanghai Simgui Technology Co., Ltd | Method for manufacturing silicon on insulator |
| US8080482B2 (en) | 2006-01-31 | 2011-12-20 | Memc Electronic Materials, Inc. | Methods for preparing a semiconductor structure for use in backside illumination applications |
| US8865601B2 (en) | 2006-01-31 | 2014-10-21 | Sunedison Semiconductor Limited (Uen201334164H) | Methods for preparing a semiconductor wafer with high thermal conductivity |
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