[go: up one dir, main page]

WO1997023035A1 - Melangeur a transistor a effet de champ en transmission passive a triple equilibrage - Google Patents

Melangeur a transistor a effet de champ en transmission passive a triple equilibrage Download PDF

Info

Publication number
WO1997023035A1
WO1997023035A1 PCT/US1996/019964 US9619964W WO9723035A1 WO 1997023035 A1 WO1997023035 A1 WO 1997023035A1 US 9619964 W US9619964 W US 9619964W WO 9723035 A1 WO9723035 A1 WO 9723035A1
Authority
WO
WIPO (PCT)
Prior art keywords
balun
fet
terminal
mixer
source
Prior art date
Application number
PCT/US1996/019964
Other languages
English (en)
Other versions
WO1997023035B1 (fr
Inventor
Michael W. Vice
Original Assignee
Watkins-Johnson Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Watkins-Johnson Company filed Critical Watkins-Johnson Company
Priority to AU12916/97A priority Critical patent/AU1291697A/en
Publication of WO1997023035A1 publication Critical patent/WO1997023035A1/fr
Publication of WO1997023035B1 publication Critical patent/WO1997023035B1/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D9/00—Demodulation or transference of modulation of modulated electromagnetic waves
    • H03D9/06—Transference of modulation using distributed inductance and capacitance
    • H03D9/0658—Transference of modulation using distributed inductance and capacitance by means of semiconductor devices having more than two electrodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0001—Circuit elements of demodulators
    • H03D2200/0023—Balun circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041—Functional aspects of demodulators
    • H03D2200/0043—Bias and operating point
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041—Functional aspects of demodulators
    • H03D2200/0066—Mixing
    • H03D2200/0074—Mixing using a resistive mixer or a passive mixer
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041—Functional aspects of demodulators
    • H03D2200/0088—Reduction of intermodulation, nonlinearities, adjacent channel interference; intercept points of harmonics or intermodulation products
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/12—Transference of modulation from one carrier to another, e.g. frequency-changing by means of semiconductor devices having more than two electrodes
    • H03D7/125—Transference of modulation from one carrier to another, e.g. frequency-changing by means of semiconductor devices having more than two electrodes with field effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements

Definitions

  • the invention relates generally to radio frequency communication devices and more specifically to passive transmission FET mixers requiring relatively low local oscillator power levels and having excellent isolation of the local oscillator signal relative to the radio and intermediate frequency signals.
  • the Siliconix Si8901-DBM is a monolithic quad-MOSFET ring demodulator/mixer that is reported to achieve third-order intercepts exceeding + 37 Dbm and 2-Db signal overload compression and desensitization of +30 Dbm at a LO drive level of + 17 Dbm (50 W).
  • the Si8901 commutation-mixer relies on the switching action of the quad- MOSFET elements to effect a mixing action.
  • the MOSFETs act, essentially, as a pair of switches reversing the phase of a signal at a rate determined by the LO frequency.
  • the MOSFETs exhibit a finite on-resistance that is expressed as a conversion efficiency loss. The loss results from the r ⁇ of the MOSFETs relative to both the signal and IF impedances and signal conversion to unwanted frequencies.
  • the present invention comprises a triple balanced passive transmission FET mixer that operates in the LO/RFTF frequency range of from 10 Mhz to 1000 Mhz with reduced levels of nonlinearity and intermodulation distortion as the result of the topological structure and the application of a dc bias to FET channels used for mixing which is useful for both up- and down-frequency conversion of RF and IF signal frequencies.
  • the RF and IF signal frequencies may overlap. It is therefore a feature of the present invention to produce a radio frequency mixer that has a wide dynamic range of operation and low overall signal distortion including low intermodulation distortion and partial cancellation of nonlinearity distortion imposed on the radio frequency signal.
  • FIG. 1 is a block diagram of an embodiment of the triple balanced mixer of the present invention.
  • FIG. 2 is a schematic diagram of a preferred embodiment of the triple balanced mixer of the present invention.
  • FIG. 3 is a schematic of a pair of back-to-back FETs used as a model to explain how the present invention reduces intermodulation distortion in the preferred embodiment.
  • FIG. 4 is a schematic diagram of wavefront propagation in a transmission line.
  • FIG. 5 is a schematic diagram of the embodiment of the invention in FIG. 2 showing the flow of current (neglecting phase shift in the transmission lines) in the RF and LF baluns of the mixer when FETs Ql and Q2 are conducting (ON) and FETS Q3 and Q4 are not conducting (OFF) for an applied RF input signal.
  • FIG. 6 is a schematic diagram of the embodiment of the invention in FIG. 2 showing the flow of current (neglecting phase shift in the transmission lines) in the RF and LF baluns in the mixer when FETs Ql and Q2 are not conduction (OFF) but FETS Q3 and Q4 are conducting (ON) for an applied RF input signal.
  • FIG. 7 is a schematic diagram of the embodiment of the invention in FIG. 2 showing the flow of current (neglecting phase shift in the transmission lines) in the RF and LF baluns of the mixer when FETs Ql and Q2 are conducting (ON) and FETS Q3 and Q4 are not conducting (OFF) for an applied IF input signal.
  • FIG. 8 is a schematic diagram of the embodiment of the invention in FIG. 2 showing the flow of current (neglecting phase shift in the transmission lines) in the RF and LF baluns in the mixer when FETs Ql and Q2 are not conduction (OFF) but FETS Q3 and Q4 are conducting (ON) for an applied IF input signal.
  • FIGs. 9 and 10 are schematic diagrams that illustrate the manner in which amplified LO signals of the FET drains are isolated from the RF-port and IF-port.
  • FIG. 1 illustrates an embodiment of the triple-balanced mixer 10 of the present invention.
  • Mixer 10 comprises a balanced local oscillator (LO) circuit 11 , first and second switching circuits 12 and 13 coupled to local oscillator input circuit 11 , a switching circuit control circuit 14 ( a bias circuit in the preferred embodiment) coupled to and provided for controlling the switching operation of switching circuits 12, 13, a radio frequency (RF) to intermediate frequency (IF) coupling circuit 16 connected to the switching circuits 12 and 13.
  • LO local oscillator
  • RF radio frequency
  • IF intermediate frequency
  • a two-terminal local oscillator input port 19 having a pin te ⁇ riinal 20 and a ground terminal 21 is provided for coupling an external local oscillator (LO) signal source 22 to the local oscillator circuit 11 via a LO input filter circuit 23.
  • a two-terminal radio frequency (RF) port 24 having a pin terminal 25 and a ground terminal 26 is provided for coupling an external radio frequency signal sink (or source) 27 to the RF-to-LF coupling circuit 16, and a two-terminal intermediate frequency (IF) port 28 having a pin terminal 29 and a ground terminal 30 is provided for coupling an external intermediate frequency signal source (or sink) 31 to the RF-to-IF coupling circuit 16.
  • Control circuit 14 may optionally be provided with a control circuit input port 32 for coupling the circuit to externally generated signals. For example, in one embodiment of the invention a bias voltage generated by an external bias voltage source 33 is applied to the mixer circuit 10 at input port 32.
  • Mixer 10 may be operated as either an up-frequency converter in which case the input signal is applied at the intermediate frequency (IF) port 29 and the output signal is extracted at the radio frequency (RF) port 24, or as a down-frequency converter in which case the input signal is applied at the RF port 24 and the output signal is extracted at the LF port 28.
  • IF intermediate frequency
  • RF radio frequency
  • the RF and IF ports may be used as stated, or reversed roles, with only minor changes in performance.
  • the RF input signal When operated as a frequency down conversion circuit, the RF input signal is applied at the RF port 24 and coupled to the switching circuits 12, 13 via RF-to-IF coupling circuit 16.
  • the LO signal is applied at LO port 19 and coupled to switching circuits 12, 13 in phase complementary manner so that switch 12 is on when switch 13 is off and vice versa.
  • the switches operate at the frequency of the LO input signal, and the rapid transition from a low impedance (ON) to a high impedance (OFF) results in a mixing action between the LO and RF signals within the switch.
  • Control circuit 14 provides an optional control signal for influencing operation of the switching devices 12, 13.
  • Each of the switching circuits 12, 13 are fabricated in such a manner that temporal changes in admittance in each switch (implemented by FETs in one embodiment) resulting from application of the RF signal approximately cancel, thereby reducing intermodulation distortion RF-to-IF.
  • Coupling network 16 is fabricated such that good LO-to-IF, LO-to-IF, and RF-to-IF isolation are realized.
  • FIG. 2 is an illustration of a preferred embodiment of the triple-balanced mixer 10 shown in functional block diagram form in FIG. 1.
  • switching devices 12, 13 are realized with a first pair (Ql and Q2) 38 and a second pair (Q3 and Q4) 39 of interconnected field-effect transistors (FETs), each FET having a control or gate (G) terminal, as well as drain (D) and source (S) terminals.
  • the source terminal of Ql is connected to the source terminal of Q2, and the source terminal of Q3 is connected to the source terminal of Q4.
  • the FET-pair switching devices 38, 39 are responsible for mixing the local oscillator (LO) signal coupled to the FET switch by the LO input circuit 11 with the radio frequency (RF) signal coupled to the FET switches by the RF-to-IF coupling circuit 16 to generate an intermediate frequency (IF) signal. Because these FET-pairs are at the heart of the signal mixing action and couple to the LO, RF, and LF functional components of the mixer circuit, the structure and operation of mixer 10 are described relative to the FET-pairs 38, 39.
  • LO local oscillator
  • RF radio frequency
  • the mixer operates over a LO/RF frequency range of about 1700 MHz to about 2200 MHz, and nominally operates with a LO drive signal of about +21 dBm and a -5 Volt bias voltage.
  • the gate terminals are self biasing at about -2 volts.
  • the circuit is typically useful over the RF bandwidth range of from about 1700 MHZ to about 2200 MHZ, an IF bandwidth of from about 10 MHZ to about 200 MHZ, and LO drives of from about 1700 MHZ to about 2200 MHz; however, in principle there are no absolute frequency limits to the circuit's applicability.
  • FET pair Q1-Q2 38 provides a single switching operation between circuit nodes 40 and 41.
  • combined FET-pair Q3-Q4 provides a single switching operation between circuit nodes 42 and 43.
  • Each node 40, 41 , 42, and 43 corresponds to a drain terminal of one of the FETs.
  • the RF signals When operating as a frequency down-converter where an externally generated RF signal is applied to the RF port, the RF signals are forced to pass through both FETs (Ql and Q2) of FET-pair 38 in such a way that the RF signal enters the drain of one FET (Ql) emerges from the source terminal of the same FET (Ql), then enters the source terminal of the second FET (Q2) and emerges from the drain of the second FET (Q2).
  • propagation of the RF signal through the first FET (Ql) may perturb the admittance of the FET with the resulting effect on the output signal, but for FETs (Ql and Q2) of comparable construction, propagation through the second FET (Q2) has an opposite perturbing effect on the admittance of Q2 as compared to the effect on Ql.
  • the same local oscillator signal pumps (switches) both FETs in the FET pair.
  • the net effect of propagation of the signal through both serially connected (source-to-source) FETs Ql and Q2 is cancellation of some of the distortion, including an appreciable amount of intermodulation distortion. The theoretical basis for this distortion cancellation is now described.
  • the serially connected FET-pair structure and application of drain bias to the channels of the FET transistors provide structure and method for significantly reducing the intermodulation distortion in the mixer output signal.
  • the manner in which the each pair of back- to-back FETs reduce distortion is now described with reference to FIG. 3, which shows a pair of serially connected FETs (e.g. Q1-Q2 or Q3-Q4).
  • the gate-to- source voltage (VQ S ) is equal to the sum of the gate-to-drain voltage (V GD ) and the drain- to-source voltage (Vus).
  • V Q S V GD + V DS
  • the change in resistance between the two FET drains is equal to the change of resistance between the source and drain of the first FET Ql ( ⁇ R D1S1 ) and the change of resistance between the source and drain of the second FET Q2 ( ⁇ R D2S2 ).
  • V D]D2 the voltage V D]D2 is symmetrically dropped across both FETS Ql and Q2, so that:
  • V D ⁇ s ⁇ " V D2S2 (approximately).
  • the small signal shown in FIG. 3 passes through the FET channel combination Ql and Q2 without controlling the resistance of the FET channel combination.
  • This condition is equivalent to infinite intermodulation suppression and helps reduce intermodulation distortion in mixer 10.
  • Infinite intermodulation suppression is achieved only if the approximations assumed here hold, that is for an ideal system. In an actual physical circuit, the approximations do not hold exactly, and intermodulation is suppressed by some finite amount.
  • a comparable derivation showing that the change in resistance between the FET pair Q3-Q4 drain terminals is zero may be made for FET-pair Q3-Q4.
  • the triple balanced nature of the mixer also reduces mixer distortion.
  • each FET is in transition from "ON" to "OFF" (Q1-Q2 midway from on to off, or Q3-Q4 midway from off to on, for example) the FET transistors are producing nearly maximum distortion.
  • the symmetrical structure of Ql and Q2 relative to the structure of Q3 and Q4 advantageously results in partial cancellation of the distortion produced by Ql and Q2 with that distortion produced by Q3 and Q4.
  • the cancellation only obtains for a short period of time, but since cancellation occurs during a period of maximum distortion, and is recursive with respect to every cycle of the LO signal, such cancellation can be significant relative to overall mixer operation.
  • the FETs operate with a gate bias voltage V g applied by gate bias circuit 44 between the gate and source terminals and a drain bias voltage V d applied by drain bias circuit 45 between the drain and source terminals.
  • the drain bias voltage V d acting as a switch control signal source 33 is generated by an external drain bias voltage source 46, while the gate terminals of the FETs are self biased as described hereinafter.
  • a dc drain bias voltage is generated by dc drain bias circuit 45 and applied to the channels of the mixing FETs (Ql , Q2, Q3, and Q4) at each FET source terminal. This drain bias voltage to the FET pairs significantly reduces intermodulation distortion in the output signal as described.
  • Drain bias circuit 45 is connected to an external dc bias voltage source 46 at drain bias port 47.
  • Scaling resistor Rl 94 (50 ohm) serves to scale the bias voltage that appears at the source terminal of each FET transistor (Ql, Q2, Q3, and Q4), and to limit the bias current through each FET.
  • Optional diode Dl 95 provides reverse bias protection.
  • Capacitor Cl 96 provides ac isolation of the bias port 47 from the other mixer components.
  • the bias voltage is coupled to the FET source terminals through resistors R4 97 and R5 98, which provide an appropriate impedance for the bias current into each FET pair.
  • resistors R4 and R5 are selected at about 25 ohms each to provide the desired impedance.
  • the drain bias circuit 45 also comprises RF transmission line balun (T2A, T2B) 73, 76 and IF transmission line balun (T3A, T3B) 80, 81 which provide a dc return path to ground for the drain bias current.
  • drain bias current flows from the point of application at the Ql source terminal, through FET Ql, out the drain terminal of Ql , and then through LF balun T3A 80 to the ground terminal 79 at LF port 77.
  • drain bias to the FET causes the FET to function as a LO signal amplifier.
  • a drain bias voltage is applied to the FET source terminals, and the LO signal is applied to the connected gate terminals of the two paired FETs, a LO response signal appearing much like an amplified version of the gate LO signal is generated within the FET structure and appears at each conducting FET drain terminal.
  • the appearance of this drain LO response signal enhances the switching behavior of the FET.
  • the applied LO signal and the response LO signal generated within the FET junction work together in a compound fashion so that, in essence, each FET sees a larger LO driving signal than the LO signal applied at the gate alone. Therefore, the FET switches operate with a lower externally applied LO signal.
  • Gate bias voltage provided by Gate bias circuit 44 is generated for FET pair 38 (Q1-Q2) by coupling capacitor C2 58, which functions as a dc current blocking capacitor, between the first LO input circuit 11 output port and joined FET-pair Ql and Q2 gate terminals.
  • FET pair 38 is pumped by balanced LO circuit 11 comprising first transmission line balun T1A (TlAl and T1A2) 51 and second transmission line balun TIB (T1B1 and T1B2) 54, first and second termination resistors R2 56 and R3 57, and dc blocking capacitors C2 58 and C3 59.
  • Each of FET Ql and Q2 attains to a self bias level by the charging of capacitor C2 during Q2, Q2 forward gate conduction.
  • gate bias voltage is generated for FET pair 39 (Q3-Q4) by coupling the second LO input circuit 11 output port with capacitor C3 59 to FET pair 39 (Q3-Q4) gate terminals.
  • Eliminating an explicit bias source for the gate is advantageous because such implementation reduces cost by eliminating some components, and eliminates the inconvenience of having to provide the separate bias source.
  • provision of self-biasing circuitry does not preclude application of a separate external gate bias if additional flexibility is desired for tuning the behavior of the mixer circuit 10.
  • resistor Rl 94 is 50 ohms
  • resistors R4 97 and R5 98 are each 25 ohms
  • resistors R256 and R3 57 are each 100 ohms
  • capacitor Cl 96 is 10K picofarad (pF)
  • capacitors C2 and C3 are each 50 pF
  • optional diode Dl 95 is a silicon junction diode, the gate terminals of FETs Ql, Q2, Q3, and Q4 self-bias at about -2 volts relative to their source terminals.
  • Nominal circuit component values for the exemplary mixer 10 are indicated parenthetically after the component name.
  • the two inputs of the balanced LO drive circuits 11 are coupled to external LO source 22 at the LO port 19 through dc blocking capacitors C4 61 and C5 62.
  • the outputs of the two balanced local oscillator drive circuits are connected to the FET pairs 38, 39 in a phase complementary fashion so that Ql and Q2 are driven 180-degrees out of phase relative to Q3 and Q4. That is, the local oscillator source input connected to pin terminal 20 of the two-terminal LO input port 19 is coupled to the gates of Ql and Q2 but to the source terminals of Q3 and Q4. And the local oscillator source input connected to the ground terminal 21 of the two-terminal LO input port 19 is coupled to the gate terminals of Q3 and Q4, but to the source terminals of Ql and Q2.
  • inductor Ll 47 (3 nanoHenry (nH)) is connected in serial with inductor L2 48 (3 nH), and the serial combination is connected in parallel with transmission line balun T1A 51 termination resistor R2 56 (100 ohm).
  • Capacitor C649 (0.5 pF) is connected between the node common to serially connected inductors Ll and L2 and ground.
  • inductor L3 50 (3 nH) is connected in serial with inductor L4 52 (3 nH), and the serial combination is connected in parallel with transmission line balun TIB 54 termination resistor R3 57 (100 ohm).
  • Capacitor C7 53 (0.5 pF) is connected between the node common to serially connected inductors L3 and L4 and ground.
  • Pin terminal 71 and ground terminal 72 of RF input port 70 are coupled to the mixer switching devices 38 and 39 (Q1-Q2 and Q3-Q4) via RF balun T2A (T2A1 and T2A2) 73 and T2B (T2B1 and T2B2) 76.
  • Pin and ground terminals 78, 79 of IF input port 77 are coupled to the mixer switching devices 38 and 39 (Q1-Q2 and Q3-Q4) via IF balun T3A (T3A1 and T3A2) and T3B (T3B1 and T3B2) 80, 81.
  • the RF balun comprises two transformers 73, 76 and IF balun comprises two transformers 80, 81.
  • each LO balun, RF balun, and IF balun comprises a pair of 100 ohm transmission line bifilar wires.
  • T2A is a 100 ohm bifilar wire
  • T2B is a 100 ohm bifilar wire.
  • the RF balun (73, 76) and IF balun (80, 81) are wired to each other in such a fashion that during frequency down-conversion (for example), and in conjunction with a LO signal applied to switching devices 38, 39 and the action of the switching devices, RF input energy flows unidirectionally from the RF port 70 (source) to IF port 77 (sink).
  • Each of the two RF transmission line transformers 73, 76 making up the RF balun and the two LF transmission line transformers 80, 81 making up the IF balun participate in the conveyance of energy during each and every LO signal half cycle as described in great detail hereinafter.
  • input energy from the LF port acting as the (source) would flow unidirectionally from the IF port 77 to the RF sink at the RF port 70 in analogous manner.
  • the traveling voltage wave reflects from the FETs due to impedance mismatch between the transmission line ( «50 ⁇ ) and the FETS (Z ⁇ ⁇ J ⁇ *8 ⁇ , Zp CTs oFF ⁇ lOOO ⁇ ).
  • the FET impedance is much less than the line impedance ⁇ ⁇ 50 ⁇
  • the FETS are not conducting, their impedance is much greater that the line impedance (Z FETS > > 50 ⁇ ).
  • the current associated with the local wavefronts of both the incident and reflected waves must flow through Q, and Q 2 , since they form current pairs flowing into the load (e.g. at node A) and out of the load (e.g. at node B); hence they flow through the load.
  • the energy (current) flow is achieved by providing direct electrical connections between appropriate circuit components (as shown and described hereinafter) and by exciting modes in the transmission line baluns that have appropriate propagation modes.
  • a first terminal 84 of the RF balun output port is coupled to the first FET Ql drain and to a second terminal 89 of the first LF balun output port
  • a second terminal 85 of the first RF balun 73 output port is coupled to the third FET Q3 drain and to a second terminal 91 of second LF balun 81 output port
  • a first terminal 86 of the RF balun 76 output port is coupled to the fourth FET Q4 drain and to a first terminal 88 of the LF balun 80 output port
  • a second terminal 87 of the second RF balun 76 output port is coupled to second FET Q2 drain and to a first terminal 90 of the IF balun 81 output port.
  • the coupling between local oscillator balun transformers 51, 53 and the gate and source terminals ofthe first, second, third, and fourth FET transistors is made in pair-wise phase complementary manner such that the first and second FETs Ql and Q2 are driven about 180 degrees out of phase relative to the third and fourth FETs Q3 and Q4.
  • the first and second FETs (Q1-Q2) are driven to ON and OFF conduction states opposite to the conduction states of the third and fourth FETs (Q3-Q4).
  • the conduction state (ON or OFF) of each FET pair determines the phase angle of transmission, and operation of the FET switches results in commutation of the RF signal to the IF port, for example, during frequency down-conversion.
  • FIGS. 5 and 6 illustrate the switching action of transistors Ql , Q2, Q3, and Q4 in response to a LO signal input.
  • LO balun 51 , 54 will present a 50 ⁇ impedance to the LO because resistors R2 56 (100 ohms) and R3 57 (100 ohms) are seen in parallel and represent the principal components of the LO input impedance.
  • LO balun 51 , 54 is wound such that the LO signal is 180 degrees out of phase between the gates of Ql and Q2 and the gates of Q3 and Q4.
  • FET transistors Ql , Q2, Q3, and Q4 do not operate in their linear regions for any significant time and will either be fully ON or fully OFF.
  • FIG. 5 illustrates conditions in the mixer when Ql and Q2 are ON and Q3 and Q4 are OFF.
  • FIG. 6 illustrates the opposite condition when Ql and Q2 are OFF and Q3 and Q4 are ON. If Ql and Q2 are ON, then Q3 and Q4 must be OFF, and vice versa.
  • FETs Ql , Q2, Q3, and Q4 present low impedance of about 2-8 ohms when conducting (ON) and a very high impedance when not conducting (OFF), and either way they do not present an impedance comparable to the impedance of the RF or IF baluns (generally about 50 ohms to about 75 ohms).
  • the RF and IF baluns provide at least three benefits.
  • the baluns cooperate with other mixer components to provide the primary signal mixing and energy coupling function of the mixer circuit.
  • the baluns are an important component of the drain bias circuit.
  • Mixer circuit 10 maintains LO-to-RF and LO-to-LF isolation by directing current flow through the baluns in a balanced fashion.
  • mixer 10 results in partial cancellation of nonlinearity distortion imposed on the RF signal.
  • the LO signal excites the RF and IF baluns in a mode that is not capable of propagating to the RF or IF ports.
  • This propagation mode results in about equal LO voltages at the left hand nodes of T2A1 (node 84), T2A2 (node 85), T2B1 (node 86), T2B2 (node 87), T3A1 (node 88), T3A2 (node 89), T3B1 (node 90), and T3B2 (node 91).
  • Case I described in reference to FIG. 5, Q1/Q2 are ON, Q3/Q4 OFF, and the RF signal (not shown) is applied to the RF port 71 , 72 and the IF port 78, 79 has a load (not shown) connected to it (e.g. the IF port is terminated).
  • RF-port current flows into T2A1 and emerges at the drain of Ql . Passing through Q1/Q2, it flows through T3B1 in the direction shown in FIG. 5 and emerges out of the IF-port terminal 78.
  • RF-port current also flows from RF lead 71 into T2B1 and then through T3A1 in the direction shown and emerges out of the IF-port terminal 78 into the IF load.
  • LF port current passes through the LF termination (load) and returns through IF-port ground terminal 79.
  • IF-port ground current flows into T3A2, into the Ql drain, through Q1/Q2 and through T2B2 in the direction shown in FIG. 5. It then flows out of RF-port ground terminal 72 where it returns to the RF source generator (not shown).
  • IF-port ground current also flows from LF ground terminal 79 into T3B2, through T2A2 in the direction shown and out of RF-port ground terminal 72, where it returns to the RF source generator.
  • the resulting currents have the following properties: (1) the currents flow through Q1/Q2, which are ON; (2) the currents do not flow through Q3/Q4, which are OFF; and (3) the currents form complementary current pairs in each of T2A, T2B, T3A, T3B, consistent with energy flow through each and every aforementioned transformer.
  • IF-port current also flows from pin terminal 78 into T3 A 1 and emerges at the drain of Q4. Passing through Q4/Q3, it flows through T2A2 in the direction shown in FIG. 6 and emerges out of the RF-port ground terminal 72 (out the Q3 drain and IF-port current also flows from pin terminal 78 into T3B1 and then through T2B2 in the direction shown and emerges out of the RF-port ground terminal 72, where it returns to the RF source generator.
  • the resulting currents for Case # have the following properties: (1) the currents flow through Q3/Q4, which are ON; (2) the currents do not flow through Q1/Q2, which are OFF; and (3) the currents form complementary current pairs in each of T2A, T2B, T3A, T3B, consistent with energy flow through each and every one of these transformers.
  • RF port current passes through the RF load (not shown) and returns through RF- port ground 72.
  • RF-port ground current flows from good terminal 72 into T2B2, through Q2/Q1 and through T3A2 in the direction shown in FIG. 7. It then flows out of IF-port ground terminal 79 where it returns to the IF source generator (not shown).
  • RF-port ground current also flows from ground level 72 into T2A2, through T3B2 in the direction shown and out of LF-port ground terminal 79, where it returns to the LF source generator.
  • the resulting currents for Case # LU have the following properties: (1) the currents flow through Q1/Q2, which are ON; (2) the currents do not flow through Q3/Q4, which are OFF; and (3) the currents form complementary current pairs in each of T2A, T2B, T3A, T3B, consistent with energy flow through each and every aforementioned transformer.
  • RF-port current also flows into T2B1 and emerges at the drain of Q4. Passing through Q4/Q3, it flows through T3B2 in the direction shown in FIG. 8 and emerges out of the IF-port ground 79. RF-port current also flows into T2A 1 and then through T3A2 in the direction shown and emerges out of the IF-port ground terminal, 79 where it returns to the RF source generator.
  • the resulting currents for Case LV have the following properties: (1) the currents flow through Q3/Q4, which are ON; (2) the currents do not flow through Q1/Q2, which are OFF; and (3) the currents form complementary current pairs in each of T2A, T2B, T3A, T3B, consistent with energy flow through each and every one of these transformers.
  • FIGS. 9 and 10 shows current request for alternate LO signal half cycles.
  • any current required by RF-port/IF-port during one half cycle of the LO e.g. Q1/Q2 ON
  • alternate LO signal half cycle e.g. Q3/Q4 ON
  • these RF-port and IF-port currents correspond to a symmetrically rectified version of the LO waveform. As such, they do not contain any component at the LO frequency.
  • the RF and IF circuits are symmetrical and support frequencies of equal bandwidth, the designations as RF and as IF are somewhat artificial.
  • the input signals are applied at an RF port and output is taken at an IF port.
  • the labels "RF port” and “IF port” owe their relevance to the mixer application and can alternatively be replaced by the labels "primary port” and “secondary port,” respectively.
  • the higher frequency may be input at either the RF or IF ports and the mixer 10 may be used for either up or down frequency conversion.
  • the input may be applied to either the IF port in which case the output signal is at the RF port, or the input may be applied at the RF port and the output signal extracted at the LF port.
  • the RF and IF frequency bands may be distinct and non-overlapping or alternatively the frequency ranges may overlap broadly.

Landscapes

  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Superheterodyne Receivers (AREA)

Abstract

L'invention concerne un mélangeur à transistor à effet de champ doté de deux circuits de commutation comprenant chacun deux séries de transistors à effet de champ couplés (Q1, Q2; Q3, Q4); un symétriseur d'antenne d'oscillateur local (T1A, T1B) à entrée unique de deux bornes et à deux sorties à deux bornes, chaque sortie étant reliée aux bases couplées des transistors (Q1, Q2; Q3, Q4) de l'un des circuits de commutation; un symétriseur d'antenne RF (T2A, T2B) fournissant les signaux d'entrée RF aux drains des transistors de chaque circuit de commutation; et, enfin, un symétriseur d'antenne aux fréquences intermédiaires (T3A, T3B) et un circuit de polarisation en courant continu (45). Le mélangeur requiert uniquement la présence d'un oscillateur local à faible puissance et offre une annulation partielle de la distorsion de non linéarité imposée aux signaux RF sinsi qu'une réduction de la distorsion d'intermodulation.
PCT/US1996/019964 1995-12-20 1996-12-18 Melangeur a transistor a effet de champ en transmission passive a triple equilibrage WO1997023035A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU12916/97A AU1291697A (en) 1995-12-20 1996-12-18 Triple-balanced passive transmission fet mixer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US57529495A 1995-12-20 1995-12-20
US08/575,294 1995-12-20

Publications (2)

Publication Number Publication Date
WO1997023035A1 true WO1997023035A1 (fr) 1997-06-26
WO1997023035B1 WO1997023035B1 (fr) 1997-08-21

Family

ID=24299716

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1996/019964 WO1997023035A1 (fr) 1995-12-20 1996-12-18 Melangeur a transistor a effet de champ en transmission passive a triple equilibrage

Country Status (2)

Country Link
AU (1) AU1291697A (fr)
WO (1) WO1997023035A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999039431A1 (fr) * 1998-02-01 1999-08-05 Marconi Aerospace Electronic Systems, Inc. Systeme radio comprenant un dispositif de melange a transistor a effet de champ et un circuit de commutation a attaque en ondes carrees, et procede associe
WO1999039432A1 (fr) * 1998-02-01 1999-08-05 Marconi Aerospace Electronic Systems, Inc. Structure et procede de supermelangeur fet a signal de commutation a onde carree de fet genere par porte logique
CN1316739C (zh) * 2002-08-30 2007-05-16 富士通量子器件有限公司 开关电路、开关模块和控制开关电路的方法
TWI686055B (zh) * 2015-03-31 2020-02-21 美商諾斯洛普格拉曼系統公司 三重平衡交錯混合器

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5280648A (en) * 1988-12-06 1994-01-18 Zenith Electronics Corporation Double-balanced high level wide band RF mixer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5280648A (en) * 1988-12-06 1994-01-18 Zenith Electronics Corporation Double-balanced high level wide band RF mixer

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
E. OXNER: "High Dynamic Range Mixing with the SI8901", ELECTRONIC ENGINEERING, vol. 58, no. 713, May 1986 (1986-05-01), UK, pages 53 - 56, XP000644945 *
NEUF D ET AL: "DOUBLE BALANCED, COPLANAR, IMAGE REJECTION MIXER USES MONOLITHIC MESFET QUAD", MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, BOSTON, JUNE 10 - 14, 1991, vol. 2, 10 June 1991 (1991-06-10), HEITER G L, pages 843 - 846, XP000260504 *
TOKUMITSU T ET AL: "DIVIDER AND COMBINER LINE-UNIFIED FET'S AS BASIC CIRCUIT FUNCTION MODULES- PART II", IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, vol. 38, no. 9, 1 September 1990 (1990-09-01), pages 1218 - 1226, XP000142217 *
WEINER S ET AL: "2 TO 8 GHZ DOUBLE BALANCED MESFET MIXER WITH +30 DBM INPUT 3RD ORDER INTERCEPT", IEEE MTT INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, NEW YORK, MAY 25 - 27, 1988, vol. VOL. 2, no. 1988, 25 May 1988 (1988-05-25), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 1097 - 1100, XP000014399 *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999039431A1 (fr) * 1998-02-01 1999-08-05 Marconi Aerospace Electronic Systems, Inc. Systeme radio comprenant un dispositif de melange a transistor a effet de champ et un circuit de commutation a attaque en ondes carrees, et procede associe
WO1999039432A1 (fr) * 1998-02-01 1999-08-05 Marconi Aerospace Electronic Systems, Inc. Structure et procede de supermelangeur fet a signal de commutation a onde carree de fet genere par porte logique
US6108529A (en) * 1998-02-01 2000-08-22 Bae Systems Aerospace Electronics Inc. Radio system including FET mixer device and square-wave drive switching circuit and method therefor
US6144236A (en) * 1998-02-01 2000-11-07 Bae Systems Aerospace Electronics Inc. Structure and method for super FET mixer having logic-gate generated FET square-wave switching signal
US6654595B1 (en) 1998-02-01 2003-11-25 Signia-Idt, Inc. Radio system including mixer device and switching circuit and method having switching signal feedback control for enhanced dynamic range and performance
CN1316739C (zh) * 2002-08-30 2007-05-16 富士通量子器件有限公司 开关电路、开关模块和控制开关电路的方法
TWI686055B (zh) * 2015-03-31 2020-02-21 美商諾斯洛普格拉曼系統公司 三重平衡交錯混合器

Also Published As

Publication number Publication date
AU1291697A (en) 1997-07-14

Similar Documents

Publication Publication Date Title
US5799248A (en) Quasi-double balanced passive reflection FET mixer
US5752181A (en) Method and apparatus for reducing inermodulation distortion in a mixer
US6807407B2 (en) Dual double balanced mixer
US7580693B2 (en) Passive reflection mixer
US5678226A (en) Unbalanced FET mixer
US6064872A (en) Totem pole mixer having grounded serially connected stacked FET pair
US5465415A (en) Even order term mixer
US6871059B1 (en) Passive balun FET mixer
US5280648A (en) Double-balanced high level wide band RF mixer
US4751744A (en) Monolithic distributed mixer
US5027163A (en) High level wide band RF mixer
US5513390A (en) Biased FET mixer
US5732345A (en) Quasi-double balanced dual-transformer dual FET mixer, which achieves better isolation by using a first and second diplexer, and a transmission line RF balun
US8478219B2 (en) Heterodyne receiver
US5789963A (en) Low power consumption mixer and frequency conversion with inter-terminal isolation for stable mixing
Koizumi et al. A GaAs single balanced mixer MMIC with built-in active balun for personal communication systems
US6957055B2 (en) Double balanced FET mixer with high IP3 and IF response down to DC levels
JP3339892B2 (ja) 集積回路およびその使用方法
US5963858A (en) Method and apparatus for mixing signals
WO1997023035A1 (fr) Melangeur a transistor a effet de champ en transmission passive a triple equilibrage
US8249541B2 (en) Subharmonically pumped mixer
EP0802625B1 (fr) Mélangeur à transistor FET non équilibré
WO1997023035B1 (fr) Melangeur a transistor a effet de champ en transmission passive a triple equilibrage
Kobayashi et al. A novel 12-24 GHz broadband HBT distributed active balanced mixer
CA2174395C (fr) Melangeur a fet symetrique

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GE HU IL IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK TJ TM TR TT UA UG UZ VN AM AZ BY KG KZ MD RU TJ TM

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): KE LS MW SD SZ UG AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: JP

Ref document number: 97522934

Format of ref document f/p: F

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase