[go: up one dir, main page]

WO1997015116A3 - Circuits a verrouillage et bascules pour cadencement vrai par horloge monophase (tspc) - Google Patents

Circuits a verrouillage et bascules pour cadencement vrai par horloge monophase (tspc) Download PDF

Info

Publication number
WO1997015116A3
WO1997015116A3 PCT/SE1996/001315 SE9601315W WO9715116A3 WO 1997015116 A3 WO1997015116 A3 WO 1997015116A3 SE 9601315 W SE9601315 W SE 9601315W WO 9715116 A3 WO9715116 A3 WO 9715116A3
Authority
WO
WIPO (PCT)
Prior art keywords
static
latches
flipflops
rail
dynamic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/SE1996/001315
Other languages
English (en)
Other versions
WO1997015116A2 (fr
Inventor
Jiren Yuan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
FORSKARPATENT I LINKOEPING AB
Original Assignee
FORSKARPATENT I LINKOEPING AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by FORSKARPATENT I LINKOEPING AB filed Critical FORSKARPATENT I LINKOEPING AB
Publication of WO1997015116A2 publication Critical patent/WO1997015116A2/fr
Publication of WO1997015116A3 publication Critical patent/WO1997015116A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/356121—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit with synchronous operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • H03K3/356026—Bistable circuits using additional transistors in the input circuit with synchronous operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • H03K3/356034—Bistable circuits using additional transistors in the input circuit the input circuit having a differential configuration
    • H03K3/356043—Bistable circuits using additional transistors in the input circuit the input circuit having a differential configuration with synchronous operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)

Abstract

On analyse dans ce document la vitesse, la robustesse et la performance statique des circuits à verrouillage et bascules pour cadencement vrai par horloge monophase (TSPC). On propose de nouveaux circuits à verrouillage et de nouvelles bascules permettant d'améliorer la vitesse globale, les économies d'énergie, l'insensibilité à la pente d'horloge et la performance statique du TSPC. On propose de nouveaux circuits à verrouillage et bascules à rail unique et à rail double, parmi lesquels on compte différentes versions dynamiques, partiellement statiques et entièrement statiques. Les retards sont réduits selon des facteurs de 1,3, 2,1, 2,2 et 2,4 respectivement pour les versions dynamiques à rail unique, dynamiques à rail double, partiellement statiques et entièrement statiques. En même temps, les consommations d'énergie sont également réduites, et par conséquent, les produits vitesse-consommation sont réduits selon des facteurs de 1,9, 3,5, 3,4 et 6,5 respectivement pour un taux d'activité moyen (0,25). Ces perfectionnements sont accompagnés de comptes de transistors réduits et de charges d'horloge réduites. Une version particulière des circuits à verrouillage proposés n'utilise qu'un seul transistor cadencé et que des transistors NMOS en logique (dans les circuits à verrouillage à la fois de type n et de type p et dans les versions tant dynamiques que statiques).
PCT/SE1996/001315 1995-10-17 1996-10-16 Circuits a verrouillage et bascules pour cadencement vrai par horloge monophase (tspc) Ceased WO1997015116A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9503616-6 1995-10-17
SE9503616A SE507550C2 (sv) 1995-10-17 1995-10-17 Anordning vid grindar och flipp-floppar av kategorin äkta enfasklockade kretsar

Publications (2)

Publication Number Publication Date
WO1997015116A2 WO1997015116A2 (fr) 1997-04-24
WO1997015116A3 true WO1997015116A3 (fr) 1997-05-15

Family

ID=20399844

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/SE1996/001315 Ceased WO1997015116A2 (fr) 1995-10-17 1996-10-16 Circuits a verrouillage et bascules pour cadencement vrai par horloge monophase (tspc)

Country Status (2)

Country Link
SE (1) SE507550C2 (fr)
WO (1) WO1997015116A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106571825A (zh) * 2016-11-07 2017-04-19 中山大学 基于tspc电路的异步时钟信号产生电路

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19749521C2 (de) * 1997-11-08 1999-09-02 Temic Semiconductor Gmbh Bistabile Kippstufe
EP1188237B1 (fr) 1999-06-07 2004-11-03 Infineon Technologies AG Circuiterie a bascule
US6778026B2 (en) * 2002-01-15 2004-08-17 Microtune (San Diego), Inc. High-speed phase frequency detection module
DE102004037591A1 (de) * 2004-08-03 2006-03-16 Infineon Technologies Ag Dual-Rail Precharged Flip-Flop
US9088285B2 (en) 2013-06-25 2015-07-21 Qualcomm Incorporated Dynamic divider having interlocking circuit
CN104378103B (zh) * 2014-09-16 2017-08-04 哈尔滨工业大学（威海） 双轨预充电逻辑单元结构
WO2018137751A1 (fr) * 2017-01-24 2018-08-02 Telefonaktiebolaget Lm Ericsson (Publ) Circuits à retard variable
CN111027276B (zh) * 2018-10-09 2024-09-20 珠海錾芯半导体有限公司 基于多相电平敏感锁存器的集成电路优化系统和方法
US10840892B1 (en) 2019-07-16 2020-11-17 Marvell Asia Pte, Ltd. Fully digital, static, true single-phase clock (TSPC) flip-flop
CN112260682B (zh) * 2020-10-26 2023-07-25 加特兰微电子科技(上海)有限公司 Tspc触发器、双模预分频器和分频器相关器件

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4568842A (en) * 1983-01-24 1986-02-04 Tokyo Shibaura Denki Kabushiki Kaisha D-Latch circuit using CMOS transistors
US5311070A (en) * 1992-06-26 1994-05-10 Harris Corporation Seu-immune latch for gate array, standard cell, and other asic applications

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4568842A (en) * 1983-01-24 1986-02-04 Tokyo Shibaura Denki Kabushiki Kaisha D-Latch circuit using CMOS transistors
US5311070A (en) * 1992-06-26 1994-05-10 Harris Corporation Seu-immune latch for gate array, standard cell, and other asic applications

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
IEEE JOURNAL OF SOLID STATE CIRCUITS, Volume 27, No. 11, November 1992, D.W. DOBBERPUHL et al., "A 200-MHZ 64-B Dual-Issue CMOS Microprocessor". *
IEEE JOURNAL OF SOLID-STATE CIRCUITS, Volume 24, No. 1, February 1989, JIREN YUAN et al., "High-Speed CMOS Circuit Technique". *
IEEE JOURNAL OF SOLID-STATE CIRCUITS, Volume 26, No. 8, August 1991, M. AFGHAHI et al., "Double Edge-Triggered D-Flip-Flops for High-Speed CMOS Circuits". *
IEEE JOURNAL OF SOLID-STATE CIRCUITS, Volume 29, No. 6, June 1994, PATRIK LARSSON et al., "Impact of Clock Slope on True Single Phase Clocked (TSPC) CMOS Circuits". *
IEEE JOURNAL OF SOLID-STATE CIRCUITS, Volume SC-22, No. 5, October 1987, YUAN JI-REN et al., "Correspondence". *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106571825A (zh) * 2016-11-07 2017-04-19 中山大学 基于tspc电路的异步时钟信号产生电路

Also Published As

Publication number Publication date
SE507550C2 (sv) 1998-06-22
WO1997015116A2 (fr) 1997-04-24
SE9503616L (sv) 1997-04-18
SE9503616D0 (sv) 1995-10-17

Similar Documents

Publication Publication Date Title
WO1997015116A3 (fr) Circuits a verrouillage et bascules pour cadencement vrai par horloge monophase (tspc)
US5498988A (en) Low power flip-flop circuit and method thereof
EP0863461B1 (fr) Système de transmission de données avec pipeline auto-cadencé et circuit asynchrone de commande de signal
ES8401714A1 (es) Procedimiento de fabricacion de sistemas elasticos de atadura.
DE69429342D1 (de) Vereinheitlicher gleitkommadatenpfad und ganzzahldatenpfad für einen risc-prozessor
ATE315801T1 (de) Datenträger mit verborgenem leistungsverbrauch
MY116428A (en) Fast regular multiplier architecture
EP0851581A3 (fr) Circuit de bascule
GB9525824D0 (en) Power reduction in a data processing system using pipeline registers and method therefor
US6313683B1 (en) Method of providing clock signals to load circuits in an ASIC device
ES1043376U (es) Capazo-cuna.
AU2001282781A1 (en) Method for operating a communication system and objects for such a system
US5642061A (en) Short circuit current free dynamic logic clock timing
EP0130381A3 (fr) Mécanisme pour la réalisation d'instructions d'aiguillage sur n'importe quel bit dans n'importe quel registre exécutable en un cycle de machine dans un système ordinateur à jeu d'instructions primitif
TW359028B (en) Level shifter irrespective of variation of threshold voltage
EP1796991A4 (fr) Systeme transporteur
EP0206928A3 (en) Low active-power address buffer
GB1429411A (en) Data transmission system
WO2002037342A3 (fr) Systeme de prevision des performances de pieces fabriquees
EP1081857A1 (fr) Procédé d'opération d'un circuit intégré d'application spécifique (ASIC), dispositif ASIC et bascule bistable destinée à être utilisée dans le dispositif ASIC
EP0899741A3 (fr) Dispositif de mémoire à semiconducteurs de type mode en rafale
WO1998054719A3 (fr) Etui
US20030025529A1 (en) Conditional clock gate that reduces data dependent loading on a clock network
WO1999005789A3 (fr) Verrou de blocage de bus resistant a la tension
IL156972A0 (en) A phase-locked loop

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): JP US

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

AK Designated states

Kind code of ref document: A3

Designated state(s): JP US

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: JP

Ref document number: 97515750

Format of ref document f/p: F

122 Ep: pct application non-entry in european phase