WO1997011497A1 - Fabrication method of vertical field effect transistor - Google Patents

Abstract

A method of fabricating a high-output, vertical field-effect transistor having high switching characteristics, which requires only one step to form an N+ connection region and an N- connection region though two steps are required conventionally. To this end, arsenic is implanted into an N-epitaxial layer by high-energy ion implantation of at least 500 keV. As a result, the vertical impurity distribution through the substrate becomes low (or substantially the same) - high - low (substantially the same) with respecto to the concentration of the N-epitaxial layer.

Description

 Specification

Manufacturing method of vertical field effect transistor

Technical field

 The present invention relates to a vertical field effect transistor, and more particularly to a method for manufacturing a vertical field effect transistor having high output and high-speed switching characteristics.

Background art

 Power supplies used for general or industrial use, such as switching regulators, have a tendency to become smaller and lower in price by increasing the frequency, and switching transistors used for these are increasingly used. In addition, low-cost, high-output, high-speed switching performance is required. Normally, this type of transistor has a high output and high speed switching current by providing multiple sources and gates on the surface of the semiconductor substrate, connecting them in parallel, and providing a drain electrode on the back. A vertical field-effect transistor having a structure is used. However, this transistor has a high resistance during conduction (on-resistance) and a large feedback capacitance between the gate and the drain. There is no problem, and various improvement proposals have been made.

Japanese Patent Application Laid-Open No. 63-175754 / 78 discloses that an N ion implanted layer is formed by ion implantation to not only increase the concentration of only the surface but also make the entire N + connection region uniform. It has an O degree distribution to reduce the on-resistance. In Japanese Patent Application Laid-Open No. 1-2536966, after forming an n-conductivity type drain region by epitaxial growth, n-type impurity ions are implanted to form an n + connection region. Implanted impurity ions, or low port n- A method is described in which a conductive type drain region is formed by epitaxial growth, a high-concentration n + connection region is grown, and a low-concentration n-conductive region is formed by epitaxy growth. It is described that the parasitic capacitance is reduced and the resistance during conduction is reduced by these methods. Disclosure of the invention

 However, Japanese Unexamined Patent Publication No. 63-175574 / 98 discloses that not only the concentration on the surface alone is increased, but also the N ions which can make the entire N + connection region have a uniform distribution. Since high-energy ions are implanted, the port on the substrate surface could not be sufficiently lowered, and it was not possible to reduce the return volume S between the gate and drain.

Also, in Japanese Patent Application Laid-Open No. 1-253936, it is possible to reduce the parasitic capacitance and the resistance at the time of conduction, but the realization method is to reduce the n-one conductivity type drain region. The method of implanting n-type impurity ions to form an n + contact region after forming by epitaxial growth, and then implanting p-type impurity ions, requires two ion implantation steps. In addition, the n-type impurity ion concentration near the substrate surface is made to be isotopically low by offsetting by the p-type impurity ion, so that the carrier is small in spite of the fact that the amount of impurities including np is very large. Therefore, there was a problem that the resistance value in this part did not become too small. In addition, since lowering the port by canceling np makes it difficult to fine-tune the port, there is also a problem that it is difficult to control the V th of the transistor. After forming a low-concentration n-conductivity-type drain region by epitaxy, a high-port n + connection region is grown, and a low-concentration n-conductivity-type region is formed by epitaxy. Form In the method, epitaxy was performed three times, and the number of steps increased.

 Another problem is that, in the above-described conventional technology, the n + connection region is formed at the same depth as immediately below the gate even in the source region, so that latch-up due to breakdown in the case of avalanche breakdown is sufficiently suppressed. There was also a problem that it was not done.

 Therefore, the present invention provides a manufacturing method in which the n-type impurity concentration in the vicinity of the substrate surface immediately below the gate is sufficiently reduced, and the impurity concentration distribution is increased toward the inside of the substrate in one step. Aim.

 Another object of the present invention is to provide a vertical field effect transistor that suppresses latchup.

 In one embodiment of the present invention for achieving the above object, after forming the N-epi layer or after forming the channel layer, the surface concentration is equal to or less than the concentration of the N-epi layer, and the peak concentration is N. 500 ke so that the range in the depth direction of the region above the concentration of the N-epi layer and above the concentration of the N-epi layer is located between the surface of the N-epi layer and the lower end of the channel region. Arsenic is ion-implanted with 髙 energy of V or more. In this method, since arsenic is used as an impurity, impurity diffusion is small, and the concentration near the substrate surface does not increase.

Further, in another embodiment of the present invention, immediately below the gate, the surface concentration is equal to or less than the concentration of the N-epi layer, and the range in the depth direction of the region where the portability of the N-epi layer is equal to or more than the N-epi layer is N-epi. The arsenic distribution located between the surface of the epitaxial layer and the bottom of the channel region, and immediately below the channel, the range in the depth direction of the region where the concentration of the N-epi layer exceeds the concentration between the bottom of the channel region and the substrate A vertical field-effect transistor having an arsenic distribution located therein is formed by ion implantation of arsenic with an energy of 500 keV or more using the gate polysilicon and the resist as a mask. in this case, Since the breakdown current path changes depending on the arsenic distribution directly below the channel, the latch-up phenomenon is suppressed. BRIEF DESCRIPTION OF THE FIGURES

 FIG. 1 is a sectional view of a vertical field-effect transistor according to the present invention. FIG. 2 is a view showing an impurity distribution along a depth direction of a cut surface at the center of a gate electrode.

 FIG. 3 is a conceptual diagram of Embodiment 1 of the manufacturing method.

 FIG. 4 is a conceptual diagram of Embodiment 1 of the manufacturing method.

 FIG. 5 is a conceptual diagram of Embodiment 1 of the manufacturing method.

 FIG. 6 is a conceptual diagram of Embodiment 2 of the manufacturing method.

 FIG. 7 is a conceptual diagram of Embodiment 2 of the manufacturing method.

 Fig. 8 is a conceptual diagram of Embodiment 2 of the manufacturing method.

 FIG. 9 is a diagram showing a change in on-resistance when the dose of the 髙 energy arsenic implantation is changed.

 FIG. 10 is a diagram showing a change in the feedback capacitance S with respect to the impurity distribution shape immediately below the gate.

 FIG. 11 is a diagram showing a conventional impurity distribution.

 FIG. 12 is a diagram showing a conventional impurity distribution.

 FIG. 13 is a view showing a conventional impurity distribution.

 FIG. 14 is a view showing a vertical field effect transistor structure according to the present invention.

 FIG. 15 is a diagram showing a conventional structure for avoiding destruction due to latch-up.

FIG. 16 shows a method for manufacturing a vertical field-effect transistor structure according to the present invention. FIG.

 FIG. 17 is a view showing a method of manufacturing a vertical field-effect transistor structure according to the present invention.

 FIG. 18 is a diagram showing a breakdown current path in the embodiment according to the present invention.

 FIG. 19 is a diagram showing a breakdown current path in the conventional structure. BEST MODE FOR CARRYING OUT THE INVENTION

 Hereinafter, the present invention will be described in more detail with reference to examples.

FIG. 1 is a sectional view of a vertical field-effect transistor according to an embodiment of the present invention. The structure shown in Fig. 1 has a structure in which an N-epi layer 4 is laminated on the surface of an N-substrate 5, and in addition to the channel region 3 and the N + source region 2 inside the N-epi layer 4, Implanted layer 1 is formed. A gate electrode 6 is formed on the N-epi layer 4 via an oxide film. After the N-epi layer 4 or the channel layer 3 is formed, the surface concentration of the high-energy arsenic-implanted layer 1 becomes less than the concentration of the N-epi layer 4 and the peak concentration is more than the concentration of the N-epi layer 4 In addition, the distribution in the depth direction in which the S-degree of the N-epi layer 4 is equal to or more than the S degree is a distribution located between the surface of the N-epi scrap 4 and the lower end 10 of the channel region. This high-energy arsenic implanted layer 1 is formed on the entire surface of the N-epi layer 4 by using high-energy ion implantation of 500 keV or more. Usually, in addition to these, a P + connection region 9 is formed, but in the present embodiment, the description in the figure is omitted. In this embodiment, the surface of the N-epi layer 4 or the N-connection region 8 becomes the N-epi layer 4, and the portion of the N-epi layer 4 higher than the port degree becomes the N + connection region 7. —Connection area is formed. FIG. 2 shows the impurity distribution along the depth direction 11 of the cut surface at the center of the gate electrode 6 in FIG. The horizontal axis in FIG. 2 represents the depth direction 11 and the vertical axis represents the impurity concentration. In FIG. 2, an N-epi layer and a high energy arsenic implanted layer 1 are formed on an N substrate 5. As shown in Fig. 2, the surface concentration is lower than the concentration of the N-epi layer, the peak concentration is higher than the concentration of the N-epi layer, and is higher than the concentration of the N-epi layer. The range is a distribution located between the surface of the N-epi layer and the bottom of the channel region. In the prior art, the impurity concentration of the N-epi layer 4 and the impurity concentration of the N-connection region 8 do not always match, but in the present invention, the impurity concentration of the N-epi layer 4 and the impurity concentration of the N-connection region 8 are different. The impurity concentrations are completely consistent. By forming the high-energy arsenic-implanted layer 1, the N-connection region and the N + connection region 7 can be formed in one step.

 One embodiment of the manufacturing method for the embodiment shown in FIG. 1 is shown in FIG. 3, FIG. 4, and FIG.

One embodiment of the manufacturing method for the embodiment shown in FIG. 1 is shown in FIGS. 3, 4, and 5. The N-epi layer 4 is seeded on the N substrate 5 by epitaxial growth (Fig. 3). As the N-substrate 5, an arsenic-doped substrate that easily reduces resistance is used. When forming the N-epi layer 4, phosphorus is doped to make the N-epi layer N-type. Next, a high-energy arsenic implanted layer 1 is formed using high-energy ion implantation of 500 keV or more (Fig. 4). After the above steps, a channel region 3 and an N + source region 2 are formed (FIG. 5). The channel region 3 is formed by implanting boron into the substrate 5 after forming a predetermined mask, and further diffusing boron by heat treatment. The lower end of the channel region 3 is located deeper than the lower end of the high-energy arsenic implanted layer 1. The N + source region 2 is formed by implanting arsenic after forming a predetermined mask. In the arsenic distribution formed in Fig. 4, the diffusion coefficient of arsenic is different. It is not changed by the heat treatment shown in Fig. 5 because it is smaller than the impurity by one order of magnitude. By forming the high-energy arsenic implanted layer 1, the N-connection region 8 and the N + connection region 7 can be formed in the process.

Another embodiment of the manufacturing method for the embodiment shown in FIG. 1 is shown in FIG. 6, FIG. 7, and FIG. The channel region 3 is formed after the N-epi layer 4 is laminated on the N substrate 5 by epitaxial growth (FIG. 6). As the substrate 5, a low-resistance arsenic-doped substrate is used. When the N-epi layer 4 is formed, phosphorus is doped to make the N-epi layer N-type. The channel region 3 is formed by implanting po- ron into the substrate 5 after forming a predetermined mask, and further diffusing boron by heat treatment. Next, a high-energy arsenic implanted layer 1 is formed using high-energy ion implantation of 500 keV or more (Fig. 7). The lower end of the channel region 3 is located deeper than the lower end of the high-energy arsenic implanted layer 1. After the above steps, an N + source region 2 is formed (FIG. 8). The N + source region 2 is formed by implanting arsenic after forming a predetermined mask. Since the diffusion coefficient of arsenic is one order of magnitude lower than that of other impurities, the impurity distribution formed in Fig. 7 does not change due to the heat treatment in Fig. 8.

FIG. 9 shows a change in on-resistance when the dose of the high-energy arsenic implantation is changed in the embodiment shown in FIG. Fig. 9 shows the calculation results using a device simulator. The horizontal axis in FIG. 9 shows the arsenic dose, and the vertical axis shows the on-resistance. From Fig. 9, it can be seen that if arsenic is implanted at 1.0E16 (cm-2), a low resistance with an on-resistance of 100mΩ mm2 or less can be obtained. This value is at the same level as when only N + connection region 7 is formed. FIG. 10 shows a change in the feedback capacitance with respect to the impurity distribution shape immediately below the gate. FIG. 10 shows a calculation result using a device simulator. Next to Fig. 10 The axis represents the impurity distribution shape just below the gate, and the vertical axis represents the feedback capacitance. It can be seen that the feedback capacitance can be reduced when the high energy arsenic implanted layer 1 is formed, as compared with the case where only the N + connection region 7 is formed. When the N + connection region 7 is not formed, the feedback capacitance S can be further reduced, but as shown in FIG. 9, the on-resistance becomes as high as about 120 mΩ mm 2. From FIGS. 9 and 10, it can be seen that this embodiment is effective not only in reducing the conventional two steps to one step but also in reducing the resistance and the feedback capacitance. Due to the reduction of the resistance and the reduction of the return capacitance, the vertical field effect transistor according to the present embodiment has a high output and a high speed switching characteristic.

FIGS. 11, 12 and 13 show differences in impurity distribution between the conventional technology and the high-energy arsenic-implanted layer 1 according to the embodiment of the present invention. The horizontal axis in FIGS. 11, 12, and 13 represents the depth direction 11, and the vertical axis represents the impurity concentration. In FIG. 11, N + connection region 7 is formed by N + epi layer 1 101 on top of N-epi layer 4, and N-connection region 8 is further formed by N-epi layer 1 An example in the case of forming with 102 is shown. When arsenic is used for the N + epi layer 1101, the diffusion coefficient of arsenic is at least one order of magnitude smaller than that of other impurities, so that there is a flat portion of the impurity distribution. When using high-energy arsenic implantation eyebrow 1, such a flat part does not exist. In addition, the impurity concentrations of the N-epi layer 1102 of the N + epi layer 1101 and the N-epi layer 4 do not always match. In FIG. 12, an N + connection region 7 is formed on the N-epi layer 4 by the N + epi layer 1 101, and the surface of the N + connection region 7 is opposite to arsenic. An embodiment in which the N-connection region 8 is formed by forming a conductive type polon diffusion layer 1221 will be described. In the embodiment shown in FIG. 12, boron is introduced to form the N-connection region 8. When the high energy arsenic implanted layer 1 is used, no boron exists in the N-connection region 8. No. Both the prior art shown in FIGS. 11 and 12 require two steps to form the N + connection region 7 and the N − connection region 8. When the high-energy arsenic-implanted layer 1 is used, the N + connection region 7 and the N − connection region 8 can be formed in one step, so that the cost per chip is reduced. FIG. 13 shows an embodiment in which high-energy ion implantation is used to flatten the impurity concentration of the N + connection region 7. The surface concentration of the N + connection region 7 formed by the high-energy ion-implanted layer 1301 shown in FIG. 13 is higher than the concentration of the N-epi layer 4. Furthermore, in order to form such a distribution, it is necessary to use phosphorus instead of arsenic.

A conventional technique for avoiding destruction by latch-up will be described with reference to FIGS. 15 and 19. FIG. FIG. 15 shows an embodiment of the prior art. In FIG. 15, the N-epi layer 4 is removed above the N-substrate 5, and the channel region 3, N + source region 2, N + connection region 7, N + -The connection area 8 is formed. In the embodiment shown in FIG. 15, a P + connection region 9 is formed to avoid destruction due to latch-up. In this embodiment, a total of three steps are required to form the N + connection region 7, the N- connection region 8, and the P + connection region 9. The reason why the conventional P + connection region 9 is effective in avoiding latch-up will be described with reference to FIG. FIG. 19 shows the path 1801 of the breakdown current when the vertical field-effect transistor is subjected to avalanche breakdown. When a current flows along the breakdown current path 1801 in the channel region 3, the voltage at the edge of the gate electrode 6 in the channel region 3 increases. Since the N + source region 2, the channel region 3, and the N-epi layer 4 form an NPN bipolar transistor, the vertical field effect transistor has an edge portion of the gate electrode 6 in the channel region 3. When the voltage rises, the base turns on and a large current flows. This phenomenon is We call it top. If the vertical field-effect transistor latches up, the device will be destroyed. In order to prevent latch-up, it is necessary to suppress the voltage rise at the edge of the gate electrode 6. The P + connection region 9 is a technology that suppresses an increase in compressibility at the edge of the gate electrode 6 due to a voltage drop by reducing the resistance of the channel portion 3. When the present technology is used, an N + connection region, an N − connection region, and a P + connection region are formed in a total of three steps.

FIG. 14 shows an embodiment of the present invention. Fig. 14 shows an N + connection region, an N- connection region, and a device structure that enables a structure to avoid latch-up to be formed in a single process, which was conventionally formed in three processes. It is. In FIG. 14, an N-epi layer 4 is laminated on an N substrate 5, and a channel region 3 and an N + source region 2 are formed in the region of the N-epi layer 4. The structure shown in Fig. 14 shows that immediately below the gate pole 6, the surface area in the depth direction where the surface concentration is less than the concentration of the N-epi layer 4 and higher than the portability of the N-epi layer 4 is N- The arsenic distribution located between the surface of the epitaxial layer 4 and the lower end 10 of the channel region, and the area directly below the channel region 10 in the depth direction where the concentration of the N-epi layer is higher than the lower end of the channel region 1 It has a rectangular high-energy arsenic implanted layer 12 which simultaneously constitutes an arsenic distribution located between 0 and the N substrate 5. The arsenic distribution directly under the gate ¾ pole 6 of the rectangular high-energy arsenic implanted layer 12 plays a role in obtaining high output and high switching characteristics, and the arsenic distribution directly under the channel region 10 avoids damage due to latch-up. Play a role. The reason why the arsenic distribution immediately below the channel region 10 avoids destruction due to latch-up will be described with reference to FIG. In the prior art shown in FIG. 19, the avalanche breakdown occurs near the left end of the gate electrode 6 in the channel region 3. On the other hand, in the embodiment shown in FIG. + Source area 2 Occurs near the left end. Therefore, the breakdown current flows along the path 1801. Blake Kuda Since the pin current path 1801 is shorter than that of the related art, a voltage drop at the edge of the gate electrode 6 of the channel region 3 due to a voltage drop does not easily occur. Therefore, latch-up is less likely to occur. Simply increasing the concentration of the N-epi layer 4 results in the breakdown current path 1802 shown in FIG. 19, and cannot avoid latch-up.

FIGS. 16 and 17 show the manufacturing method of the embodiment shown in FIG. The manufacturing method shown in Fig. 16 and Fig. 17 makes it possible to form the N + connection area, N-connection area, and P + connection area in one process, which were conventionally formed in three processes. _{c An} N-epi layer 4 is formed on the substrate 5 and a channel region 3 and an N + source region 2 are formed in the N-epi layer 4 (FIG. 16). As the N-substrate 5, a low-resistance arsenic-doped substrate is used. When the N-epi layer 4 is formed, phosphorus is doped to make the N-epi layer N-type. The channel region 3 is formed by implanting boron into the substrate 5 after forming a predetermined mask, and further diffusing boron by heat treatment. The N + source region 2 is formed by implanting arsenic after forming a predetermined mask. Next, in order to form the gate electrode 6, a resist 1701 is applied on the polysilicon, and the resist 1701 is applied only to a predetermined region by photolithography. Remove and remove. By etching the polysilicon after removing the resist 1701, the structure shown in Fig. 17 can be formed. After forming the structure shown in Fig. 17, a rectangular high-energy arsenic implanted layer 12 is formed by high-energy arsenic implantation 1702. A rectangular high energy arsenic implanted layer 12 is formed. The lower end of the arsenic distribution directly below the gate ¾ pole 6 is located above the lower end of the channel region 3, and the upper end of the arsenic distribution immediately below the channel region 3 is located below the lower end of the channel region 3. The positions of the arsenic distribution directly below the gate electrode 6 and the arsenic distribution directly below the channel region 3 in the depth direction 11 can be separately specified by the resist film thickness and the implantation energy. By using high-energy arsenic implantation 1702, a structure that conventionally required three processes can be configured by the ェ process.

 One of the effects of the present invention is that the N + connection region and the N − connection region, which are conventionally formed in two steps, can be formed in one step, and the cost per chip can be made equal to the case where only the N + connection region is formed.

Another advantage of the present invention is that the N + connection region conventionally formed in three steps, The structure to avoid destruction due to N-connection area and latch-up can be formed in one process, and the unit cost of the chip can be reduced to less than the conventional one.

Claims

The scope of the claims 1. A vertical field-effect transistor in which a gate and a source region are formed on a main surface of a semiconductor substrate including an N-epi layer, and a drain is formed on a back surface of the semiconductor substrate,  In the N-epi layer immediately below the gate, from the first surface, which is lower than the impurity concentration of the N-epi layer, from the main surface to the back surface of the semiconductor substrate, The arsenic concentration distribution becomes higher than the impurity concentration of the second layer, and then becomes the third concentration lower than the impurity concentration of the N-epi layer. A vertical field effect transistor, wherein the position where the concentration changes to the third port is deeper than the source region and shallower than the lower end of the channel region.  2. In the vertical field effect transistor according to claim 1, in the N-epi layer immediately below the source region, the position at which the first concentration changes from the first concentration to the second port is as described above. A vertical field-effect transistor characterized by being deeper than the lower end of the channel region.  3. A method of manufacturing a vertical field-effect transistor in which a gate and a source region are formed on a main surface of a semiconductor substrate including an N-epi layer and a drain is formed on a back surface of the semiconductor substrate.  A first step of forming an arsenic-implanted layer by introducing arsenic into the N-epi layer by ion implantation,  A second step of forming a channel region by introducing porosity into the N-epi layer deeper than the arsenic-implanted layer immediately below the gate. Manufacturing method. 4. A vertical electric field in which the gate and source regions are formed on the main surface of the semiconductor substrate including the N-epi layer, and the drain is formed on the back surface of the semiconductor substrate. Effect In the manufacturing method of Tranjisu,  A first step of forming a channel region by introducing boron into the N-epi layer;  A second step of forming arsenic-implanted layers shallower than the lower end of the channel region by introducing arsenic into the N-epi waste by ion implantation. Production method.  5. In a method of manufacturing a vertical field effect transistor in which a gate and a source region are formed on a main surface of a semiconductor substrate including an N-epi layer and a drain is formed on a back surface of the semiconductor substrate,  First step of forming a channel region by introducing polon into the N-epi layer After the first step, a resist for forming the gate is formed on the main surface of the semiconductor substrate. A second step of forming the resist into a desired shape;  After the second step, arsenic is implanted into the N-epi layer immediately below the gate by ion implantation to form an arsenic implanted layer shallower than the lower end of the channel region, and the arsenic implanted layer is formed immediately below the source region. A third step of introducing arsenic into the N-epi layer by ion implantation to form an arsenic implanted layer deeper than the lower end of the channel region. Effect Transis evening manufacturing method.  6. The method for manufacturing a vertical field-effect transistor according to any one of claims 3 to 5,  The method of manufacturing a vertical electric field transistor, wherein the ion implantation of the arsenic is a high energy ion implantation of 500 keV or more.