WO1997003465A1 - Puce semi-conductrice, son procede de conditionnement et electrode a bosse - Google Patents
Puce semi-conductrice, son procede de conditionnement et electrode a bosse Download PDFInfo
- Publication number
- WO1997003465A1 WO1997003465A1 PCT/JP1996/000432 JP9600432W WO9703465A1 WO 1997003465 A1 WO1997003465 A1 WO 1997003465A1 JP 9600432 W JP9600432 W JP 9600432W WO 9703465 A1 WO9703465 A1 WO 9703465A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- film
- bump electrode
- semiconductor pellet
- mounting
- external terminal
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 165
- 239000008188 pellet Substances 0.000 title claims abstract description 109
- 238000000034 method Methods 0.000 title claims description 65
- 238000004806 packaging method and process Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 84
- 239000000203 mixture Substances 0.000 claims description 16
- 239000000956 alloy Substances 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 9
- 229910045601 alloy Inorganic materials 0.000 claims description 5
- 238000007740 vapor deposition Methods 0.000 claims description 4
- 238000001704 evaporation Methods 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 abstract description 34
- 239000011347 resin Substances 0.000 abstract description 31
- 229920005989 resin Polymers 0.000 abstract description 31
- 238000002844 melting Methods 0.000 abstract description 12
- 239000010408 film Substances 0.000 description 241
- 239000002184 metal Substances 0.000 description 46
- 229910052751 metal Inorganic materials 0.000 description 46
- 229910020220 Pb—Sn Inorganic materials 0.000 description 25
- 230000005496 eutectics Effects 0.000 description 21
- 239000010410 layer Substances 0.000 description 17
- 230000001681 protective effect Effects 0.000 description 17
- 238000007650 screen-printing Methods 0.000 description 16
- 238000005516 engineering process Methods 0.000 description 14
- 238000000206 photolithography Methods 0.000 description 13
- 230000008018 melting Effects 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000001590 oxidative effect Effects 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- 239000010953 base metal Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 4
- 239000003365 glass fiber Substances 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000009719 polyimide resin Substances 0.000 description 4
- 239000003870 refractory metal Substances 0.000 description 4
- 238000001771 vacuum deposition Methods 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 229910000765 intermetallic Inorganic materials 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000007822 coupling agent Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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Definitions
- the present invention relates to a mounting technique for mounting a semiconductor pellet on a mounting surface of a mounting substrate with a bump electrode interposed.
- a semiconductor pellet is mounted on a mounting surface of a mounting board made of a resin substrate having a low heat resistance with a bump electrode interposed between the mounting board and the CCB (_Controlled C_olla P). se B_onding)
- An implementation technology is disclosed in IEEE [Controlled Collapse Chip Connection (C4) 'Ann Enabling Technology, 1993, PP. 378-394].
- C4 Controlled Collapse Chip Connection
- a semiconductor pellet is mounted using bump electrodes made of a high-melting point composition and solders made of a low-melting point composition. The mounting method using the CCB mounting technology is described below.
- the mounting substrate is formed of, for example, a resin substrate in which glass fiber is impregnated with an epoxy resin.
- the heat resistant temperature of the mounting board is about 260 [° C] ⁇ 60 seconds to about 120 seconds.
- the semiconductor pellet has a bump electrode on an external terminal on its main surface.
- the bump electrode is made of, for example, an alloy material having a composition of 99 to 95 [wt%] Pb—1 to 5 [wt%] Sn. In this case, the melting point of the bump electrode is about 318 to 325 [° C].
- the external terminals on the surface are made of a base metal film (BLM: B_all L_initing_etalizaton) to ensure high wettability with the bump electrodes.
- This external terminal is connected to the lower internal terminal through an opening formed in the final protective film of the semiconductor pellet.
- the underlying metal film is not limited to this structure, but may be used for the metal film (for example, Cr film) that has adhesiveness to the final protective film of the semiconductor pellet and the bump electrode from the surface side of the lower internal terminal. It has a laminated structure in which a wettable metal film (for example, a Cu film) and a non-oxidizable metal film (for example, an Au film) are sequentially laminated.
- a paste solder is formed (printed) on the surface of the external terminal on the mounting surface of the mounting substrate by a screen printing method.
- the welcome solder is formed of, for example, a eutectic composition of 37 [wt%] Pb-6 3 [wt%] Sn. In this case, the melting point of the solder is about 18 3 (Pb—Sn eutectic temperature) C].
- the screen printing method is a method in which paste paste solder placed on a screen mask is transferred by a squeegee from the opening of the risk-lean mask onto the external terminals on the mounting surface of the mounting board.
- the semiconductor bellet is arranged on the mounting surface of the mounting board, and a bump electrode is arranged between an external terminal of the mounting board and an external terminal of the semiconductor pellet.
- a paste-like solder is interposed between the external terminal of the mounting board and one end of the bump electrode.
- the semiconductor pellet can be mounted on the mounting surface of the mounting substrate made of a resin substrate having a low heat-resistant temperature with the bump electrode interposed therebetween.
- the bump electrode has a high melting point composition with a small Sn content [wt%].
- the reason for the formation of the Pb-Sn alloy material is to prevent the bump electrodes from being damaged due to the difference in thermal expansion coefficient between the mounting substrate and the semiconductor pellet.
- the bump electrode becomes harder as the Sn content [% by weight] increases. Disclosure of the invention
- the CCB mounting technology for mounting a semiconductor pellet using the bump electrode made of the high melting point composition and the receiving solder made of the low melting point composition is based on a paste-shaped solder solder that is screen-printed on the surface of the external terminal of the mounting board. After formation, the semiconductor pellet is placed on the mounting surface of the mounting board, and then heat treated to mount the semiconductor pellet. For this reason, the number of steps for mounting is increased by an amount corresponding to the step of forming the paste-like solder.
- ⁇ Screen printing method uses a paste-like solder placed on a screen mask. This is a method in which a squeegee is used to transfer the image from the opening of the rescreen mask onto the surface of the external terminals on the mounting surface of the mounting board.
- the arrangement pitch of the opening of the screen mask is limited to about 300 0 ⁇ ]. is there.
- the arrangement pitch of the external terminals on the mounting substrate can be reduced to about 100 [ ⁇ m] by forming the external terminals on the thin film wiring layer.
- the arrangement pitch of the external terminals of the semiconductor pellet can be reduced to about 100 [ ⁇ m] by forming the external terminals by photolithography.
- the arrangement pitch of the bump electrodes can be reduced to about 100 [ ⁇ ] by forming the bump electrodes by a lift-off method using photolithography technology.
- the arrangement pitch of the openings of the screen mask is limited to about 300 [/ im]
- the arrangement pitch of the external terminals of the mounting board, the external terminals of the semiconductor pellet, and the bump electrodes is met by the solder pitch. It is restricted by the arrangement pitch.
- the bump Since the arrangement pitch of the poles is not set to be less than 300 [y «m], the semiconductor in which the semiconductor pellet is mounted on the mounting surface of the mounting board made of a resin substrate having a low heat-resistant temperature with bump electrodes interposed therebetween. The number of pins in the device cannot be increased.
- the film thickness accuracy of the contact solder formed by the screen printing method is low.
- a connection failure occurs between the external terminal of the mounting board and one end of the bump electrode, and the semiconductor battery is mounted on the mounting surface of the mounting board made of a resin substrate having a low heat-resistant temperature via the bump electrode.
- the yield of the semiconductor device mounting the semiconductor device is reduced.
- Another object of the present invention is to increase the number of pins in a semiconductor device in which a semiconductor pellet is mounted via a bump electrode on a mounting surface of a mounting substrate made of a resin substrate having a low heat resistance temperature. To provide technology.
- Another object of the present invention is to provide a technology capable of increasing the yield of a semiconductor device in which a semiconductor battery is mounted via a bump electrode on a mounting surface of a mounting substrate made of a resin substrate having a low heat resistance temperature. Is to provide.
- a semiconductor pellet having a bump electrode on an external terminal wherein the bump electrode is formed from a surface side of the external terminal by a Pb film and a film thickness of the Pb film.
- the bump electrode is formed from a surface side of the external terminal by a Pb film and a film thickness of the Pb film.
- each of the thin Sn films is sequentially stacked.
- Each of the Pb film and the Sn film is formed by a vapor deposition method.
- the bump electrode at one end of the bump electrode, there is a Pb-Sn interface where Pb atoms and Sn atoms react to form a eutectic composition, so that one end of the bump electrode ( (Sn film) can be melted at the Pb-Sn eutectic temperature (183 [° C]).
- the external terminals of the mounting board and one end of the bump electrode are connected to the Pb-Sn eutectic temperature (183 [° C] ), And can be electrically and mechanically connected, without using low-melting-point solder formed by screen printing, and on the mounting surface of a mounting substrate made of a resin substrate with a low heat-resistant temperature.
- the semiconductor pellet can be mounted with a bump electrode interposed therebetween.
- the semiconductor pellet can be mounted on the mounting surface of a mounting substrate made of a resin substrate having a low heat-resistant temperature without using a low-melting-point contact solder formed by the screen printing method
- the screen printing method can be used.
- the arrangement pitch of the external terminals of the mounting board, the external terminals of the semiconductor pellet, and the bump electrodes can be set without being restricted by the solder formed by the method described above. m].
- the thickness accuracy of each of the Pb film and the Sn film formed by the vapor deposition method is higher than the film thickness accuracy of the contact solder formed by the screen printing method. Poor connection with the tip of the bump electrode can be prevented.
- the mounting board made of a resin The yield of the semiconductor device in which the semiconductor pellet is mounted on the mounting surface with the bump electrode interposed therebetween can be improved.
- FIG. 1 is a cross-sectional view of a semiconductor device according to Embodiment 1 of the present invention.
- FIG. 2 is a cross-sectional view of a main part of the mounting board showing a state before a mounting step is performed.
- FIG. 3 is a plan view of the mounting board.
- FIG. 4 is a cross-sectional view of a main part of the semiconductor pellet showing a state before a mounting process is performed.
- FIG. 5 is a plan view of the semiconductor pellet.
- FIG. 6 is a fragmentary cross-sectional view for explaining a method of forming the semiconductor pellet.
- FIG. 7 is a fragmentary sectional view for explaining a method of forming the semiconductor pellet.
- FIG. 8 is a fragmentary sectional view for explaining a method of forming the semiconductor pellet.
- FIG. 9 is a fragmentary cross-sectional view for explaining a method of forming the semiconductor pellet.
- FIG. 10 is a cross-sectional view for explaining a method for mounting the semiconductor pellet.
- FIG. 11 is an enlarged sectional view of a main part for describing a method of mounting the semiconductor pellet.
- FIG. 12 is a sectional view of a principal part showing a modification of the semiconductor pellet.
- Fig. 13 explains the mounting method of the semiconductor pellet shown in Fig. 12 It is an important section enlarged sectional view for the.
- FIG. 14 is a sectional view of a principal part showing another modified example of the semiconductor pellet.
- FIG. 15 is a sectional view of a principal part showing another modification of the semiconductor pellet.
- FIG. 16 is a cross-sectional view of a principal part of a semiconductor device that is Embodiment 2 of the present invention.
- FIG. 17 is a plan view of a semiconductor pellet showing a state before a mounting process is performed.
- FIG. 18 is a cross-sectional view of a base on which bump electrodes according to Embodiment 3 of the present invention are arranged.
- FIG. 19 is an enlarged sectional view of a main part of the base.
- FIG. 20 is a fragmentary cross-sectional view for explaining the method for forming the bump electrode.
- FIG. 21 is a cross-sectional view for explaining a method of mounting a semiconductor battery using the bump electrode.
- FIG. 22 is a cross-sectional view for explaining a method of mounting a semiconductor pellet using the bump electrodes.
- FIG. 23 is a cross-sectional view for explaining a method of mounting a semiconductor pellet using the bump electrodes.
- FIG. 24 is a sectional view showing a modification of the bump electrode.
- FIG. 1 (cross-sectional view) shows a schematic configuration of a semiconductor device which is Embodiment 1 of the present invention.
- the semiconductor device has a semiconductor pellet 8 mounted on a mounting surface of a mounting substrate 1 with a bump electrode 14 interposed therebetween.
- the mounting board 1 includes, for example, a wiring board 2 and a thin film wiring layer 3.
- the wiring board 2 is formed of, for example, a resin substrate in which glass fiber is impregnated with an epoxy resin or a polyimide resin.
- the wiring board 2 has, for example, a multilayer wiring structure.
- the thin film wiring layer 3 has a multilayer wiring structure in which, for example, polyimide resin is an insulated layer. That is, the mounting substrate 1 of the present embodiment has a structure in which a resin substrate in which glass fiber is impregnated with an epoxy resin or a polyimide resin is used as a base.
- the heat-resistant temperature of the mounting board 1 in this case is about 260 [° C] ⁇ 60 seconds to about 120 seconds.
- a plurality of external terminals 5 and a plurality of internal terminals 4 formed thereunder are arranged.
- Each of the plurality of external terminals 5 is electrically and mechanically connected to each of the plurality of internal terminals 4 through an opening (reference numeral 3A shown in FIG. 2) formed in the final protective film 3B of the thin film wiring layer 3. It is connected to the.
- a plurality of internal terminals 6 are arranged on the back surface of the wiring board 2 of the mounting board 1.
- a spherical bump electrode 16 is electrically and mechanically connected to each of the plurality of internal terminals 6 via an external terminal 7.
- the bump electrode 16 is made of, for example, a Pb-Sn alloy material.
- the semiconductor pellet 8 includes a semiconductor substrate 9 made of, for example, single crystal silicon. It is mainly composed. On the element formation surface (the lower surface in FIG. 1) of the semiconductor substrate 9, a logic circuit system, a storage circuit system, or a mixed circuit system thereof is mounted. A plurality of external terminals 13 and a plurality of internal terminals 11 formed thereunder are arranged on the element formation surface of the semiconductor substrate 9. Each of the plurality of external terminals 13 is electrically and mechanically connected to each of the plurality of internal terminals 11 through openings (reference numeral 12 C shown in FIG. 4) formed in the final protective film 12. ing.
- Each of the plurality of internal terminals 11 is formed on the uppermost wiring layer among wiring layers for electrically connecting the semiconductor elements formed on the element forming surface of the semiconductor substrate 9, for example, an A1 film or It is formed of an A1 alloy film.
- Each of the plurality of internal terminals 11 is insulated and separated from the semiconductor substrate 9 by an interlayer insulating film 12.
- the external terminals 5 of the mounting board 1 and the external terminals 13 of the semiconductor pellet 8 are electrically and mechanically connected by bump electrodes 14. In other words, the semiconductor pellet 8 is mounted on the mounting surface of the mounting board 1 using the CCB mounting technology.
- a resin 15 is filled in a gap region between the mounting board 1 and the semiconductor pellet 8.
- the resin 15 is formed of, for example, an insulating resin obtained by adding a silicone filler, a curing accelerator, a coupling agent, and the like to an epoxy-based thermosetting resin.
- the external terminals 5 of the mounting substrate 1 are formed with a base metal film (BLM: Ball Limit) of the bump electrodes 14 in order to ensure high wettability with the bump electrodes 14. ing etalization).
- BBM Ball Limit
- the external terminals 5 are not limited to this structure, as shown in FIG. 2 (a cross-sectional view of a main part of the mounting board showing a state before the mounting process is performed), the final terminals are placed on the front side of the internal terminals 4. It has a laminated structure in which a metal film 20 having adhesiveness to the protective film 3B, a metal film 21 having wettability to the bump electrode 14 and a metal film 22 having non-oxidizing property are sequentially laminated. It is configured.
- the metal film 20 is formed of a refractory metal film, for example, a Cr film, and its thickness is set to, for example, about 0.1 [m].
- the metal film 21 is formed of, for example, a Cu film, and the thickness thereof is set to, for example, about 0.5 to 5 [ ⁇ ].
- the metal film 22 is formed of, for example, an Au film, and its thickness is set to about 0.1 [ ⁇ ].
- the external terminal 7 is configured as a base metal film for the bump electrode 16 in order to ensure high wettability with the bump electrode 16.
- the external terminal 7 is not limited to this structure, but has the same configuration as the external terminal 5 described above.
- the external terminal 5 and the external terminal 7 are electrically connected to each other via a wiring 3 C, a through-hole wiring 2 B, and an electrode 6.
- the through-hole wiring 2B is formed on the inner wall surface of the through-hole 2A formed in the wiring board 2. Since the through holes 2A are formed by mechanical processing (for example, drilling), it is extremely difficult to set the arrangement pitch to 300 [/ im] or less. However, since the mounting board 1 of this embodiment is composed of the wiring board 2 and the thin film wiring layer 3, the arrangement pitch of the internal terminals 4 and the external terminals 5 must be set to 300 [m] or less. Can be.
- Each of the internal terminal 4 and the external terminal 5 is formed by photolithography technology. Has been established. This photolithography technique can reduce the arrangement pitch of each of the internal terminals 4 and the external terminals 5 to about 100 [ ⁇ ].
- the external terminals 5 of the mounting board 1 of this embodiment are arranged at an arrangement pitch of 100 [ ⁇ m], as shown in FIG. 3 (a plan view of the mounting board showing a state before the mounting process is performed). Have been. In FIG. 3, the dashed line indicates the mounting position of the semiconductor pellet 8.
- the external terminal 13 of the semiconductor pellet 8 is formed as a base metal film (BLM: B ⁇ al 1 imiting ⁇ letalization) of the bump electrode 14 in order to ensure high wettability with the bump electrode 14. ing.
- the external terminal 13 is not limited to this structure, but as shown in FIG. 4 (a cross-sectional view of a main part of the semiconductor pellet before the mounting process is performed), the surface of the internal terminal 11 is From the metal film 20 having an adhesive property to the final protective film 12, the metal film 21 having a wettability to the bump electrode 14, and the metal film 22 having a non-oxidizing property. It has a laminated structure.
- the metal film 20 is formed of a refractory metal film, for example, a Cr film, and its thickness is set to, for example, about 0.1 [m].
- the metal film 21 is formed of, for example, a Cu film, and its thickness is set to, for example, about 0.5 to 5 [m].
- the metal film 22 is formed of, for example, an Au film, and its thickness is set to about 0.1 [m].
- the final protective film 12 has a laminated structure in which, for example, a silicon nitride film 12A and a silicon oxide film 12B are sequentially laminated.
- Each of the internal terminal 11 and the external terminal 13 is formed by photolithography. This photolithography technique can reduce the arrangement pitch of the internal terminals 11 and the external terminals 13 to about 100 [in].
- the external terminals 13 of the semiconductor pellet 8 of this embodiment are As shown in the figure (a plan view of a semiconductor pellet showing a state before a mounting step is performed), the semiconductor pellets are arranged at an arrangement pitch of 100 [m].
- the bump electrode 14 is formed by forming a Pb film 14B and a Sn film 14A thinner than the Pb film 14B from the surface side of the external terminal 13 respectively. It has a laminated structure in which layers are sequentially laminated.
- the thickness of the Pb film 14B is set to, for example, about 50 to: L O O [m]
- the thickness of the Sn film 14A is set to, for example, about 0.4 to 4 [ ⁇ m].
- Each of the Pb film 14B and the Sn film 14A is formed by a vacuum evaporation method.
- the bump electrode 14 is formed by sequentially laminating the Pb film 14 B and the Sn film 14 A thinner than the Pb film 14 B from the surface side of the external terminal 13.
- the bump electrodes 14 are formed by a lift-off method using photolithography technology.
- the lift-off method using the photolithography technique can reduce the arrangement pitch of the bump electrodes 14 to about 100 [m].
- the bump electrodes 14 of this embodiment are arranged at an arrangement pitch of 100 [m].
- the bump electrode 14 is not subjected to a step of forming the shape into a spherical shape by heat treatment, that is, not subjected to a wet back treatment. That is, as shown in FIGS. 4 and 5, the shape of the bump electrode 14 is formed in a truncated cone shape, and its vertical cross-sectional shape is formed in a trapezoidal shape.
- a method of manufacturing the semiconductor pellet 8 will be described with reference to FIG. 6 to FIG. 9 (cross-sectional views showing main parts in respective manufacturing steps).
- a semiconductor wafer composed of a semiconductor substrate 9 made of single crystal silicon is prepared.
- semiconductor elements are formed on the surface of the semiconductor wafer (the element formation surface of the semiconductor substrate 9), and wiring, interlayer insulating films 10, internal terminals 11, final protective films 12, etc. are formed on the surface of the semiconductor elements.
- a plurality of semiconductor pellet forming regions having substantially the same circuit system mounted on the surface of a semiconductor wafer are formed in a matrix.
- the final protective film 12 has a laminated structure in which a silicon nitride film 12A and a silicon oxide film 12B are laminated.
- the internal terminal 11 is formed by a photolithography technique, for example, an A1 film or an A1 alloy film.
- an opening 12 C for exposing the surface of the internal terminal 11 is formed in the final protective film 12.
- the final protective film 12 is adhered to the final protective film 12 on the surface of the final protective film 12 including the surface of the internal terminal 11 exposed from the opening 12C.
- a metal film 20 having a wettability, a metal film 21 having a wettability to the bump electrode 14 and a metal film 22 having a non-oxidizing property are sequentially laminated.
- Each of the metal film 20, metal film 21, and metal film 22 is deposited by, for example, a sputtering method.
- the metal film 20 is formed of a refractory metal film, for example, a Cr film, and its thickness is set to, for example, about 0.1 [m].
- the metal film 21 is formed of, for example, a Cu film, and its thickness is set to, for example, about 0.5 to 5 ⁇ .
- the metal film 22 is formed of, for example, an Au film, and its thickness is set to about 0.1 [m].
- a photoresist mask 23 is formed on the surface of the final protective film 12. This photoresist mask 23 is formed by a photolithography technique.
- Pb and Sn were sequentially deposited on the entire surface of the semiconductor wafer (semiconductor substrate 9) by a vacuum deposition method, and a Pb film 14 was formed on the surface of the external terminal 13 as shown in FIG.
- a laminate composed of B and the Sn film 14A is formed.
- a similar laminated body is also formed on the surface of the photoresist mask 23.
- the shape of the laminated body formed on the surface of the external terminal 13 is formed in a truncated cone shape, and its vertical cross-sectional shape is formed in a trapezoid shape. This laminate is separated from the laminate formed on the surface of the photoresist mask 23.
- the thickness accuracy of each of the Pb film 14B and the Sn film 14A is higher than the thickness accuracy of the contact solder formed by the screen printing method.
- the photoresist mask 23 is removed using a lift-off method, and the laminate (Pb film 14B, Sn film 14A) on the surface of the photoresist mask 23 is removed.
- a bump electrode 14 having a laminated structure composed of the Pb film 14B and the Sn film 14A is formed. Since the thickness accuracy of each of the Pb film 14B and the Sn film 14A is high, the height of each bump electrode 14 is uniform.
- the semiconductor wafer is divided for each semiconductor belt. And the semiconductor pellet shown in Fig. 5. Cut 8 is formed. Since the bump electrodes 14 are not subjected to the wet-back process, the height of each bump electrode 14 can be made uniform.
- the mounting board 1 shown in FIGS. 2 and 3 is prepared, and the semiconductor pellet 8 shown in FIGS. 4 and 5 is prepared.
- the arrangement pitch of the external terminals 5 of the mounting board 1 is set to 100 [ ⁇ ].
- the arrangement pitch of the external terminals 13 and the bump electrodes 14 of the semiconductor pellet 8 is set to 100 [ ⁇ m].
- the semiconductor pellet 8 is arranged on the mounting surface of the mounting board 1, and the external terminals 5 of the mounting board 1 and the external terminals 13 of the semiconductor pellet 8 are connected to each other.
- a bump electrode 14 is arranged between them.
- a heat treatment is performed to electrically and mechanically connect the external terminals 5 of the mounting substrate 1 to one end (511 film 14) of the bump electrode 14.
- the heat treatment is performed in an atmosphere at a temperature slightly higher than the Pb-Sn eutectic temperature (183 [at]) at which Pb atoms and Sn atoms react to form a eutectic structure.
- a reaction layer (intermetallic compound layer) 24 is formed between the external terminal 5 of the mounting board 1 and one end of the bump electrode 14, so that mounting is performed.
- the external terminal 5 of the substrate 1 and one end of the bump electrode 14 can be firmly fixed.
- the bump electrodes 14 are formed on the mounting surface of the mounting board 1 made of a resin substrate having a low heat resistance temperature without using a solder formed on the surface of the external terminal 5 of the mounting board 1 by a screen printing method.
- the semiconductor pellet 8 can be mounted therebetween.
- Each of the metal film 22 of the external terminal 5 and the metal film 22 of the external terminal 13 is a bump electrode. Absorbed in 14
- a resin 15 is filled in a gap region between the mounting board 1 and the semiconductor pellet 8. Thereafter, by forming a spherical bump electrode 16 on the surface of the external terminal 7 of the mounting board 1, the semiconductor device shown in FIG. 1 is almost completed.
- Each of the Sn films 14A, which is thinner than the thickness of the film 14B, is formed in a laminated structure in which they are sequentially laminated.
- Pb—Sn interface where Pb atoms and Sn atoms react to form a eutectic composition.
- Sn film can be melted at Pb-Sn eutectic temperature (183 [° C]).
- the external terminals 5 of the mounting substrate 1 and the tips of the bump electrodes 14 are connected to the Pb-Sn eutectic temperature. (183 [° C]), making it possible to connect electrically and mechanically without using a low melting point solder formed by screen printing.
- the semiconductor pellet 8 can be mounted on the mounting surface of the mounting substrate 1 made of a substrate via the bump electrodes 14.
- the semiconductor pellet 8 is interposed on the mounting surface of the mounting substrate 1 made of a resin substrate having a low heat resistance with a bump electrode 14 interposed therebetween.
- the external terminals 5 of the mounting substrate 1 and the external terminals of the semiconductor pellet 8 can be mounted without being restricted by the low-melting-point composition solder formed by the screen printing method.
- the arrangement pitch of the electrodes 13 and the bump electrodes 14 can be set, and the arrangement pitch of the bump electrodes 14 can be set to 300 [ ⁇ or less. As a result, it is possible to increase the number of pins of the semiconductor device in which the semiconductor pellet 8 is mounted on the mounting surface of the mounting substrate 1 made of a resin substrate having a low heat-resistant temperature with the bump electrode 14 interposed therebetween.
- Each of the Pb film 14 B and the S ⁇ film 14 ⁇ is formed by a vacuum evaporation method.
- the film thickness accuracy of each of the Pb film 14B and Sn film 14A formed by the vapor deposition method is smaller than the film thickness accuracy of the low-melting-point solder formed by the screen printing method. Therefore, poor connection between the external terminal 5 of the mounting board 1 and one end of the bump electrode 14 can be prevented.
- the yield of a semiconductor device in which the semiconductor pellet 8 is mounted on the mounting surface of the mounting substrate 1 made of a resin substrate having a low heat-resistant temperature with the bump electrode 14 interposed therebetween can be increased.
- the metal film 20 having wettability with respect to the final protective film 12 may be formed of a refractory metal film, for example, a Ti film.
- the metal film 21 having wettability to the bump electrode 14 may be formed of, for example, a Ni film.
- each of the external terminal 5 and the external terminal 13 is a metal film having a non-oxidizing property, a metal film having an adhesive property to a final protective film, a metal film having a wettability to the bump electrode 14,
- Each of the non-oxidizing metal films may be sequentially laminated to form a laminated structure.
- the bump electrode 14 is formed of a Sn film 14 A and a film thickness of the Sn film 14 A from the surface side of the external terminal 13.
- a Pb film 14B thicker than the Pb film 14B and an Sn film 14A thinner than the Pb film 14B may be formed in a laminated structure.
- a reaction layer intermetallic compound layer
- the external terminals 13 of the semiconductor pellet 8 and the other end of the bump electrode 14 can be firmly fixed.
- the bump electrode 14 has a Pb film 14 B, which is thinner than the Pb film 14 B from the surface side of the external terminal 13.
- Each of the multilayer films 14C including the Sn film 14C1 and the Pb film 14C2 may be sequentially laminated.
- one end of the bump electrode 14 is determined by the Pb—Sn eutectic temperature (183 [° C]). (Multilayer film 14 C) can be reliably melted.
- Multilayer film 1 4 C of S n film 14 C 1, P b film 14 C 2 are each of a thickness of 3 7 [wt 0/0] P b - 63 [ wt. /. ] It is set to the film thickness of the alloy layer of the composition before and after.
- the bump electrode 14 is a multilayer film composed of a Sn film 14 C 1 and a Pb film 14 C 2 from the surface side of the external terminal 13.
- 14 C, a Pb film 14 B thicker than the thickness of the multilayer film 14 C, and a thinner Sn film 14 C 1 and a Pb film 14 C 2 than the Pb film 14 B May be formed in a laminated structure in which the respective multilayer films 14C are sequentially laminated.
- the bump electrode since there are a plurality of Pb-Sn interfaces at one end and the other end of the bump electrode, the bump electrode depends on the Pb-Sn eutectic temperature (183 [° C]). It is possible to surely melt one end (the multilayer film 14C) of 14 and the other end.
- the bump electrodes 14 are formed from the surface side of the external terminals 13 by an Sn film 14A, a P film having a thickness larger than that of the Sn film 14A.
- b film 14B, a multilayer film 14C comprising a Sn film 14C1 and a Pb film 14C2 thinner than the thickness of the Pb film 14B
- a multilayer film 14 C composed of an Sn film 14 C 1 and a Pb film 14 C 2, compared with the film thickness of the multilayer film 14 C
- the Pb film 14B may have a stacked structure in which a thick Pb film 14B and a Sn film 14A thinner than the thickness of the Pb film 14B are sequentially stacked.
- FIG. 1 A schematic configuration of a semiconductor device according to the second embodiment of the present invention is shown in FIG.
- the semiconductor belt 8 and the semiconductor component 26 are mounted on the mounting surface of the mounting board 1.
- the semiconductor pellet 8 is mounted on the mounting surface of the mounting board 1 with the bump electrode 14 interposed therebetween. That is, the semiconductor pallet 8 is mounted in the CCB scheme (ontroled C_ollaps eB_onding).
- the mounting substrate 1 is formed of, for example, a resin substrate in which glass fiber is impregnated with an epoxy resin or a polyimide resin.
- the heat-resistant temperature of the mounting board 1 is about 260 [° C] ⁇ 60 seconds to about 120 seconds.
- the external terminals 5 of the mounting board 1 and the external terminals 13 of the semiconductor bellet 8 are electrically and mechanically connected by bump electrodes 14.
- Each of the external terminals 5 of the mounting substrate 1 and the external terminals 13 of the semiconductor pellet 8 is provided with a base metal film (BLM: B_all limiting M) of the bump electrode 14 in order to ensure high wettability with the bump electrode 14. .etalization).
- BBM base metal film
- Each of the external terminal 5 and the external terminal 13 is not limited to this structure. However, as in the first embodiment, the external terminal 5 and the external terminal 13 are wetted by the metal film having an adhesive property to the final protective film and the bump electrode 14. Metal film, non-oxidizing gold It has a laminated structure in which the metal films are sequentially laminated.
- the bump electrode 14 is formed of a Pb film (14B) and an Sn film (14A) thinner than the Pb film from the surface side of the external terminal 13 in the same manner as in the first embodiment. ) Are sequentially laminated.
- solder 27 is, for example, 3 7 [weight. /. ] Pb-63 [weight. /. ] It is formed of an alloy material having a composition of Sn. This alloy material has a melting point of about 18 3 [° C].
- the external terminals 13 and the bump electrodes 14 of the semiconductor pellet 8 are 200 [m ] Are arranged at an arrangement pitch of.
- the external terminals 5 of the mounting board 1 are similarly arranged at an arrangement pitch of 200 [m].
- the mounting board 1 and the semiconductor pellet 8 are prepared.
- the arrangement pitch of the external terminals 5 of the mounting board 1 is set to 200 m].
- a solder paste material 37 [% by weight] Pb-63 [% by weight] Sn
- the arrangement pitch of the external terminals 13 and the bump electrodes 14 of the semiconductor pellet 8 is set to 200 [m].
- the semiconductor pellet 8 and the semiconductor component 26 are arranged on the mounting surface of the mounting substrate 1, and a bump electrode is provided between the external terminal 5 of the mounting substrate 1 and the external terminal 13 of the semiconductor pellet 8. 1 4 and solder paste material between the external terminals 2 ⁇ of the mounting board 1 and the leads 26 ⁇ of the semiconductor component 26. Place.
- heat treatment is performed to electrically and mechanically connect the external terminals 5 of the mounting substrate 1 to one end of the bump electrodes 14, and to connect the external terminals 25 of the mounting substrate 1 to the leads of the semiconductor components 26.
- 26 A is electrically and mechanically connected with solder 27.
- the heat treatment is performed in an atmosphere at a temperature slightly higher than the Pb-Sn eutectic temperature (183 [° C]) at which Pb atoms and Sn atoms react to form a eutectic structure.
- a reaction layer (intermetallic compound layer) is formed between the external terminal 5 of the mounting substrate 1 and one end of the bump electrode 14, so that the external terminal 5 of the mounting substrate 1 and the bump electrode 14 are formed.
- One end can be firmly fixed.
- the bump electrodes 14 are formed on the mounting surface of the mounting substrate 1 made of a resin substrate having a low heat resistance temperature without using a solder formed on the surface of the external terminal 5 of the mounting substrate 1 by a screen printing method.
- the semiconductor bellet 8 can be mounted with the interposition.
- a resin 15 is filled in a gap region between the mounting board 1 and the semiconductor pellet 8 to substantially complete the semiconductor device shown in FIG.
- FIG. 18 (sectional view) shows a schematic configuration of the bump electrode according to the third embodiment of the present invention.
- a plurality of bump electrodes 14 are arranged on a substrate 30.
- the base 30 is composed of, for example, a support substrate 3 OA made of a single-crystal silicon substrate and a silicon oxide film 30 B formed on the support substrate 30 A and having poor wettability to the bump electrodes 14. It is configured. That is, Each of the plurality of bump electrodes 14 is disposed on the silicon oxide film 30B having poor wettability.
- the bump electrode 14 is formed from the front side of the silicon oxide film 30B as compared with the Sn film 14A and the film thickness of the Sn film 14A. It has a stacked structure in which a thick Pb film 14B and an Sn film 14A thinner than the thickness of the Pb film 14B are sequentially stacked. That is, the bump electrode 14 has a configuration in which the Sn film 14A thinner than the film thickness is provided on one surface and the back surface of the Pb film 14B.
- the base 30 itself may be formed of a material such as ceramics having poor wettability to the bump electrode (solder) 14. Further, the base 30 may be composed of a support substrate 3 OA and a metal film such as a r film having poor wettability to the bump electrodes (solder) 14.
- the base 30 is prepared.
- a mask 31 exposing a part of the surface is formed on the surface of the base 30.
- the mask 31 is formed of, for example, a photo resist film formed by a photolithography technique.
- an Sn film 14 A, a Pb film 14 B thicker than the Sn film 14 A, and a Pb film 14 B thicker than the Pb film 14 B is sequentially formed by a vacuum deposition method.
- Electrodes 14 are formed.
- the base 30 is disposed on the mounting surface of the mounting substrate 1 and the bump electrodes 14 are disposed on the external terminals 5 on the mounting surface of the mounting substrate 1.
- the bump electrodes 14 firmly connected to the external terminals 5 of the mounting substrate 1 And transferred to the mounting board 1.
- the semiconductor pellet 8 is arranged on the mounting surface of the mounting board 1, and the external terminals 5 of the mounting board 1 and the external terminals 13 of the semiconductor pellet 8 are connected to each other.
- a bump electrode 14 is arranged between them.
- the bump electrode 14 is formed. Since the Pb—Sn interface exists at one end of the electrode 14 and the other end, the external terminal 5 of the mounting board 1 and one end of the bump electrode 14 are shared by Pb—Sn. At the crystallographic temperature (183 [° C]), it can be electrically and mechanically connected, and the external end of the semiconductor pellet 8 The element 13 and the other end of the bump electrode 14 can be electrically and mechanically connected at the Pb—Sn eutectic temperature (183 [° C]).
- the bump electrode 14 is composed of a multilayer film 14 C composed of an Sn film 14 C 1 and a Pb film 14 C 2 from the surface side of the substrate 30.
- a multilayer film 14 composed of a Pb film 14 B thicker than the thickness of the multilayer film 14 C and a Sn film 14 C 1 and a Pb film 14 C 2 thinner than the thickness of the Pb film 14 B It is also possible to form a laminated structure in which each of C is sequentially laminated. In this case, since there are a plurality of Pb-Sn interfaces at one end and the other end of the bump electrode, the bump electrode depends on the Pb-Sn eutectic temperature (183 [° C]). It is possible to surely melt one end of the 14 (multilayer film 14 C) and the other end.
- the bump electrodes 14 are formed from the surface side of the base 30 from the Sn film 14 A, the Pb film 14 B, and the Pb film 14 B, which are thicker than the Sn film 14 A.
- Each of the Sn films 14A, which is thinner than the film thickness of B may be formed in a laminated structure in which each of them is sequentially laminated.
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Abstract
Cette puce semi-conductrice comprend des électrodes à bosses disposées sur ses bornes externes. Une électrode à bosse comprend une structure stratifiée composée d'une couche de Pb et d'une couche de Sn plus mince disposées à la surface d'une borne externe. On peut ainsi connnecter cette puce semi-conductrice, par cette électrode à bosse, à la surface d'un substrat de résine présentant une faible résistance thermique sans utiliser de brasure préparatoire à faible température de fusion. On peut fabriquer avec un meilleur rendement un dispositif semi-conducteur à nombre de broches accru en connectant cette puce semi-conductrice, par l'intermédiaire d'électrodes à bosses, à un substrat de résine présentant une faible résistance thermique.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50565997A JP3582014B2 (ja) | 1995-07-12 | 1996-02-26 | 半導体ペレットの実装方法 |
| TW085103809A TW380361B (en) | 1995-07-12 | 1996-04-01 | Semiconductor pellet and the assembly method thereof and the bump electrode |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17570395 | 1995-07-12 | ||
| JP7/175703 | 1995-07-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO1997003465A1 true WO1997003465A1 (fr) | 1997-01-30 |
Family
ID=16000776
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP1996/000432 WO1997003465A1 (fr) | 1995-07-12 | 1996-02-26 | Puce semi-conductrice, son procede de conditionnement et electrode a bosse |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP3582014B2 (fr) |
| TW (1) | TW380361B (fr) |
| WO (1) | WO1997003465A1 (fr) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001196409A (ja) * | 2000-01-03 | 2001-07-19 | Motorola Inc | 半導体デバイス |
| WO2001091176A3 (fr) * | 2000-05-23 | 2002-04-18 | Unitive Electronics Inc | Billes de soudure a deux/trois couches et procedes de fabrication correspondants |
| US7081404B2 (en) | 2003-02-18 | 2006-07-25 | Unitive Electronics Inc. | Methods of selectively bumping integrated circuit substrates and related structures |
| US7156284B2 (en) | 2000-12-15 | 2007-01-02 | Unitive International Limited | Low temperature methods of bonding components and related structures |
| US7213740B2 (en) | 2000-11-10 | 2007-05-08 | Unitive International Limited | Optical structures including liquid bumps and related methods |
| US7531898B2 (en) | 2002-06-25 | 2009-05-12 | Unitive International Limited | Non-Circular via holes for bumping pads and related structures |
| US7547623B2 (en) | 2002-06-25 | 2009-06-16 | Unitive International Limited | Methods of forming lead free solder bumps |
| KR101217753B1 (ko) * | 2008-12-22 | 2013-01-02 | 알루미늄 오프쇼오 피티이 리미티드 | 소화기가 내장된 랜딩 패드 |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60224248A (ja) * | 1984-04-23 | 1985-11-08 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
| JPS63146452A (ja) * | 1986-12-10 | 1988-06-18 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
| JPS6461038A (en) * | 1987-09-01 | 1989-03-08 | Nec Corp | Manufacture of semiconductor device |
| JPH01208844A (ja) * | 1988-02-17 | 1989-08-22 | Hitachi Ltd | 半導体装置 |
| JPH07302797A (ja) * | 1994-05-02 | 1995-11-14 | Motorola Inc | 半導体素子ならびにその製造および使用方法 |
-
1996
- 1996-02-26 JP JP50565997A patent/JP3582014B2/ja not_active Expired - Fee Related
- 1996-02-26 WO PCT/JP1996/000432 patent/WO1997003465A1/fr active Application Filing
- 1996-04-01 TW TW085103809A patent/TW380361B/zh not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60224248A (ja) * | 1984-04-23 | 1985-11-08 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
| JPS63146452A (ja) * | 1986-12-10 | 1988-06-18 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
| JPS6461038A (en) * | 1987-09-01 | 1989-03-08 | Nec Corp | Manufacture of semiconductor device |
| JPH01208844A (ja) * | 1988-02-17 | 1989-08-22 | Hitachi Ltd | 半導体装置 |
| JPH07302797A (ja) * | 1994-05-02 | 1995-11-14 | Motorola Inc | 半導体素子ならびにその製造および使用方法 |
Non-Patent Citations (1)
| Title |
|---|
| BY SOLDER WELDING HANDBOOK EDITION COMMITTEE, "Solder Welding Handbook", 25 March 1970, SANPO, p. 109-111. * |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001196409A (ja) * | 2000-01-03 | 2001-07-19 | Motorola Inc | 半導体デバイス |
| WO2001091176A3 (fr) * | 2000-05-23 | 2002-04-18 | Unitive Electronics Inc | Billes de soudure a deux/trois couches et procedes de fabrication correspondants |
| US6492197B1 (en) | 2000-05-23 | 2002-12-10 | Unitive Electronics Inc. | Trilayer/bilayer solder bumps and fabrication methods therefor |
| US7213740B2 (en) | 2000-11-10 | 2007-05-08 | Unitive International Limited | Optical structures including liquid bumps and related methods |
| US7156284B2 (en) | 2000-12-15 | 2007-01-02 | Unitive International Limited | Low temperature methods of bonding components and related structures |
| US7531898B2 (en) | 2002-06-25 | 2009-05-12 | Unitive International Limited | Non-Circular via holes for bumping pads and related structures |
| US7547623B2 (en) | 2002-06-25 | 2009-06-16 | Unitive International Limited | Methods of forming lead free solder bumps |
| US7081404B2 (en) | 2003-02-18 | 2006-07-25 | Unitive Electronics Inc. | Methods of selectively bumping integrated circuit substrates and related structures |
| US7579694B2 (en) | 2003-02-18 | 2009-08-25 | Unitive International Limited | Electronic devices including offset conductive bumps |
| KR101217753B1 (ko) * | 2008-12-22 | 2013-01-02 | 알루미늄 오프쇼오 피티이 리미티드 | 소화기가 내장된 랜딩 패드 |
Also Published As
| Publication number | Publication date |
|---|---|
| TW380361B (en) | 2000-01-21 |
| JP3582014B2 (ja) | 2004-10-27 |
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