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WO1996035165A1 - Controle des limites d'une memoire d'instruction dans un microprocesseur - Google Patents

Controle des limites d'une memoire d'instruction dans un microprocesseur Download PDF

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Publication number
WO1996035165A1
WO1996035165A1 PCT/US1996/006146 US9606146W WO9635165A1 WO 1996035165 A1 WO1996035165 A1 WO 1996035165A1 US 9606146 W US9606146 W US 9606146W WO 9635165 A1 WO9635165 A1 WO 9635165A1
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WIPO (PCT)
Prior art keywords
branch
instruction
stage
prefetch
address
Prior art date
Application number
PCT/US1996/006146
Other languages
English (en)
Inventor
Robert Divivier
Mario Nemirovsky
Original Assignee
National Semiconductor Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corporation filed Critical National Semiconductor Corporation
Priority to EP96913319A priority Critical patent/EP0771442A1/fr
Publication of WO1996035165A1 publication Critical patent/WO1996035165A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching

Definitions

  • the invention relates to detecting and reporting instruction memory boundary violations. More particularly, the invention relates to a method and apparatus for detecting when the boundary of an instruction memory has been reached in the prefetch stage of a pipelined microprocessor, but not reporting an exception until it is no longer possible to branch around the limit violation.
  • Modem microprocessors employ pipelining techniques which allow multiple, consecutive instructions to be prefetched, decoded, and executed in separate stages simultaneously. Accordingly, in any given clock cycle, a first instruction may be executed while the next (second) instruction is simultaneously being decoded, and the instruction after that one (a third instruction) is simultaneously being fetched. Since less processing is performed on each instruction per cycle, cycle time can be made shorter. Thus, while it requires several clock cycles for a single instruction to be pre-fetched, decoded, and executed, it is possible to have a processor completing instructions as fast as one instruction per cycle with a very short cycle period, because multiple consecutive instructions are in various stages simultaneously.
  • buffers for temporarily holding data are used to define the boundary between consecutive stages of a microprocessor pipeline.
  • the data calculated in a particular stage is written into these buffers before the end of the cycle.
  • the pipeline advances upon the start of a new cycle, the data is written out of the boundary buffers into the next stage where the data can be further processed during that next cycle.
  • Most pipelined microprocessor architectures have at least four stages including, in order of flow,
  • prefetch stage instructions are read out of memory (e.g., an instruction cache) and stored in a buffer.
  • the prefetch buffer may receive one to several instructions.
  • the processor reads an instruction out of the prefetch buffer and converts it into an internal instruction format which can be used by the microprocessor to perform one or more operations, such as arithmetic or logical operations.
  • the execute stage the actual operations are performed.
  • the writeback stage the results of the operations are written to the designated registers and/or other memory locations.
  • one or more of the four basic stages can be further broken down into smaller stages to simplify each individual stage and even further improve instruction completion speed.
  • instructions are read out of memory in a sequential address order.
  • instruction branches in which the retrieval of instructions from sequential address spaces is disrupted, are common, occurring on average about every four to nine instructions.
  • the hardware in an instruction prefetch stage typically comprises a prefetch buffer or prefetch queue which can temporarily hold instructions.
  • the decode stage can take in the bytes of an instruction held in the prefetch stage for decoding during that cycle.
  • Some microprocessor architectures employ what are known as variable width instruction sets. In such architectures, the instructions are not all the same width. For instance, in the instruction set for the x86 family of microprocessors developed by Intel Corporation of Santa Clara, California, an instruction can be anywhere from 1 to 16 bytes wide.
  • Some microprocessor architectures utilize a segmented address space in which the total memory space is broken down into a plurality of independent, protected address spaces. Each segment is defined by a base address and a segment limit.
  • the base address for instance, may be the lowest numerical address in the segment space.
  • the segment limit defines the size of the segment. Accordingly, the end boundary of the segment is defined by the sum of the base address and the segment limit. Alternately, the base address may be the highest address and, as such, the end boundary of the segment would be the difference between the base address and the segment limit.
  • a branch instruction usually specifies, in some manner, the address from which the next instruction to be executed after the branch instruction is to be retrieved.
  • the execute stage halts the normal flow of instructions through the preceding stage of the pipe, e.g., the prefetch and decode stages, and instead supplies the next address for retrieving instructions to the prefetch stage.
  • ⁇ e instructions which had been retrieved from sequential addresses after the branch instruction which are in the pipe i.e., the instructions in the prefetch and decode stages, should not be executed, but should be flushed from the pipe.
  • the flow can be altered by mechanisms other than an executed branch instruction, such as an interrupt. Any change in program flow from sequential addressing is collectively referred to as a branch in this specification, even if it is not the result of a branch instruction.
  • the base address of the particular segment as indicated by the segment descriptor and an offset indicating the distance of the desired data (i.e., instruction) from the base of the segment must be added together.
  • the offset itself may comprise up to three more parts, a base, index and displacement. If so, those quantities must be added to generate the offset before the offset could be added to the segment base.
  • the invention is an efficient method and apparatus for detecting and reporting instruction segment limit violations when programming flow branches to a valid address, but sequential instruction execution from the branch address results in a segment limit violation.
  • a segment space value is an efficient method and apparatus for detecting and reporting instruction segment limit violations when programming flow branches to a valid address, but sequential instruction execution from the branch address results in a segment limit violation.
  • SEGSPACE is generated in the execute stage, where the linear address of an instruction to be fetched from memory is generated.
  • the execute stage includes two adders which can perform two address additions in the same cycle. Accordingly, all addresses which have only a scaled index and a displacement or a base and a displacement can be calculated in a single cycle.
  • a first adder calculates the segment offset and a second adder adds the calculated offset to the segment base to generate the linear address.
  • a limit check circuit in the execute state subtracts the calculated offset from the segment limit value to generate the SEGSPACE value which indicates the number of bytes between the instruction pointer and the segment limit.
  • the SEGSPACE value is provided into a SEGSPACE register in the prefetch stage and the prefetch stage starts retrieving instructions sequentially from the branch address. As bytes are brought into the prefetch stage, the value in the SEGSPACE register is decremented by the number of byte retrieved. When the value in the SEGSPACE register reaches zero, a LIMIT HIT latch is set.
  • an instruction limit error is not reported, until (1) there are fewer bytes remaining in the prefetch stage than are necessary to complete the instruction currently in the decode stage, (2) a branch has not occurred in the execute stage, and (3) the LIMIT HIT latch is set. When these conditions are met, the decode stage reports an instruction segment limit exception to the execute stage upon the next pulse of the program counter.
  • An interrupt handler can then perform any recovery functions it has available to it to attempt to recover from the error. If it cannot recover from the error, programming is stopped and a flag is set indicating that the program has been stopped due to an instruction segment limit exception.
  • Figure 1 is an architectural block diagram of a microprocessor according to a preferred embodiment of the present invention.
  • Figure 2 is a block diagram showing a logical representation of the prefetch stage of a microprocessor according to a preferred embodiment of the present invention.
  • Figure 3 is a block diagram of limit violation detecting and reporting circuitry in the prefetch and decode stages of a microprocessor according to a preferred embodiment of the present invention.
  • Figure 4 is a block diagram of an actual preferred implementation of limit violation detecting and reporting circuitry in the prefetch and decode stages according to a preferred embodiment of the present invention.
  • FIG. 1 is a block diagram generally illustrating the various pipeline stages of a microprocessor according to a preferred embodiment of the present invention. As shown, the microprocessor is pipelined into five stages, namely, 1) a prefetch stage, 2) a decode stage, 3) an execute stage, 4) a writeback stage, and 5) a second writeback stage. As shown, the prefetch stage includes two prefetch buffers 12 and 14, termed prefetch buffer 0 and prefetch buffer 1 , respectively.
  • the prefetch stage also includes prefetch logic 20 for performing various functions relating to the control of the loading of the prefetch buffers with instructions.
  • the decode stage loads from prefetch buffer 0. Accordingly, prefetch buffer 0 defines the boundary between the prefetch stage and the decode stage.
  • the decode stage includes a data extraction unit 26 for separating the various portions of an instruction and forwarding them to the appropriate logic in the decode stage.
  • the decode stage further includes decoder 22 for decoding instructions and a microcode-ROM 24.
  • the data extraction unit 26 separates the instruction into its individual components, including, for instance, prefix byte(s), op-code and operand(s). The prefix and op-code portions are forwarded to the decoder 22.
  • the decoder 22 addresses a particular location or locations in microcode- ROM 24 responsive to the op-code.
  • Microcode-ROM 24 outputs decoded instruction controls for controlling the execute stage to appropriate registers for clocking into the execute stage on the next cycle.
  • Data extraction unit 26 extracts any operands and forwards them to appropriate registers for clocking into the execute stage on the next cycle.
  • the x86 architecture has over 200 instructions.
  • the instruction may include no operands, one operand, or two operands.
  • a branch instruction usually specifies in the operand field the address location to which instruction flow is to jump.
  • the branch address can be specified as a relative address (by providing the number of addresses or bytes from the present address to the branch address) or as a more complex value which must be calculated from the operands in the branch instruction and/or other data).
  • the operand might specify a register or memory location from which the address or a portion of the address is to be fetched.
  • the operand might also specify a direct offset address from which the linear address can be generated by adding in the base address of the current segment. Any number of other methods could be used also.
  • the instruction is executed and, in the case of branch instructions, a linear address is generated.
  • a linear address is generated.
  • two quantities must be added.
  • the base address of the particular segment and a value indicating the distance of the desired data from the base of the segment (a segment offset value) must be added.
  • the segment offset value itself may comprise up to three more parts, namely, a base, an index, and a displacement.
  • the execute stage employs two adders so that two address additions can be performed in one cycle. Accordingly, all addresses which have only a scaled index and a displacement or a base and a displacement can be calculated in a single cycle.
  • the first adder 28 is used to operate on instruction operands for all types of instructions such as add, subtract, multiply, divide, and logical operation instructions as well as instructions requiring address additions.
  • the second adder 30 is only used for calculating linear addresses. Generation of linear addresses is necessary, not only for branch instructions, but also for certain other types of instructions, such as memory and I/O reads. During branch instructions, a first adder 28 generates the segment offset by adding the necessary values.
  • the two particular values which are added depend on the particular instruction, and are selected by multiplexers 74, 76, 78 and 80.
  • the second adder 30 adds the calculated segment offset from the first adder 10 the segment base in order to generate the linear address.
  • the segment base is supplied from the shadow register 32 of the execute stage.
  • the linear address is then used to fetch instructions into the prefetch stage.
  • the segment offset value which is output by first adder 28 is input through multiplexer 82 to a first input terminal of a limit check circuit 34.
  • a segment limit value is supplied from the shadow register 32 to the other input of limit check circuit 34.
  • the limit check circuit subtracts the offset value from the segment limit, thus generating a value, SEGSPACE, which is the number of bytes between the branch address and the end of the segment within which that address resides.
  • the output, SEGSPACE, of limit check circuit 34 is supplied to prefetch logic 20 in the prefetch stage and is used therein to detect and report memory segment boundary violations as will be described in greater detail below.
  • FIG. 2 is a more detailed block diagram showing a logical representation of prefetch stage apparatus for retrieving and handling prefetched instructions according to a preferred embodiment of the present invention.
  • the prefetch stage utilizes a two tier prefetch buffer system comprising buffers 12 and 14.
  • the provision of a two tier prefetch buffer system helps keep prefetch buffer 0 as full as possible on each cycle and, thus, helps avoid pipeline stalls caused by the unavailability of instructions in prefetch buffer 0 for the decode stage to decode.
  • the decode stage pulls instructions for decoding only out of primary prefetch buffer 12 (hereinafter prefetch buffer 0).
  • prefetch buffer 0 is the data interface between the prefetch stage and the decode stage.
  • Prefetch buffer 14 is a secondary buffer (hereinafter prefetch buffer 1) into which retrieved instruction bytes which cannot be loaded directly into prefetch buffer 0 are stored. The instruction bytes loaded into prefetch buffer 1 are held there until space becomes available in prefetch buffer 0, at which time the bytes are loaded from prefetch buffer 1 into prefetch buffer 0.
  • the decode stage does not interface with prefetch buffer 1 , but only with prefetch buffer 0.
  • instruction bytes are returned from memory, they are loaded into byte positions within the prefetch buffers 0 and 1 which are dictated by their addresses. Particularly, the 3 LSBs of the address dictate the byte position in the 8 byte wide buffers into which the instruction byte should be loaded.
  • Loading instruction bytes into the prefetch buffers in this manner substantially simplifies circuitry throughout the processor.
  • Cache line and prefetch buffer widths of 8 bytes are preferred because it achieves a substantial reduction in semiconductor area as compared to prior art architectures in which the prefetch buffer (or queue) is as wide as the maximum possible instruction width or wider. However, it is wide enough to accommodate the vast majority of instructions in a single line.
  • the prefetch stage includes a transparent latch 54 for timing purposes. It also includes multiplexers 56 and 58.
  • prefetch buffer 0 The instruction bytes returned from memory (either external memory or cache memory) are loaded directly into prefetch buffer 0, if the appropriate byte position in prefetch buffer 0 is available. Those instructions bytes for which space does not currently exist in prefetch buffer 0 are loaded into the corresponding byte position in prefetch buffer 1. An instruction byte held in prefetch buffer 1 will be loaded into prefetch buffer 0 when the corresponding byte position in prefetch buffer 0 becomes available (i.e., when the decode stage consumes the instruction byte that is currently occupying that byte position in prefetch buffer 0).
  • Each byte in the prefetch buffers has associated with it a valid tag bit indicating whether or not the data contained in the corresponding byte position of the buffer is a valid instruction byte to be decoded.
  • the valid tag bits are used to determine which bytes are available for loading of incoming instruction bytes from memory and which bytes are occupied by valid instruction bytes to be decoded and, therefore, cannot be overwritten by the incoming instruction bytes.
  • the clock enable signals 70 and 72 of prefetch buffers 0 and 1, respectively, and the select control lines 62 and 64 of multiplexers 58 and 56, respectively, are used to direct the instruction bytes returned from memory into the appropriate prefetch buffer 0 or 1.
  • Multiplexers 56 and 58 are each 8 bytes wide, which is the same width as the cache lines and the prefetch buffers. Multiplexers 56 and 58 also each have 8 select control lines 64 and 62, respectively, so that each byte can be individually selected. Also, each byte of the prefetch buffers 12 and 14 can be individually enabled by a separate clock enable signal. Accordingly, the clock enable signals 72 and 70 of prefetch buffers 0 and 1, respectively, also are 8 bits wide.
  • the select control lines 64 and 62 of multiplexers 56 and 58, respectively, and the clock enable signals 70 and 72 of prefetch buffers 0 and 1, respectively, are controlled in accordance with the following scheme to assure proper loading of data.
  • all bytes in byte positions for which there is room in prefetch buffer 0 i.e., for which the corresponding byte positions in line buffer 12 are tagged invalid
  • prefetch buffer 0 bypassing prefetch buffer 1.
  • valid instruction bytes in prefetch buffer 1 which are in byte positions corresponding to an invalid tagged byte position in prefetch buffer 0 are loaded from prefetch buffer 1 into prefetch buffer 0.
  • Valid bytes from memory and valid bytes from prefetch buffer 1 will never co-exist in the same byte position since a memory request would not have been made unless the data in prefetch 1 in the byte position corresponding to the incoming data from memory was tagged invalid. In other words, a memory request would not be made by the prefetch stage unless there was room in prefetch buffer 1 for the returned data.
  • prefetch buffer 1 Those instruction bytes returned from memory for which room does not presently exist in prefetch buffer 0 are loaded into prefetch buffer 1. After each fetch, the valid tag bits of both prefetch buffers are updated. This updating operation includes consideration of not only the bytes which were loaded into prefetch buffers 1 and 0 during that cycle, but also those bytes in prefetch buffer 0 which were consumed by the decoder during that cycle and, therefore, can be reset from valid to invalid.
  • U.S. Patent Application Serial No. entitled “Two Tier Prefetch Structure And Method With Bypass” (Attorney Docket No. NSC 1-65000) filed on even date herewith and incorporated herein by reference.
  • Figure 3 is a logical representation of the componentry in the prefetch and decode stages for detecting and reporting a segment space violation in a microprocessor made in accordance with the present invention.
  • the SEGSPACE value calculated by the limit check circuit 34 in the execute section is provided to the first input of a 2:1 multiplexer 84.
  • Multiplexer 84 is controlled to select SEGSPACE responsive to a signal from the execute stage indicating that a branch has been taken in that cycle.
  • the SEGSPACE value is provided through multiplexer 84 into a SEGSPACE register 86, where it is stored. Every cycle, the contents of the SEGSPACE register 86. are outputted to a decrement circuit 88.
  • Decrement circuit 88 subtracts from the SEGSPACE value the number of bytes which were loaded into the prefetch stage during that cycle and returns the new SEGSPACE value to the SEGSPACE register 86 through the other input of 2:1 multiplexer 84.
  • the SEGSPACE value also is provided to a zero detect circuit 90.
  • Zero detect circuit 90 compares the SEGSPACE value to zero and outputs a one bit signal indicating whether the SEGSPACE value has reached zero or not. When zero detect circuit 90 detects that the SEGSPACE value in register 86 has reached 0, it sets a LIMIT HIT latch 92. Also, circuitry determines the last valid byte of instruction data and updates the valid tag bits such that the incoming bytes which are beyond the segment limit are tagged invalid.
  • the setting of the LIMIT HIT latch 92 occurs when the last byte in the memory segment has been loaded into one of the prefetch buffers. When this event occurs, there is no point in continuing to prefetch consecutive instruction bytes out of memory since, by definition, there are no more valid instruction bytes sequentially available. Accordingly, the output of the LIMIT HIT latch 92 is provided to additional prefetch logic (not shown) which will halt the prefetching of instructions unless and until a branch occurs.
  • the setting of the LIMIT HIT latch 92 indicates only that the last possible sequential instruction has been prefetched. It does not necessarily mean that mis instruction will ever reach the execute stage since a branch could occur before it reaches the execute stage.
  • a branch instruction exists in the pipeline somewhere between the instruction just executed in the execute stage and the last byte in the segment.
  • a branch instruction may exist (1) in prefetch buffer 0, (2) in prefetch buffer 1, or (3) in the decode stage currently being decoded. Accordingly, despite the fact that a segment limit hit has been detected, an exception is not reported to the execute stage until it is confirmed that there is no possibility of a branch occurring before that last instruction in the segment space is executed.
  • the output of AND gate 94 is supplied to the decode stage where it is ANDed with the inverse of a BRANCH TAKEN signal 95 and the inverse of an ENOUGH BYTES signal 97.
  • the BRANCH TAKEN signal 95 is received from the execute stage and indicates whether or not the execute stage is currently executing a branch. If it is a taken branch, then the limit error exception should not be • reported since the pipeline will be flushed and instruction execution will continue from a new location before the last instruction in the segment is executed.
  • the ENOUGH BYTES signal 97 input to AND gate 96 is a one bit signal generated in the decode stage which indicates whether or not enough bytes are tagged valid in prefetch buffer 0 to complete the instruction currently being decoded.
  • the decode stage keeps track of the valid tag bits of prefetch buffer 0 for normal operation regardless of the limit checking function. Accordingly, the decode stage is aware of the number of bytes needed to complete the decoding of the instruction currently in the decode stage as well as the number of valid instruction bytes in prefetch buffer 0.
  • the ENOUGH BYTES signal can be derived from these values through a simple combinational logic circuit.
  • the output of AND gate 94 is asserted (indicating that (a) there are no valid instruction bytes in prefetch buffer 1 and (b) the LIMIT HIT latch is set), (2) the BRANCH TAKEN signal 95 is not asserted (indicating that the execute stage is not currently executing a branch), and (3) the ENOUGH BYTES signal is not asserted (indicating that there are not enough bytes in prefetch buffer 0 to complete the instruction currently being decoded), then instruction execution cannot continue without violating the segment limit. Thus, an exception should be reported. Accordingly, the output of AND gate 96, is provided to latch 98 in the decode stage, the contents of which will be forwarded to the execute stage on the next advancement of the program counter. When the output of AND gate 96 has set the latch 98, the execute stage can perform whatever error recovery operations are available to attempt to recover from the error. If it cannot recover from the error, program execution is halted and the error logged.
  • FIG. 4 is a block diagram illustrating a preferred actual implementation of the prefetch limit detecting and reporting apparatus illustrated in Figure 3.
  • the SEGSPACE register is broken down into two sections.
  • the first section 104a includes the 29 MSBs of the 32 bit SEGSPACE value and the second portion 104b comprises the three LSBs of the SEGSPACE value.
  • the limit check circuit 34 in the execute stage actually generates the one's complement of the number of bytes between the branch address and the segment limit, rather than a positive value.
  • all arithmetic is in l's complement rather than in positive values, as were discussed above with respect to Figure 3.
  • SEGSPACE value (actually the l's complement thereof) is input to a first input of a multiplexer 102a, while the 3 LSBs of the SEGSPACE value are input to the first input of a second multiplexer 102b.
  • the select control input signal to multiplexers 102a and 102b is the BRANCH TAKEN signal 95 generated in the execute stage. If a branch is taken, multiplexers 102a and 102b select the value coming in from the execute stage on SEGSPACE line 120. Otherwise, they select their second inputs on lines 118 and 106, respectively.
  • the 29 MSBs of SEGSPACE are sent through multiplexer 102a to SEGSPACE register 104a and the three LSBs of the SEGSPACE value are forwarded through multiplexer portion 102b to SEGSPACE register 104b.
  • the clock enable for register 104b is asserted whenever the prefetch stage receives data from memory (cache or external) or a branch is taken.
  • the three LSBs of the SEGSPACE value stored in register 104b are incremented with wrap around from seven (i.e., binary 111) to zero (i.e., binary 000) by the number of instruction bytes retrieved from memory each cycle. In other words, it is incremented in modulo 8.
  • the output 114 of register 104b is added in adder 122 to the number of incoming bytes, e.g., 2 if it is a memory access or 8 if it is a cache hit (assuming no branch). If the carry bit in the third bit position of adder 122 is set, it means that an 8 byte boundary has been crossed and that the 29 MSBs of SEGSPACE, as stored in register 104a, should be incremented by 1.
  • the clock enable input 124 into register 104a is the carry bit in the third bit position of adder 122.
  • the output of register 104a is provided to an INCREMENT-BY-ONE circuit 108 every cycle.
  • register 104a is enabled to load data only when the carry bit out of the third bit position of adder 122 is asserted.
  • the incremented value output by INCREMENT-BY- ONE circuit 108 every cycle does not replace the value in register 104a unless an 8 byte boundary has been crossed in the 3 LSBs of the SEGSPACE value stored in register 104b.
  • the LIMIT HIT latch is set as follows.
  • the three LSBs of SEGSPACE stored in register 104b are provided on line 114 to a first input of a comparator circuit 122.
  • the second input of comparator circuit 122 is coupled to receive a signal indicating the number of bytes which have been returned from memory. If the 3 LSBs of SEGSPACE are less than or equal to the number of bytes prefetched during this cycle, then comparator 122 asserts its output 126. If the 29 MSBs of SEGSPACE are all ones, the assertion of line 126 indicates that the last instruction byte in the segment has been retrieved into the prefetch stage (it does not matter whether it is in prefetch buffer 0 or prefetch buffer 1).
  • the output of register 104a also is provided to detect-all- l's circuit 110.
  • circuit 110 detects that all 29 MSBs of the SEGSPACE value are 1, it asserts line 112.
  • a detection of all l's in the 29 MSBs of the SEGSPACE value in register 104a indicates that the latest instruction or instructions prefetched are at an address location that is within 8 bytes of the segment limit and, thus, the signal on line 126 indicates whether the last instruction byte in the segment has been loaded into the prefetch stage. Accordingly, the SPACE- WITHIN-EIGHT signal on line 112 is used to validate the signal on line 126.
  • the signal on line 126 is ANDed with the output 112 of DETECT- ALL-ONES circuit 110 by AND gate 130.
  • the output of AND gate 130 sets the LIMIT HIT latch 92.
  • output 126 of comparator 122 and output Tl 2 of DETECT-ALL-ONES circuit 110 are relevant, not only during sequential addressing after a branch, but even during the cycle in which the branch address is first loaded into the registers 104a and 104b.
  • the branch address is the address of the first byte after the branch.
  • circuitry shown in Figure 4 is identical to circuitry shown in Figure 3 and, therefore, will not be described again.
  • circuit elements in Figure 4 which are identical to circuit elements shown in Figure 3 are identified by the same reference numerals.
  • COUNT* (atty. docket no. NSC 1-66400); U.S. patent application Serial No. 08/ , entitled

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Abstract

L'invention porte sur un procédé et l'appareil correspondant permettant, d'une part, de détecter utilement et de signaler des violations de limite d'un segment d'instruction lors d'une phase de pré-lecture d'un processeur pipeline et, d'autre part, de ne signaler d'exception que lorsqu'il n'est plus possible de procéder à un déroutement autour de la violation de limite. Chaque fois qu'il se produit un déroutement dans un processeur, le cycle opératoire du processeur calcule le nombre d'octets se trouvant entre l'adresse de destination de déroutement et le dernier octet d'instruction valide pouvant être adressé de manière séquentielle à partir de l'adresse de destination de déroutement. La valeur est fournie à un registre lors de la phase de pré-lecture du processeur durant laquelle, à moins que ne survienne un autre déroutement et jusqu'à sa survenue, la valeur est décrémentée à chaque cycle du nombre d'octets ayant fait l'objet d'une pré-lecture durant ce cycle. S'il est procédé à un déroutement, la nouvelle adresse de destination de déroutement est fournie au registre à partir du cycle opératoire. Lorsque la valeur atteint zéro, la pré-lecture est arrêtée, mais le reste du pipeline peut poursuivre le déroulement normal des opérations jusqu'à ce qu'il n'y ait plus de possibilité pour une instruction de déroutement d'exister dans le pipeline entre la phase de pré-lecture et le cycle opératoire. Ce n'est qu'à ce moment, qu'une exception de limite de segment est signalée au cycle opératoire lors de l'impulsion suivante de compteur d'instruction
PCT/US1996/006146 1995-05-06 1996-05-01 Controle des limites d'une memoire d'instruction dans un microprocesseur WO1996035165A1 (fr)

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