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WO1996033466A1 - Realisation d'operations d'entree/sortie dans un systeme de processeurs multiples - Google Patents

Realisation d'operations d'entree/sortie dans un systeme de processeurs multiples Download PDF

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Publication number
WO1996033466A1
WO1996033466A1 PCT/EP1995/001454 EP9501454W WO9633466A1 WO 1996033466 A1 WO1996033466 A1 WO 1996033466A1 EP 9501454 W EP9501454 W EP 9501454W WO 9633466 A1 WO9633466 A1 WO 9633466A1
Authority
WO
WIPO (PCT)
Prior art keywords
bus
adapter
hierarchical
multiprocessor system
instructions
Prior art date
Application number
PCT/EP1995/001454
Other languages
English (en)
Inventor
Rolf Hilgendorf
Gottfried Goldrian
Rolf Fritz
Klaus-Jörg GETZLAFF
Original Assignee
International Business Machines Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corporation filed Critical International Business Machines Corporation
Priority to JP8531419A priority Critical patent/JPH09507939A/ja
Priority to PCT/EP1995/001454 priority patent/WO1996033466A1/fr
Publication of WO1996033466A1 publication Critical patent/WO1996033466A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges

Definitions

  • the invention is directed to a multiprocessor system with a hierarchically structured Input/Output (I/O) bus, wherein at the nodes of the I/O bus, adapters are provided which support I/O operations. Further the invention relates to an improved method for performing I/O operations in a multiprocessor system.
  • I/O Input/Output
  • I/O adapters In multiple processor computers known in the prior art, the processing units communicate with I/O adapters in order to start up or to perform I/O operations.
  • I/O instructions which can be for example "Sense/Control instructions", where a Control instruction transfers one word of data to an I/O adapter, and a Sense instruction causes an adapter to transfer one word of data back to a processing unit.
  • a particular aim for a system design is to make the occupation of the I/O buses minimum duration.
  • Fig. 1 is a schematic representation of a multiple processor computer system according to prior art approaches, which comprises a hierarchically structured I/O bus system;
  • Fig. 2 and 3 show block diagram charts which depict the propagation of signals through several levels in a hierarchical I/O system; and Fig. 4 is a timing chart for a bus protocol illustrating the improved method according to the invention for handling a complex I/O bus structure as shown in Fig. 1.
  • Fig. 1 shows a prior art multiple processor computer system which comprises a number of processing units CPU_1 - CPU_n which are connected to a memory unit MEM consisting of several memory banks.
  • the processing units are also connected to a hierarchical I/O bus structure via a BUS ADAPTER_1 and by means of a single system BUS_1.
  • the I/O bus splits up into several tree-like sub-buses, each of them being connected to terminal bus partitions I/O ADAPT via a number of second-stage ADAPTERS_2.
  • This structure shows, only exemplary, the architecture of complex hierarchically structured I/O bus systems, whereby the shown structure can be extended by adding more layers of sub-buses at the bottom of the shown structure.
  • a possible solution in this situation can be that the Sense operation starts normally and frees BUS_1 after the Command is accepted by ADAPTER 1.
  • the Command then is driven to its destination location, e.g. one of the I/O Adapters on BUS_3. But the answer returnes back only to ADAPTER_1 and is stored there temporarily.
  • the processing unit which needs the result has to poll frequently ADAPTER_1 to find out if the result has already arrived and in case of it, finally fetches it from a pre-defined storage location in ADAPTER_1.
  • the described method therefore, puts a heavy load onto BUS_1.
  • ADAPTER_1 may deliver an interrupt signal to the processing units.
  • one or all processing units will react to the interrupt. If all processing units react, each of them has to stop its current program and to switch to an interrupt handler.
  • the interrupt handler has to sense all interrupt sources known to him and this way determine if some action has to follow or not. Sooner or later, all except the one processor which waits for the answer will turn back and continue their current programs. The processing unit which is waiting will complete its Sense/Control operation and may continue as well.
  • processing unit If only one processing unit is selected to react, it has to stop its current operation and to find the source for the interrupt. Then, from the data which are gathered from the interrupting unit, it has to determine which processing unit has to receive the interrupt to process it further.
  • ADAPTER_1 has to provide enough storage locations for the maximum number of Sense/Control instructions which can be concurrently active.
  • a Sense instruction can be rejected by a reject mechanism in case of no location being available.
  • a Sense/Control instruction to an I/O adapter breaks up into two operations, a Sense from a processing unit and a Control from the adapter transferring the answer.
  • a new operation for BUS_1, called Disconnected_Sense is defined.
  • the Sense/Control command is propagating through several levels in the hierarchical I/O system, where each level is freed by an early status signal (Fig. 3).
  • Fig. 3 an early status signal
  • a Control data word is transferred if the operation code specified is a control operation to an I/O adapter.
  • ADAPTER_1 interprets the command and after receiving the second cycle it sends an early status signal back to the issuing processing unit. This early status may be an Accept, an Error or a Reject signal. Alternatively, the command is accepted and preliminary stored in the ADAPTER_1, anyway. A Reject signal is sent if there is already a Sense operation pending for one of the I/O adapters connected to the same ADAPTER_2 as the I/O adapter which is currently tried to be accessed.
  • BUS_1 is disengaged for further operations.
  • the processing unit which issued the Disconnected_Sense instruction falls into a quiescent state where it awaits a Control Command from ADAPTER_1.
  • ADAPTER_1 takes up the command and the data received, adds a sequence number for identification and sends all down to the appropriate ADAPTER_2, e.g. using BUS_2. After sending this package, BUS_2 is free again. This is accomplished by sending an early status signal from ADAPTER_2 to ADAPTER_1.
  • ADAPTER_2 inspects the command, and transfers it to the appropriate bus, e.g. BUS_3, to which the addressed I/O adapter is connected. This bus is held occupied until the I/O adapter of destination puts out the answer. Meanwhile ADAPTER_2 transforms the command received into a Control command which is sent back to ADAPTER_1. Hereby the address of the source processing unit is transformed as to be the destination address for the Control command.
  • the appropriate bus e.g. BUS_3
  • ADAPTER_2 transforms the command received into a Control command which is sent back to ADAPTER_1.
  • the address of the source processing unit is transformed as to be the destination address for the Control command.
  • the answer of the I/O adapter of destination is a simple Status information.
  • a Sense command it is either the requested data word or an Error status.
  • the received answer is put as data to the Control prepared by ADAPTER_2 and then sent to ADAPTER_1.
  • ADAPTER_1 If the ADAPTER_1 receives the Control signal correctly, it requests BUS_1 and forwards the Control to the waiting processing unit. If the data transfer between ADAPTER_2 and ADAPTER_1 is erroneous, ADAPTER_1 sends a Control with a bad status indication to the waiting processing unit. In both cases, ADAPTER_1 resets an appropriate "sense pending" latch to allow for new sense commands.
  • Fig. 4 a timing chart of a bus protocol illustrating the improved method according to the invention is shown.
  • I/O bus structure which comprises three bus layers BUS_!, BUS_2 and BUS_3, it is referred to the foregoing Figures.
  • the three bus layers of this embodiment comprise different bus cycle times, respectively.
  • the invention can be also applied to a bus structure which provides an allover synchronous bus cycle.
  • the drawing exemplary shows the pending signals on these buses in case of an exemplary Disconnected-Sense operation, dependent on the time.
  • Disconnected-Sense instruction can be the content of a CPU register containing for example a memory address which defines a memory location in which incoming data from an I/O device of destination have to be stored.
  • ADAPTER_1 takes up and interprets this command and sends an early status command back to the issuing processing unit.
  • the processing unit which issued the Disconnected_Sense instruction falls into a quiescent state awaiting a control command from ADAPTER_1.
  • BUS_2 ADAPTER_1 sends this package down to the appropriate ADAPTER_2 which lies on the way to the adapter of destination. After sending this package also BUS_2 becomes free of signals.
  • the protocol of BUS_3 is illustrated for two exemplary cases.
  • the issuing processing unit delivered a Control command wherein a Control command CC followed by a data package, e.g. the ordered I/O operation or an address in the main storage, where data fetched by means of I/O shall be stored, are on BUS_3.
  • the I/O Adapt of destination delivers a status signal, e.g. an Accept of a command or a Not Accept due to an erroneous state or an already busy state of the Adapter.
  • the I/O Adapter of detination delivers data which describe the internal state of the destinated I/O Adapter.
  • the terminal I/O Adapteres can be SCSI controllers or Adapters, which communicate with I/O channels.
  • the processing units themselves provide logical circuits for handling Disconnected-Sense operations.
  • the issuing processing unit receives a correct early status word due to an acceptance of the command, a CPU internal Disconnected-Sense Pending latch is set.
  • This latch being set instructs the private L2 cache memory of the CPU to accept a Control command from ADAPTER_1 which is addressed to this CPU.
  • the L2 cache memory stores data into a register pair of the CPU and resets the Disconnected-Sense Pending latch.
  • a CPU microcode polls the Disconnected-Sense Pending latch and as soon as the latch is reset, the microcode continues to use data received or a bad status signal, respectively.
  • the microcode polling loop is time ⁇ out controlled, i.e. if the latch does not drop within a defined period of time, microcode polling is stopped and a special control, only for this purpose, is issued to clear the Disconnected-Sense Pending latch in ADAPTER_1 as already described above.
  • the sense-pending latch in ADAPTER_1 is set, when ADAPTER_1 drives a Sense/Control command on BUS_2. In case of a Reset, a sequence number comes back as answer and the sense-pending latch is reset.
  • BUS_2 In a problematic operation situation, like a Sense from a processing unit is not replied by the Adapter of destination, BUS_2 is temporarily blocked. Then the processing unit resets all of the pending latches of the Adapters on the bus path to the destination Adapter.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)

Abstract

L'invention se rapporte à des opérations E/S dans un système de processeurs multiples. Ces systèmes comportent une structure de bus E/S structurées hiérarchiquement, dans laquelle des adaptateurs se trouvent aux n÷ud des bus E/S, lesdits adaptateurs prenant en charge les opérations E/S. Les adaptateurs décident d'accepter ou non une opération E/S, et en cas d'acceptation, ils dirigent la transmission de l'opération à travers le bus E/S et disconnectent temporairement la ligne entre ce n÷ud et le n÷ud suivant du dispositif de bus E/S.
PCT/EP1995/001454 1995-04-18 1995-04-18 Realisation d'operations d'entree/sortie dans un systeme de processeurs multiples WO1996033466A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP8531419A JPH09507939A (ja) 1995-04-18 1995-04-18 マルチプロセッサ・システムにおける入出力オペレーションの実行
PCT/EP1995/001454 WO1996033466A1 (fr) 1995-04-18 1995-04-18 Realisation d'operations d'entree/sortie dans un systeme de processeurs multiples

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP1995/001454 WO1996033466A1 (fr) 1995-04-18 1995-04-18 Realisation d'operations d'entree/sortie dans un systeme de processeurs multiples

Publications (1)

Publication Number Publication Date
WO1996033466A1 true WO1996033466A1 (fr) 1996-10-24

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PCT/EP1995/001454 WO1996033466A1 (fr) 1995-04-18 1995-04-18 Realisation d'operations d'entree/sortie dans un systeme de processeurs multiples

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JP (1) JPH09507939A (fr)
WO (1) WO1996033466A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2338092A (en) * 1998-06-05 1999-12-08 Mitsubishi Electric Corp Data processing apparatus has processors in some or all layers of a hierarchical bus

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0059838A2 (fr) * 1981-03-06 1982-09-15 International Business Machines Corporation Système de traitement de données avec plusieurs processeurs centraux et dispositifs périphériques
US5269011A (en) * 1990-09-24 1993-12-07 Emc Corporation Dynamically reconfigurable data storage system with storage system controllers selectively operable as channel adapters on storage device adapters

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0059838A2 (fr) * 1981-03-06 1982-09-15 International Business Machines Corporation Système de traitement de données avec plusieurs processeurs centraux et dispositifs périphériques
US5269011A (en) * 1990-09-24 1993-12-07 Emc Corporation Dynamically reconfigurable data storage system with storage system controllers selectively operable as channel adapters on storage device adapters

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
"Advanced I/O structure in hierarchical multiprocessor system", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 36, no. 8, NEW YORK US, pages 415 - 417, XP000390277 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2338092A (en) * 1998-06-05 1999-12-08 Mitsubishi Electric Corp Data processing apparatus has processors in some or all layers of a hierarchical bus
GB2338092B (en) * 1998-06-05 2000-04-19 Mitsubishi Electric Corp A data processing apparatus and its data processing method
US6223236B1 (en) 1998-06-05 2001-04-24 Mitsubishi Denki Kabushiki Kaisha Hierarchical bus structure data processing apparatus and method with reduced data transfer volume

Also Published As

Publication number Publication date
JPH09507939A (ja) 1997-08-12

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