WO1995015580A1 - Semiconductor device - Google Patents

Abstract

Synapse can be formed from a smaller number of elements in a low-power semiconductor device, which realize a highly integrated neural network. Precise modifications of synapse weighting becomes possible and a neuron computer chip of a practical level can be accomplished. The semiconductor device includes a first electrode for charge injection, connected to a floating gate through a first insulating film; a second electrode for applying programming pulses, connected to the floating gate through a second insulating film; and a MOS transistor using the floating gate as its gate electrode, wherein the charge supplied from the source electrode of the MOS transistor sets the potential at the first electrode to a predetermined value determined by the potential of the floating gate, and charges are transferred between the floating gate and the first electrode through the first insulating film by applying a predetermined pulsating voltage to the second electrode.

Description

 Semiconductor device technology

 The present invention relates to a semiconductor device, and more particularly, to providing a high-performance semiconductor integrated circuit device for realizing a neural network computer (neuron computer). Another object of the present invention is to provide a high-performance semiconductor integrated circuit device for realizing a multi-value analog memory.

Background art

 Semiconductor integrated circuit technology is progressing at an astonishingly rapid pace.For example, taking dynamic memory as an example, 4 Mbit / s, 16 Mbit / s, etc. are already in mass production and have a capacity of 64 Mbits or more. Ultra-high density memory is also being realized at the research level. A 64 megabit memory has at most about 1.2 million MOS transistors integrated on a silicon chip of at most 1 cm square. Such ultra-high integration technology is applied not only to memory circuits but also to logic circuits, and various high-performance logic integrated circuits such as 32 to 64 bit CPUs have been developed. I have.

However, these logic circuits adopt a method of performing operations using digital signals, that is, binary signals of “1” and “0”. For example, when configuring a computer, the Neumann method is used. In this method, instructions are executed one by one according to a predetermined program. With such a method, very high-speed calculations can be performed for simple numerical calculations, but calculations such as bat- tane recognition and image processing require an enormous amount of time. Furthermore, they are very weak at information processing, which is what humans are best at, such as association and learning, and various software technologies are currently being researched, but tremendous results have been obtained. It is not at present. Here, in order to solve these difficulties at once, a computer that can study the functions of the brain of living organisms and perform arithmetic processing that mimics that function, that is, a neural circuit computer There is another trend of research to develop (neuron computer). Such research began in the 1940's, but has been very active in recent years. This is due to the fact that such neuron computers can be implemented in hardware as LSI technology advances. However, there are still many problems in making a neuron computer into an LSI chip using the current semiconductor LSI technology, and the reality is that little has been said about the practical application.

 The following is a description of where the technical problems in LSI implementation are.

 The human brain has an extremely complex structure and very advanced functions, but its basic configuration is very simple. In other words, it is composed of neurons with arithmetic functions called neurons, and nerve fibers that transmit the operation results to other neurons, so to speak, function as wiring.

 Figure 14 shows a simplified model of the basic unit structure of the brain. 1401a, 1401b and 1401c are neurons, and 1402a, 1402b and 1402c are nerve fibers. 1403a, 1403b, and 1403c are called synaptic connections. For example, a signal transmitted through a nerve fiber 1402a is called w. Weighted neurons

 Enter d 1 4 0 1 a. Neurons

1401a takes a linear sum of the input signal intensities, and when the total value exceeds a certain threshold, the nerve cell is activated and outputs a signal to the nerve fiber 1402b. If the sum is below the threshold, the neuron does not output a signal. When the total value exceeds the threshold and two eurons emit a signal, the neuron is said to have “fired”.

 In the actual brain, all of these calculations, signal propagation, weight multiplication, etc. are performed by electrochemical phenomena, and signals are transmitted and processed as electrical signals. The process of learning by humans is regarded as the process of changing the weight in synaptic connections. In other words, the weights are gradually adjusted so that the correct output is obtained for various combinations of input signals, and finally settled at the optimal value. In other words, human wisdom is imprinted on the brain as the weight of synapses.

Many neurons are interconnected via synapses to form one layer. These are known to be superimposed in the human brain in six layers. this The realization of such a structure and function as an LSI system using semiconductor devices is the most important task of realizing a force neuron computer.

Figure 15 (a) is a drawing illustrating the function of one neuron, that is, one neuron.In 1943, McCullock and Pitts (Bull: Math. Biophys. Vol. 5, p. 115 ( 1943)) as a mathematical model. At present, this model is realized with semiconductor circuits, and research on configuring neuron computers is being actively pursued. VV ₂ , V ₃ ,..., V _n are n input signals defined as, for example, voltage magnitudes, and correspond to signals transmitted from other neurons. w _v w ₂ , w ₃ ,..., w _n are coefficients that represent the strength of the connection between neurons. Biological: This is called a synaptic connection. The function of the neuron is to output `` 1 '' when the value Z obtained by linearly adding each input V- by weighting w _i (i = l to n) is larger than a certain threshold ν _ΤΗ *, In addition, this operation outputs “0” when the value is smaller than the threshold. If this is expressed by a formula,

 [Equation 1]

Z≡∑w, V (1)

As

^V out = ¹ (Z> V _TH *) (2)

o (zku v _TH- ) (3)

Becomes _c

Figure 15 (b) shows Z and V. _It shows the relationship of _ut , and outputs 1 when Z is sufficiently larger than V _TH *, and outputs 0 when Z is sufficiently smaller than V _TH *.

By the way, if we want to realize such a neuron by a combination of transistors, we need many transistors, and we need to perform addition operation by converting each signal to current value and adding them up. Current flows and consumes a great deal of power. This makes high integration impossible. This problem is due to the invention of the Neuron MOSFET (abbreviated as MOS) (inventors: Naoshi Shibata, Tadahiro Omi, Heihei No. 1) -1 41463).

The present invention is an epoch-making method that requires only one transistor to perform the main function of the function of the neuron, and furthermore, can add the voltage signal as it is, so that there is almost no power consumption. FIG. 16 (a) is a simplified view of an example of a MOS cross-sectional structure, wherein 1601 is a P-type silicon substrate, 1602 and 1603 are a source and a drain formed of an N + diffusion layer, and 1604 is a channel region. A gate insulating film (eg, SiO ₂ ) provided thereon, 1606 is a floating gate which is electrically insulated and is in a potential floating state, 1607 is an insulating film such as SiO ₉ , 1608 _{(G p G 2, Gg,} G 4) corresponds to the input of an input gate neurons.

 FIG. 17 is a further simplified drawing for explaining the operation. If the capacitance coupling coefficient between each input gate and the floating gate is C ^, and the capacitance coupling coefficient between the floating gate and the silicon substrate is C0, the potential Z of the floating gate is

Z = -w (V ^ V ₂ + V ₃ + V ₄ )… (4)

_W ≡C _G Z (C ₀ + 4 C _G )… (5) Here, V ₂ , V ₃ and V ₄ are input gates respectively

G is, a voltage input to the G _3, G _4, the potential of the silicon substrate to 0V, was to have been ie ground.

This MOS is a normal N-channel MOS transistor when the floating gate is regarded as a gate electrode. The voltage from the floating gate (the voltage at which the inversion layer is formed on the surface of the substrate) is expressed as V ^ *. then, 2> ¥ _1¾ * above Les ^ 405 O down, turn off the Z <V _TII *. In other words, if one MOS 1609 is used and an inverter circuit as shown in Fig. 18 is used, the function of one neuron can be easily expressed. 1610 and 1611 are resistors for forming an inverter, and 1612 is an NMOS transistor. Figure 19, V. _utl , V. _{Shows ut2} as a function of Z, z> v v for input _{T. ut0} outputs a high-level voltage of v _DD . That is, the state where the neuron is fired is realized. As shown in Eq. (4), the basic operation that the input to the neuron is added at the voltage level and the neuron fires when the linear sum exceeds the threshold is realized by a single M〇S. -ing Since the addition in the voltage mode is performed, the current flowing in the input section is only the charge / discharge current of the capacitor, and the magnitude is very small. On the other hand, in the inverter, a DC current flows when the neuron is fired. This is because the resistor 1610 is used as a load, and according to the above-mentioned invention (Japanese Patent Application No. 11-141463). This direct current can be eliminated by using a CMOS MOS gate.

FIG. 20 and FIG. 21 are diagrams illustrating an example of the CMOS configuration. Figure 20 schematically shows the cross-sectional structure of a CMOS neuron gate, where 2001 is a P-type silicon substrate, 2002 is an n-type well, and 2003a and 200 3b is an N + type source and drain, 204a and 200b are respectively a P + type source and drain, 205 is a floating gate, and 206a to d are respectively Input gate electrode. Reference numerals 2 0 7 and 2 0 8 denote insulating films such as Si 0 _{2 and the} like, and 2 0 9 denotes a field oxide film. FIG. 21 shows an example in which one neuron circuit is configured. 210 is a symbol of the CMOS neuron gate of FIG. 20. Symbols in FIG. Corresponds to the number. Reference numeral 201 denotes a CMOS inverter, and reference numerals 210 and 210 denote NMOS and PMOS transistors, respectively. Also, 210 is the output of the neuron. As described above, a single neuron can be configured with a small number of elements, and the power consumption is extremely low, so MOS is an indispensable element in realizing a neuron computer.

 However, to realize a neuron computer, it is necessary to configure another important element other than neurons, namely, synapses. Fig. 22 shows an example of the basic configuration of a new mouth circuit including synaptic connections configured by conventional technology.

Reference numeral 222 denotes a neuron circuit as shown in FIG. 18, for example, and reference numeral 222 denotes a wiring for transmitting an output signal of another neuron. Reference numeral 222 denotes a synapse connection circuit, which is a circuit for assigning weight to an input signal. Load resistor (R + RJ connected source follower connected to source 222 of NMOS transistor 222) It is a circuit. Therefore, when the output voltage ν _の of the fired neuron is applied to the gate electrode 222 of the NM OS transistor, a voltage of V _s — V _TH appears at the source ₂₂₂ (where V is _TH is the threshold voltage of the NMOS transistor 222. o

For example, if a MOS transistor with V _TH = 0 is used, the potential of the source 222 becomes equal to V _s, and this voltage is divided by the two resistors R and R _x , and the output voltage of the synapse coupling circuit And transmitted to neuron 222 by connection 222. The output voltage, V 'R ,, Z (R + R x) _{becomes, R X Z (R + R} x) becomes weighted signal voltage V. It will be hung on. The weight can be changed by making the value of _Rx variable.

FIG. 23 shows an example of a method of realizing a variable resistor. For example, if a constant voltage is applied to the gate of one MOS transistor 2301, this transistor acts as one resistor. The resistance value can be changed by changing the value of v6 _(J.

FIG. 23 (b) shows an example of a circuit for controlling the value of V, which is composed of a 4-bit binary counter 2302 and a D / A converter 2303. ing. The synaptic connection strength is represented by a 4-bit binary number, which is converted to an analog voltage by the DZA converter 2303 and output as a value. To enhance the synaptic causes the countdown © down the value of the counter by the control signal, it may be reduced to a value of [nu _66. Conversely, to weaken the synaptic connection strength, count up and increase the value of.

 Now, problems in the case of using the synapse connection circuit as shown in FIGS. 22 and 23 will be described below.

First, the first problem is that in Fig. 22 the voltage is divided by resistors to generate weights. In this method, the current is always kept flowing through this resistor to maintain the weighted output voltage, so that the power of V _s ² / (R + R _x ) is always consumed. In this case, even if the power consumption of the neuron 222 is reduced by applying the MOS, the power consumption of the entire circuit will never decrease. Consider a two-layer neural network with one layer consisting of n neurons. The number of spliced connections is n ² , and the number of synapses is overwhelmingly greater than the number of neurons. Therefore, as long as a synaptic connection circuit that must constantly supply current is used, constructing a practical-scale neural network requires excessive power consumption and is virtually impossible to design. It is not possible to reduce power consumption by increasing the value of R + _Rx sufficiently. The time constant for charging and discharging _ut becomes very large, and the operating speed of the synapse circuit will be significantly degraded.

 The second problem is the fact that the circuit shown in Figure 23 (b), which determines the weight of the coupling problem, requires a large number of elements and cannot be integrated. In order to construct a neural network having a learning function, the strength of each synaptic connection can be changed as needed, and the changed value must be stored. In Figure 23 (b), a 4-bit binary counter is used for this purpose, but this alone requires at least about 30 M0S transistors. Furthermore, many elements are required to construct a DZA converter. Furthermore, these circuits consume more power per synaptic connection, which is disadvantageous in terms of power consumption.

As a method for reducing the number of elements required for synapse configuration, a method using a nonvolatile memory such as a floating gate type EPR〇M or E ² PROM has been proposed. These devices change their values depending on the amount of charge in the floating gate, and thus can store weights in an analog manner based on the amount of charge. Since the weight can be stored by one transistor, each synapse circuit can be made smaller than the circuit of Fig. 23 (b). However, in order to read this out as a weight and multiply it by the output of the previous neuron, a considerably complicated circuit is still required. For example, a differential amplifier using two E ^ PROM memory cells is configured [D. Soo and R. Meyer, "A Four-Quadrant NMOS Analogue Multiplier," IEEE J. Solid State Ciruits, Vol. Sc-17, No. 6, Dec., 1982], the result of weighting is read out as a current signal. Not only can the circuit not be greatly simplified, but also because the weight is multiplied by constantly flowing current, the power consumption becomes extremely large, and it cannot be used for large-scale neural networks. . A more serious problem is shown in Figure 24.

Figure 24 (a) shows the threshold voltage (V _TH ) of an E ² PROM cell with a tunnel junction as a function of the number of pulses for writing data. The program voltage is 19.5 V, the pulse width is 5 msec. When a positive pulse is applied to the control electrode for programming, electrons are injected into the floating gate, and the threshold shifts in the positive direction. Conversely, when a negative pulse is applied, electrons are emitted from the floating gate, and the threshold shifts in the negative direction. As is evident from the figure, the threshold shifts greatly with the first pulse, and changes very little with subsequent pulses. This makes it impossible to adjust the weight of synapses to many levels by finely changing the threshold.

 The cause can be explained as follows.

 Figure 24 (b) shows how the number (n) of electrons injected into the floating gate changes over time when a positive program voltage is applied in a step function. It can be seen that many electrons are injected at the beginning of the voltage application and hardly increase after that. This is the basis for charge injection. Fowler-Nordheim Tunneling current flowing in the insulating film

 [Equation 2]

b

 I oc V "e x p (-1) (6)

This depends on the potential difference V between both ends of the insulating film according to the following equation. That is, if the number of electrons in the floating gate increases due to the initial tunnel current, the potential of the floating gate drops, and V decreases, resulting in an exponential decrease in the tunnel current. Because. In order to control the tunnel current to a constant value and accurately change the synapse weight, it is necessary to precisely control the magnitude and pulse width of the pulse voltage according to the number of charges in the floating gate. Is required. In short, it is almost impossible to construct a neural network with conventional technologies in terms of low power consumption, high integration, and synaptic weighting accuracy. Therefore, the neuron computer cannot be realized by the conventional technology.

 Therefore, the present invention has been made to solve such a problem, and the power consumption is very small, and a synapse connection can be realized with a small number of elements, a high degree of integration, a high accuracy of synapse weighting, It is an object of the present invention to provide a semiconductor device capable of realizing a low power consumption two euron computer chip. Disclosure of the invention

 The semiconductor device according to the present invention includes: an electrically insulated floating gate; a first electrode for charge injection provided via the floating gate and a first insulating film; At least one second electrode for applying a programming pulse provided via the insulating film of the first type, and at least one MOS transistor using the floating gate as a gate electrode, A mechanism for setting the potential of the first electrode to a predetermined value determined from the potential of the floating gate by a charge supplied from a source electrode of the transistor; and a predetermined voltage pulse applied to the second electrode. A mechanism for causing the transfer of electric charge between the floating gate and the first electrode through the first insulating film by applying Sign. Action

 In this semiconductor device, a synapse connection can be formed by a small number of elements, and the power consumption is extremely low, so that a highly integrated and low power neural network can be realized. Furthermore, it is possible to change the synapse weight value with high precision, and this will enable a practical level of neuron combiner chip to be realized for the first time. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a circuit diagram illustrating Embodiment 1 of the present invention. FIG. 2 is a circuit diagram illustrating Embodiment 1 of the present invention.

 FIG. 3 is a circuit diagram illustrating Embodiment 1 of the present invention.

 FIG. 4 is a circuit diagram illustrating Embodiment 1 of the present invention.

 FIG. 5 is a diagram showing measurement results of the circuit shown in FIG.

 FIG. 6 is a diagram showing an actual measurement data comparing the embodiment of the present invention and the conventional example. FIG. 7 is a circuit diagram illustrating Embodiment 1 of the present invention.

 FIG. 8 is a circuit diagram illustrating Embodiment 2 of the present invention.

 FIG. 9 is a circuit diagram illustrating Embodiment 3 of the present invention.

 FIG. 10 is a circuit diagram illustrating Embodiment 5 of the present invention.

 FIG. 11 is a circuit diagram illustrating Embodiment 6 of the present invention.

 FIG. 12 is another circuit diagram illustrating Embodiment 6 of the present invention.

 FIG. 13 is a circuit diagram illustrating Embodiment 7 of the present invention.

 Figure 14 is a model of the basic unit of the brain.

Figure 15 (a) is a conceptual diagram explaining the function of one neuron, that is, one neuron. Figure 15 (b) is Z and V. It is a graph showing the relationship of _u .

 FIG. 16 is a simplified conceptual diagram showing an example of the MOS structure.

 FIG. 17 is a diagram further simplifying the structure of FIG.

FIG. 18 is an inverter circuit diagram using the neuron element of FIG. FIG] 9 is a graph showing V _out in the circuit of FIG. 18, the V i _r as a function of Z.

 FIG. 20 is a diagram schematically showing a cross-sectional structure of a CMOS neuron gate. FIG. 21 is a circuit showing a configuration of one neuron circuit.

 FIG. 22 is a circuit diagram showing an example of a basic configuration of a neuron circuit including a synaptic connection using a MOS transistor according to a conventional technique.

 FIG. 23A is a circuit diagram showing an example of a method of realizing a variable resistor, and FIG. 23B is a circuit diagram showing an example of controlling the value of.

Figure 24 is a graph showing the threshold voltage (v _TH ) of an EP ROM cell with a tunnel junction as a function of the number of pulses for writing data. FIG. 23 (b) is a graph showing the time change of the number (n) of electrons injected into the floating gate when a positive program voltage is applied in a step function.

(Explanation of code)

 101, 801, 80Γ, 901, 1001, 1 101, 1306 Floating gate (gate electrode of NMOS transistor),

 102, 70 1, 802, 804, 902, 903, 1002, 1004, 1102 NMOS transistor

 103, 702, 803, 904, 1003, 1 103 PMOS Transistor

 104 105, 1 106 NMOS transistor,

106 806, 905, 1005 V _p electrode,

107 906, 1006 V _T electrode,

 108, 808, 907, 1007, 1 105, 1302 V E

 109 tunnel oxide film part,

 703 normal inverter,

 805, 1304 switching transistor,

 807 writing electrode,

 1 104, 1 104 'terminal,

 1 107 parts,

 1301 Neural network synapse,

 1307 electrode,

 1401 a. 1401 b, 1401 c neurons,

 1402 a, 1402 b, 1402 c nerve fiber,

 1403 a, 1403 b, 1403 c synaptic connections,

 1601 silicon substrate,

 1602, 1603 source and drain,

1604 gate insulating film, 1 606 floating gate,

 1 607 insulating film,

 1 608 input gate,

 1 6 1 0, 1 6 1 1 Inverter resistance, 1 6 1 2 MOS transistor,

 200 1 Silicon substrate,

2002 ゥ el,

 2003a sauce,

 2003b drain,

2004a source,

 2004b drain,

 2005 floating gate,

 2006 a-d Input gate electrode,

 2007, 2008 Insulation film,

2009 Field oxide film,

 20 10 CMO S neuron gate,

 20 1 1 Inverter of CMO S,

 20 1 2 NMOS transistor

 20 1 3 PMOS transistor,

20 1 4 Output terminal of neuron circuit,

 220 1 Neuron circuit,

 2202 Wiring for transmitting output signals of other neurons, 2203 Synapse connection circuit,

2204 NMOS transistor,

2205 gate electrode,

2206 sauce,

2207 connection,

230 1 MO S transistor,

2302 binary counter, 2303 DZA converter. BEST MODE FOR CARRYING OUT THE INVENTION

 (Example 1)

FIG. 1 shows a first embodiment of the present invention. In the figure, ν,... Are control signals, for example, v _DD or 0.

Reference numeral 101 denotes a floating gate, which is a gate electrode of the NMOS transistor 102. 103 is a PMOS transistor, and 104 and 105 are NMOS transistors. The gates of PMOS 103 and NMOS 104 are connected to the signal line, and the gate of NMOS 105 is connected to the signal line VS. V _p is an electrode for applying a programming pulse, and a floating gate

It is also used as an input gate for determining the potential of 101. Are also electrodes for applying a programming pulse. A floating gate Ichito 1 0 1, between the narrowing electrodes 1 07 write, for example, 1 0 OA thickness of S i 0 ₂ film Ri Contact with is formed, both the potential difference is sufficiently large, for example, 1 When the voltage drops to about 0 V, current flows due to the Fowler-Nordheim tunneling phenomenon, and the charge ^^ in the floating gate 101 changes. Here, the potential of the floating gate is set to 0

_F

0 _F ^S = (C _p Vp + C _T V _T + Q _F ) / (C _p + C _T + C ₀ )… (6)

Becomes Here, C _p is capacity between V _p electrode 106 and the floating gate 1 0 1, C _T is V _T electrode 1 07 and the capacitance between the floating gate, is a stray capacitance. The capacitance between the electrode 108 and the electrode 107 is _CE .

 Next, the operation of this circuit will be described.

For simplicity, the threshold of the NMOS 1 05 is to 0V, and also, can be ignored and C _T, as C ₀ C _p> C _£. First, when in the standby state,

That is, when v _p = V _E = 0, V, = V _s = V _DD , PMOS 103 is off, NMOSs 104 and 105 are on, and the circuit is equivalently as shown in Figure 2. I can write. Next, when V. = 0, PMOS 103 turns on and NMOS 104 turns off, and the circuit becomes equivalent to FIG. In this case, V _T terminal 1 07, NMOS transients Since the current flows from the power supply _VDD via the transistors 102 and 105, the potential rises and continues to rise until the NMOS transistor 102 turns off. Therefore, its final value is 0 _F ^S — V _TN *. Here, V _TN * is a threshold value as viewed from the floating gate of NMOS 102. At this time, the potential difference between the electrode 107 and the floating gate 101 is, assuming that 0 _F ^S — is within the range of the power supply voltage, regardless of the charge amount QF in the floating gate, Looking at the floating gate from the electrode _107, it becomes V _TN *. Thereafter, the V _s = 0, result to OFF NMO S 1 0 5, V _T terminal, a floating state while maintaining the potential 0 _F ^S -V _TN *. This is shown in FIG. In this state, when injecting electrons into the floating gate, if the program voltage is V _pp (for example, V _pp = 10 V-v _T ) and Vp Vpp, the tunnel oxide film portion 109 Is, assuming that — V _TN -is within the range of the power supply voltage, regardless of the amount of charge in the floating gate ^^, always look at the floating gate from electrode 107 and look at Vpp + (that is,

1 0 V) の同じ 電圧がかかるので、 一定のパルス条件を用いれば、 一定のトンネリングが生じ、 フローティングゲ一ト内の電荷量 Q Fに依らない一定量の電子がフローティング ゲート内に注入される。 また、 フローティングゲートから電子を引き抜く際に は、 プログラム電圧を V_PP' (例えば V_PP， となる電圧） とし

Since the same voltage (10 V) is applied, constant pulse conditions cause constant tunneling, and a certain amount of electrons are injected into the floating gate independent of the charge QF in the floating gate. When electrons are extracted from the floating gate, the program voltage is set to V _PP '(for example, the voltage that becomes V _PP ).

Assuming that V _E = V _pp ', the tunnel oxide film portion 109 also has 0 _F ^S —the charge amount in the floating gate if V _TN * is within the range of the power supply voltage. Irrespective of ^^, one V _pp '+ V _TN * (that is, −10 V) is always applied when the floating gate is viewed from the electrode 107, so if a constant pulse condition is used, a constant tunneling force Then, a certain amount of electrons is extracted from the floating gate regardless of the amount of charge in the floating gate (31 _1? ). When electrons are extracted from the floating gate, V _p = — Vpp After the injection or extraction (after applying the program voltage, and after setting the voltage of the electrode to which the program voltage was applied to 0 V), V ^ V ^ VDD (switching order does not matter) As a standby state.

By repeating this series of operations, it became possible to inject and extract a certain amount of electrons from the floating gate every time a single pulse under the same conditions. Figure 5 In the measurement results of the circuit shown in FIG. 1, which confirmed this, the floating gate Ichito voltage 0 _F ^S in the state of standby in bright operation theory on the horizontal axis, the Floating Nguge foremost vertical axis injecting a single pulse of the same conditions at the G voltage, it plots the variation a 0 _F ^S of the floating gate voltage when subjected to pull-out. In the measurement result circuit of Fig. 5, one 2.5 V was used as V _TN *, but 0 _F ^S — V ^ * was within the range of the power supply voltage, that is, one 2.5 V <0 _The change is constant at _F ^S <2.5 V. This is in contrast to the fact that the characteristic value 0 of the conventional E ² PROM decreases exponentially with respect to the floating gate voltage. The black arrow in the figure indicates the direction that changes as electrons are injected and bows are removed. Is a value other than that, that is, 0 _F ^S -V _TN * is out of the range of the power supply voltage, and the characteristic of the conventional E ² P ROM appears, and the force is not constant. Absent. This is because, on the contrary, it is possible to prevent the dielectric breakdown of the oxide film caused by excessive injection of charges into the floating gate or excessive extraction of charges. Furthermore, as a synapse of a neural network, when performing hardwire learning, the synapse weight value, that is, the amount of charge in the floating gate is automatically updated any more when it reaches the maximum or minimum. This is a very favorable result in the hardware learning algorithm.

In the measurement results of FIG. 5, as the V _T, -2. While the 5 V was used, even other threshold, only the region A 0 _r ^S becomes constant deviates, similar results are obtained. FIG. 6 shows actually measured data comparing both the conventional example and the present invention. In FIG. 6, after performing a series of injection operations once, the threshold value V _TH of NMOS 102 viewed from the electrode ₁₀₆ was measured. The change amount of the threshold value AV _TH and the change amount A 0 _F of the floating gate voltage are the same, and the following relationship is established with C being a constant.

Here, except for programming, v _p = v _E = o, but V _p and v _E may be other voltages. Furthermore, c _T , c ₀ c _n , and c _E were assumed to be negligible as c _T = c ₀ = 0, but this is for the sake of simplicity, and values of other conditions are used Needless to say, this is acceptable. Further, the threshold value of NMOS 105 is set to 0 V, but this may be another value. For example, assuming that the threshold value of NMO S 105 is V _TN , when V _TN > 0, the potential of electrode ₁₀₇ only increases up to V _s — V _TN at the maximum. No. For example, this may be _{achieved by} setting v _s to a value equal to or greater than v _DD by a bootstrap circuit or the like. Alternatively, a so-called CMO S switch shown in FIG. 7 may be used instead of the NMO S 105. In FIG. 7, Ί 0 1 is an NMOS transistor,

702 is a PMOS transistor, and 703 is a normal inverter. That is, according to the present invention, a floating gate type E "PROM non-volatile memory has conventionally been made impossible without an external control circuit because it depends on the potential difference between both ends of the Fowler-Nordheim tunneling current force isolation film. In each case, it is possible to control the amount of charge in the floating gate with a single pulse under the same conditions with high accuracy without using an external control circuit and with a simple circuit. In conventional neural ^networks , large amounts of time have been spent because external large computers used to monitor the amount of charge in each floating ^{gate of the} ROM and controlled with high precision. All that was needed was a single programming pulse, which greatly reduced the learning time.

 (Example 2)

 FIG. 8 is a circuit diagram illustrating a second embodiment of the present invention.

Figure 1 is different from, the floating gate Bok 1 01 in FIG. 1 and area with NMO S Bok run register, be separated in a region having a V _p and V _T, 2 two regions thereof, Suitsuchingu That is, they are coupled via the transistor 805, and the NMOS transistor 105 has been eliminated.

In the figure, ν_ · is a control signal, for example, v _DD or 0.

(CpVp+C_TV_T+Q_F) / (C_p+C_T+C₀) ' … (7) 80 1, 80 で are floating gates separated by a switching transistor 805. Reference numeral 80 denotes the gate electrode of the NMOS transistor 802. 803 is a PMOS transistor, and 804 is an NMOS transistor. Gate Ichito of PM_〇 S transistor 803, NMO S transistor 804 to the signal line of the Vi, the gate of the switching transistor 805 are connected to the signal line of V _s. V _p is Ri electrode der for programming pulse application, also used as an input gate Bok for determining the potential of the floating gate Ichito 80 1. V _{E is} also an electrode for applying a programming pulse. Between the floating gate 801 and the write electrode 807, for example, a thickness of 10 OA When the Sio ₂ film is formed and the potential difference between them is sufficiently large, for example, about 10 V, a current flows due to the Fowler-Nordheim tunneling phenomenon, and the amount of charge (31 _? Here, if the potential of the floating gate is 0 _F ^S ,

(CpVp + C _T V _T + Q _F ) / (C _p + C _T + C ₀ ) '… (7)

Becomes Here, C _n is capacity between V _p electrode 806 and the floating gate 801, C _T is the capacitance between V _T electrode 807 and the floating gate Ichito 801, the C _Q a stray capacitance. Further, the capacitance between the electrode 808 and the electrode 807 is _CE . Operation is lost NMOS 105 of Example 1, instead, only the switching bets Rungis evening 805 is _{applied, V p> V E, V} s, the V _T, the potential change of which electrode also together.

The principle is that if the switching transistor 205 is turned off, the floating gate is separated by two parts, 801 and 80 °, so that when electrons are injected or extracted, V _p or v _E Even if a programming pulse is applied to the NMOS 802, the potential of the gate 80 # of the NMOS 802 is constant. As a result, the value 0 _F ^S — ν _ΤΝ * read out to the 807 electrode is kept constant while the programming pulse is applied to V _p or. Therefore, the same effect as in the first embodiment can be obtained.

 (Example 3)

 FIG. 9 shows a third embodiment of the present invention.

Figure 1 is different from, the PMOS transistor 103 in FIG. 1 gate one gate electrode of the NMOS transistor 904 turns placed NMOS tiger Njisu evening 904 is connected to a signal line of V _s, and, NMOS transistor 105 is no longer That is.

(C_pVp+C_TV_T+Qp) / (C_p+C_T+C₀) … (8) Reference numeral 901 denotes a floating gate, which is a gate electrode of the NMOS transistor 902. 903 is an NMOS transistor. The gate of the NMOS 903 is connected to the V "signal line. _Vp is an electrode for applying a programming pulse, and is also used as an input gate for determining the potential of the floating gate 901. V _{E is} also an electrode for applying a programming pulse. H Between the loading gate 901 and the write electrode 906, for example, a SiO ₂ film having a thickness of 10 OA is formed. When the potential difference between the two is sufficiently large, for example, when the voltage becomes about 10 V, Fowler A current flows due to the Nordheim tunneling phenomenon, and the amount of charge in the floating gate 901. ! ^ Changes. Here, if the potential of the floating gate is 0 _F ^S ,

(C _p Vp + C _T V _T + Qp) / (C _p + C _T + C ₀ )… (8)

Becomes Here, C _p is capacity between V _p electrode 905 and the floating gate 901, C _T is V _T electrode 906 and the floating gate capacitance between one bets, C. Is the stray capacitance. Further, the capacitance between the V _E electrode 907 and the electrode 906 and C _E.

The operation is as follows. With the elimination of the PMO S103 and the NMO S 105 of the first embodiment, instead of the addition of the NMOS transistor 904, the potential change of any of the electrodes V _p , V _E , V _P , and v _T Is also the same.

The principle is that if the NMOS transistor 904 is turned off, the drain terminal of the NMOS transistor 902 is cut off from the power supply, so that when electrons are injected or the bow I is cut out, V _p or V _E the source terminal of NMO S 902 programming Nguparusu is be applied, i.e., the potential of V _T electrode 906 is constant. Thus, single V _TN * values ø read the 906 electrodes, V _p, or even while the Programmer ramming pulse V _E is applied remains constant. Therefore, the same effect as in the first embodiment can be obtained.

 (Example 4)

 In the first to third embodiments, the NMOS transistor having the floating gate is replaced with the PM〇S transistor, and the polarity of the transistor having the gate connected to the signal line of Vi is reversed, ie, the NMOS transistor Is replaced with a PMOS transistor, the PMOS transistor is replaced with an NMOS transistor, and the polarity of the two power supply lines is reversed, and the signal line Vi is also inverted. The effect of is obtained.

[Equation 3] Inversion V, ··· vT (Example 5)

 FIG. 10 is a circuit diagram showing a fifth embodiment of the present invention.

Figure 1 is different from, instead placed in the NMOS transistor 102 is PMOS tiger Njisu evening 1002 1, not the source terminal of the NMO S transistor 102 V _T electrode 107 in FIG. 1 in FIG. 1, PMO S transistor 1002 This means that the NMOS transistor 105 in FIG. 1 has been eliminated.

In FIG. 10, reference numeral 1001 denotes a floating gate, which is the gate electrode of the PMOS transistor 1002. 1003 is a PMOS transistor and 1004 is an NMOS transistor. The gates of PMOS 1003 and NMOS 1004 are connected to the signal line. The V _p is an electrode for programming pulse application, even if the input gate Bok for determining the potential of the floating gate Ichito 1001 used. V _{E is} also an electrode for applying a programming pulse. A floating gate Ichito 1001, between the write electrode 1006, for example, is formed with S i 0 ₀ film thickness of 100A, both sufficiently large potential difference, if example embodiment, when it is about 10V, A current flows due to the Fowler-Nordheim tunneling phenomenon, and the charge <3 _{}? In} the floating gate 1001 changes. Here, if the potential of the floating gate is 0 _F ^S ,

0 _F ^S = (CpV _p + C _T V _T + Q _F ) / (C _p + C _T + C ₀ )… (9)

Becomes Here, C _p is the capacitance between V _p electrode 1005 and the floating gate Ichito 1001, the C _T, capacitance between V _T electrode 1006 and the floating gate, the C _Q a stray capacitance. Further, the capacitance between the V _E electrode 1007 and the electrode 1006 and C _E. Operation, there is no NMO S 105 of the first embodiment, the signal line of V _P without any summer however the only, lambda ^, the potential change of V _p, v _E are identical. Note that the gates of PMOS 1003 and NMOS 1004 are connected to the signal line of Vi instead of V. Thus, the potential V _{T of the} electrode 1006 is V. = v _DD , that is,

v_T= v_DDとなっている力、 、

v _T = v _DD force _,,

When V _DD , that is, the inverted Vi-NDD, the potential of the electrode 1006 becomes ^ 1 V _TP- as in the first embodiment. However, VTP * is a PMOS transistor This is the threshold as viewed from 1002 floating gate. The positive program voltage is applied to V _p or v _E in this state.

This principle utilizes the fact that applying a positive voltage to the floating gate of the PMOS transistor 1002 turns off the PMOS transistor 1002, and then injecting or extracting electrons afterwards.

During came, V _p, or, the source terminal of the PMO S 1 002 be positive programming Nguparusu is applied to the [nu _[pi, i.e., the potential of V _T electrode 1 006 is constant. Yotsute thereto, 1 006 read to the electrodes value 0 _F ^S - V _Tp * is, V _p, or, even while the program pulse is applied to be kept constant. Therefore, the same effect as that of the first embodiment can be obtained.

 (Example 6)

FIG. 11 is a circuit diagram illustrating the sixth embodiment. As shown in this figure, it may be used as a differential. In FIG. 11, reference numeral 1101 denotes a floating gate, which is a gate electrode of the NMOS transistor 1102 and the PMOS transistor 1103. lambda, V- are each two terminals 1 1 04, 1 output voltage appearing at 1 04 'of the circuit, the electrode 1 1 05 are coupled through the capacitor C ^ C _0. 1 1 06 has a gate electrode of an NMOS transistor is connected to the signal line V _s. At V _C = V _DD , the NMOS 1106 is on, the potential of the floating gate ₁₁₀₁ is set to 0 _F ^S , and the threshold _{values of} the NMOS transistor ₁₁₀₂ and the PMOS transistor ₁₁₀₃ are ν _ΤΝ * , V _Tp *,

ときには、 V+= 0、 V— = V_DDとなり、 例えば、 Cj - C₉、 電極 1 1 05がフ ローティ ングであるとすると、 1 1 05の電位 V_Eは V_E= V_DDZ2になり、 V^ Oのときには、 V + = 0_F ^S— V_TN*、 V— =0_F ^S—V_Tp*となり、 1 1 05の 電位 は V_E= (20_F ^S— ν_ΤΙ — V_Tp*) Z2となり、 フローティングゲートの 電圧がある定数シフトした値が読み出される。 。 もし、 I V_TN* I = I V_Tp* Iで あれば、 V_E=0_F ^Sとなり、 電極 1 1 05には、 フローティングゲートの電圧が そのまま読み出される。

Sometimes, V + = 0, V— = V _DD . For example, if Cj-C ₉ and electrode 1105 are floating, the potential V _E of 1105 becomes V _E = V _DD Z2, at the time of the V ^ O ^{_{is, V + = 0 F S -}} V TN *, V- = 0 F S -V Tp * , and the 1 1 05 of the potential ^{_{V E = (20 F S -}} ν ΤΙ - V Tp *) It becomes Z2, and the value of the floating gate voltage is read by a certain constant shift. . If any _{IV TN * I = IV Tp *} I, V E = 0 F S becomes, the electrode 1 1 05, the voltage of the floating gate is read out as it is.

In the case of injecting electrons and punching out the bow I, the same operation as in the first embodiment can be obtained by applying an appropriate voltage as and performing the same operation as in the first embodiment. Further, it is needless to say that the portion of 107 may be completely replaced with the second to fourth embodiments. The same effect can be obtained with a circuit as shown in FIG.

 (Example 7)

 FIG. 13 is a circuit diagram illustrating the seventh embodiment. '

This electrode 1 0 8 in FIG. 1 of Example 1 as a neuron circuit 1 3 0 2 of CMOS les MOS Inba Isseki gate electrode, through the sweep rate Tsu quenching transistor 1 3 0 4, combined with the signal line V _E It was made.

 In this circuit, 1301 indicates a case where the circuit is used as a synapse of a neural network.

 When electron injection and bow I extraction are performed, switch transistor 1304 is turned on, an appropriate voltage is applied, and the same operation as in embodiment 1 is performed. Powerful.

To read the potential of the floating gate 1306, turn off the switch transistor 1304, float the electrode 1307, and set to 0 or V _DD. The value read by determines the output of neuron circuit 132.

 In 1307, a switch transistor for separating 1301 and 1302 may be provided.

 Further, 1301 may be used as a differential as in the sixth embodiment.

 In the above-described first to seventh embodiments, the program voltage application electrode may be plural. Having more than one allows for selective programming. Needless to say, more excellent effects can be obtained by appropriately combining the first to seventh embodiments. Industrial applicability

According to the present invention, a synaptic connection can be formed by a small number of elements, and the power consumption is very small, so that a highly integrated and low power neural network can be realized. Further Therefore, it is possible to change the synapse weight value with high precision, and this makes it possible to realize a practical level neuron computer chip for the first time.

Claims

The scope of the claims 1. An electrically insulated floating gate, a first electrode for charge injection provided via the floating gate and a first insulating film, and provided via the floating gate and a second insulating film. At least one second electrode for applying a programming pulse, and at least one MS transistor using the floating gate as a gate electrode. A mechanism for setting the potential of the first electrode to a predetermined value determined by the potential of the floating gate by a charge supplied from a source electrode, and applying a predetermined voltage pulse to the second electrode A semiconductor device having a mechanism for transferring charges between the floating gate and the first electrode via the first insulating film. .  2. The semiconductor device according to claim 1, wherein the first electrode and a source of the MOS transistor are connected via at least one switching transistor.  3. A first region having a gate electrode portion of the mos transistor of the floating gate, and a second region including a portion of the floating gate facing the first and second electrodes. 3. The semiconductor device according to claim 1, further comprising: a switching transistor provided in a region separating the first and second regions. 4.  4. The semiconductor device according to claim 1, wherein a drain of the MOS transistor and a power supply line are connected via at least one switching transistor.