[go: up one dir, main page]

WO1994015279A1 - Element de processeur a circuit integre pouvant etre mis a l'echelle - Google Patents

Element de processeur a circuit integre pouvant etre mis a l'echelle Download PDF

Info

Publication number
WO1994015279A1
WO1994015279A1 PCT/GB1993/002588 GB9302588W WO9415279A1 WO 1994015279 A1 WO1994015279 A1 WO 1994015279A1 GB 9302588 W GB9302588 W GB 9302588W WO 9415279 A1 WO9415279 A1 WO 9415279A1
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
register
instruction
registers
processor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/GB1993/002588
Other languages
English (en)
Inventor
Andrew Keith Betts
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University College London
Original Assignee
University College London
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University College London filed Critical University College London
Publication of WO1994015279A1 publication Critical patent/WO1994015279A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30069—Instruction skipping instructions, e.g. SKIP
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30112—Register structure comprising data of variable length
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30192—Instruction operation extension or modification according to data descriptor, e.g. dynamic data typing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/324—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address using program counter relative addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/342—Extension of operand address space
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/355—Indexed addressing
    • G06F9/3557—Indexed addressing using program counter as base address

Definitions

  • This invention relates to integrated circuits and, in particular, to library elements for integrated circuit fabrication. It finds particular application in a scalable microcontroller core element and is of use where intelligence must be added to a single-chip system in order to control other specialised circuits. Its functionality and size is variable over a very large range, with a minimum internal register size varying from 4 bits upwards.
  • the design is based on a simple but powerful set of primitive instructions which does not change, even though the scaling operation alters the width of internal memory, memory words and instruction words.
  • the design is such that a change in the choice of processor configuration may have a minimal impact on the software written for the processor. This feature makes it practicable to delay the final choice of processor configuration until late in the software design cycle, allowing an accurate and informed matching of processor size and functionality of the application in hand.
  • ASIC Application Specific Integrated Circuit
  • SMILE Scalable Microcontroller Library Element
  • a scaling factor, WSR Width of Short Register
  • the instruction set is invariant with respect to the scaling operation, and it will be possible to produce a particular version of SMILE by combining configuration information with a fixed set of core design files. This procedure is practicable and commercially viable because of the existence of powerful silicon compiler tools, and the use of such tools has allowed rapid implementation of the processor. Its unusual design flexibility allows the designer to match power, register size and chip area to a specific application, thus overcoming the problems cited above.
  • SMILE's functionality degrades gracefully with decreasing size, so that these two important design criteria may be conveniently traded against each other.
  • the low minimum scaling factor (4 bits) is an important feature of the design, since it allows small chip area to be achieved in applications where the- area dedicated to circuits other than the core is small, and where only limited processing power is required.
  • an integrated circuit including a scalable integrated circuit processor element having a register block including a plurality of registers for the temporary storage of binary data characterised in that each of said registers has a data width which is a multiple of a common scaling factor (WSR), said scaling factor having a minimum value of four.
  • WSR common scaling factor
  • Figure 2 is the corresponding memory map
  • FIG. 3 is the corresponding instruction format
  • Figure 4 shows change of parameters with scaling for different embodiments of the invention
  • FIGS 5 and 6 show configurations of specific examples
  • Figure 7 is a comparison of different processor elements.
  • GPR General Purpose Register
  • Registers are labelled local or global depending on whether they are automatically saved upon occurrence of an interrupt (i.e. they are local to an interrupt process) or not (i.e. they are seen globally). There is a minimum of one global and one local register of each type (i.e. short or long).
  • the Program Counter (PC), Stack Pointer (SP) and Status Register (SR) are members of the GPR set, and have the same status as the other registers.
  • a new SMILE process is started upon every interrupt, either synchronous or asynchronous, and each of these processes can access 2 WLR short units of memory directly.
  • the total addressable memory area for SMILE is considerably greater than this, however, at 2 2WLR short units of memory, since a Memory Configuration Register (MCR) is used to extend all memory addresses by WLR bits.
  • MCR Memory Configuration Register
  • This mechanism usefully extends the memory map for the smaller versions of SMILE, which would otherwise be rather poor in this respect, and provides a very large address space for larger configurations (see Table 1).
  • Two views of the SMILE instruction set are presented - one is primitive, the other is expanded.
  • the former view is closer to the hardware implementation of the processor, and facilitates an explanation of its operation.
  • the latter view will be the one seen by most programmers and programming tools, and conceals certain low-level details.
  • the primitive instruction set has ten instructions, eight addressing modes, and a highly regular format. Conditions may be specified with each instruction, but if omitted the condition "always" is assumed.
  • the design is straightforward and uncomplicated, as is essential if one is to be able to scale to a small processor size. It also has beneficial side effects. For example, the production of simulators and other software support tools for the processor is very easy indeed, and one can program at the primitive machine level without any difficulty, holding all the instruction set in one's memory. Hardware design, particularly for the control-path, is also facilitated.
  • the instruction set is complete with respect to the application area of embedded control, and it is also orthogonal, there being no redundant instructions. It should also be noted that the addition of application specific instructions is protected by the specification.
  • the full instruction set is contained in Table 2, with each instruction written in the form:
  • ⁇ fxy> ⁇ A x ,A y ⁇
  • ⁇ fop>,[ ⁇ arg>] ⁇ x and y represent the registers associated with the first and second arguments respectively.
  • Arguments ⁇ fma>, ⁇ fop> and ⁇ arg> depend on the MA and OP instructions, and are defined below. Square brackets ([]) indicate an optional item.
  • SR2 (the indirectly addressed status data) is only accessible through the A x field. If SR is used in the A y field, then SRI is assumed. Also, as a consequence, of the way in which the XC instruction is coded, XC cannot be used with SR2. From a programming standpoint, however, this restriction has virtually no impact.
  • the bits of the SRI register have the additional capability of adding user-defined status bits when WSR>4.
  • the advantage of storing user-defined information in these locations is that they will be automatically saved on interrupt, along with all other status information (in both SR1 and SR2).
  • the L, M and I flags are derived directly from the four main status bits, C, Z, 0 and N, and facilitate the tests "if less than", “if less than or equal” and if "lower or the same”.
  • the E bit is necessary for control of interrupts, and will be described below.
  • the S bit is set by every instruction, except "MA A X ,TB n " (test bit), which sets or clears S according to the result of the test.
  • the first seven instructions listed in Table 2 are standard, and have been specified in a completely uniform way. That is, each one may be used with the same combinations of x and y registers, the same addressing modes and the same conditions (with the exception already noted for ST that A y ⁇ y).
  • the manipulate instruction, MA has no A y field, but instead has a code, ⁇ fma> that indicates one of the following operations:
  • This one instruction, MA is used to perform a range of bit-manipulation functions. These functions are not only logically collected into one instruction, at a hardware level they are also implemented in a common module, the "manipulation unit". As will be discussed shortly the number of MA functions available depends upon the particular version of SMILE being implemented.
  • the XC (exchange) instruction is in fact a special case of ST (store), and allows a register to be swapped with x or (x).
  • the OP instruction contains a number of core functions that do not require register arguments; branch (BRA); jump to subroutine (JSR); jump with interrupt (JWI); and return from interrupt (RTI).
  • BRA branch
  • JSR jump to subroutine
  • JWI jump with interrupt
  • RTI return from interrupt
  • BRA JSR and RTI instructions are quite standard, while JWI is particular type of software interrupt. It has a double-long argument, half of which is used as the PC address for the start of the interrupt routine, the other half for a new Memory Configuration Register value.
  • a load-immediate operation may be performed by exploiting the fact that the Program Counter is a member of the GPR set:
  • DC 1234 ; DC define constant
  • the Program Counter will point to the location after that instruction which in this case is a constant, 1234. That constant is therefore loaded into register x (i.e. a register in the GPR set), and the PC is incremented past the constant to the next instruction by the post-increment of the instruction on the y register.
  • This principal may be extended to implement a jump instruction, as follows:
  • the decision was taken to specify displacement mode addressing for the y register in order to support function calls in high-level languages.
  • C for example, parameters are passed to a function using a frame pointer which is placed in a register, then parameters belonging to the function are accessed with offsets from that register.
  • a disadvantage of displacement mode is that, in many applications, instructions are frequently used with a zero displacement in order to achieve simple indirect addressing, and code space is 'wasted' on these zeros.
  • Ax x
  • each instruction may be associated with a condition is an important factor in minimising code density, as it is frequently possible to avoid test-and-branch operations. If it were only possible to associate conditions with control statements, for example, then the following code might be needed to set a flag bit: OP BRA,SKIP, if_carry
  • the S status bit is set by every instruction except "MA A x TBn" (test bit n). For this reason, the "if_set” condition (which tests the S bit, and is the default condition - see Table 3) is often referred to as “always”, and its complement, "if_not_set”, as "never". The purpose of this bit is therefore three-fold:
  • the AN instruction is first used to clear the S bit, which is in the SR2 register, described above.
  • condition "if_not_set” must be associated with the AD instruction to prevent the default “if_set” from being used which would cause the instruction not to be executed.
  • the "never” (if_not_set) condition has other uses. It has been mentioned that instructions are always executed by the execution unit of SMILE, but the results are only stored if the associated condition is met. A y and the status result of the operation are always stored, however. This fact allows us to use the "never” condition in conjunction with SU to perform a compare:
  • the value of the increment (or decrement in the case of the pre decrement mode) is set by the width of x.
  • the interrupt mechanism and priority system in an ASIC may be adapted to the application, and may be monitored and controlled using memory-mapped i/o. All that is specified for the core SMILE processor is, therefore, a method for globally enabling and disabling interrupts.
  • An "Enable Interrupt" bit, E is therefore included in the SR2 status register which, when set, enables interrupts. It is automatically cleared by an interrupt, and can also be set and cleared by normal instructions. Since SR2 is stacked when an interrupt occurs, the E bit is normally restored to 1 automatically when the RTI instruction eventually pops SR2.
  • a SMILE instruction is fetched by two successive memory accesses, and is therefore 2*WSR bits wide. Since WSR can vary from 4 upwards, the instruction register width varies also. This fact represents the greatest challenge facing the SMILE architecture, since the instruction set and addressing modes must not change as the processor is scaled. A minimum register configuration is therefore specified, together with information on how this minimum is to be supplemented as the register space becomes greater.
  • the instruction is split into four fields: instruction, addressing-mode, condition and registers. The former two fields are invariant, while the latter wax and wane according to the space allowed them by the configuration. Hence the number of testable conditions and the number of register combinations allowed with each instruction addressing-mode combination varies with WSR, and the processor functionality varies accordingly.
  • the achievement of the SMILE specification is that its instruction set is able to take full advantage of the possibilities offered by increases in the condition and register field widths, so that the design is effective for a wide range of WSR values.
  • Table 6 adds more detail to the chart data, showing the size of each of the four instruction register fields.
  • the four rightmost columns show the number of testable conditions, registers, MA functions and OP functions that could be implemented for the corresponding version of SMILE.
  • the number of testable conditions is a direct consequence of the width of the corresponding bit-field, as can be verified from columns 4 and 6 of the table, but noting that a bit is scavenged from the address-mode field for the OP instructions when WSR ⁇ 8.
  • the number of registers is not directly determined by the width of the register field in the instruction however, only the number of register combinations that may be specified with each instruction is limited.
  • the MA field consists of the two bits that would normally constitute the y address-mode, plus a portion of the register field (width WRF).
  • the number of MA functions is therefore two to the power of the resulting bit field width, WMF say, and the number of registers that these functions may be applied to is two to the power of the number of remaining bits (i.e. 2(2 (2+WRF-WMF) ).
  • WMF bit field width
  • the number of registers that these functions may be applied to is two to the power of the number of remaining bits (i.e. 2(2 (2+WRF-WMF) ).
  • WSR 8
  • the MA functions can therefore be applied to all registers, as specified by the x field.
  • the table shows that 5 and 3 bits have been used to code MA respectively, implying that these functions may only be applied to
  • coding of the OP instruction is straightforward for WSR ⁇ 8, and in this case the number of available functions is equal to the number of registers in the configuration.
  • the number of OP functions and the number of register combinations that may be used with the XC instruction becomes linked since, we recall, OP is coded as a subset of the XC codes. Both XC and OP use the code that would otherwise have been attributed to ST A x ,y (store with register addressing mode for y).
  • the number of codes available to share between XC and OP is therefore two to the power of the width of the register field (WRF), and it will be seen from the charts in Figure 4 and from Table 6 that the sum of the number of OP functions with the number of XC register combinations obeys this rule.
  • the impact of the changes to the instruction register of scaling may be concentrated into a single module of combinational logic, which takes as inputs the instruction register and the status registers (SR1 and SR2), and produces a set of signals that are independent of the scaling factor for the design.
  • the remaining logic in the control path is therefore protected from the details of allowed register combinations for particular implementations, for example, and simply receives the x register and y register addresses as separate signals.
  • Condition code logic may also be hidden in such a module, so that all the rest of the control path knows about the condition associated with a given instruction is whether or not it was satisfied: i.e. the combinational logic combines the condition field with current status information to produce a single bit flag. It can therefore be seen that the basic architecture of the processor will not change as WSR is varied, and that SMILE is, therefore, genuinely scalable.
  • the expanded instruction shown in Table 7 is converted into the primitive instruction set by a preassembler and is therefore the normal interface for assembler-level programmers and compilers.
  • the preassembler can be used to 'replace' instructions that are not present in the primitive instruction set of the smaller SMILE configurations (such as ST A x ,y). It is also used to provide two extra addressing modes for A y , and to expand the manipulate (MA) and control (OP) instructions into a more familiar form.
  • pre-assembler it is important to distinguish between the pre-assembler presented here and a simple macro-preprocessor (eg. m4 on UNIX).
  • the latter tool is also useful in conjunction with the primitive SMILE assembler, for implementing the increment, decrement and compare macros given in an earlier section, for example.
  • macros could not be viewed as instructions that fitted into the regular SMILE instruction set, since they rely on the use of particular conditions for their operation, and could not themselves be used with a condition field.
  • the pre-assembler is concerned with expanding the instruction set and increasing its uniformity, rather than simply producing shorthand versions of commonly used, code segments.
  • the preassembler makes all conditions available to all instructions. If, in a given configuration, the i f_negati ve condition is not available for SUB, for example, the preassembler may translate:
  • Absolute mode instructions in the programming model are implemented in the primitive machine by replacing:
  • next_addr is the address after the instruction. Calculation of the displacement can be done at link time.
  • the objective of the SMILE project is to be able to define all the different possible configurations for the processor from a file that defines a small number of configuration parameters.
  • a generator linked to a silicon compiler will use this configuration file to produce a particular version of the processor.
  • 20-bit instruction and status words allows all the possible facilities of SMILE to be implemented together, in a straightforward way.
  • No Memory Configuration Register is included in this example, since the address bus is 20 bits wide, allowing programs to address 1M 10-bit memory elements. There are 32 registers and, since 10 bits are reserved for specifying the x and y registers in the instruction, any register may be combined in an operation with any other register. Furthermore, since 4 bits are available for specifying a condition, all 16 possible conditions may be used with any instruction. For the
  • the MA function to implement is coded into the address-mode and the y-register field (which is independent of the x-register field). This provides 7 bits which is more than enough to code the desired MA functions (TB0..9, SB0..9, CB0..9,
  • the SMILE4 example shown in Figure 6 is important, as it shows the smallest size that SMILE can be scaled to, and this configuration should therefore be of great use in applications requiring only modest added intelligence.
  • An MCR is included in this example, which effectively increases the addressable memory space from 256 nibbles to 64K nibbles. Note however that any one process can only address 256 nibbles directly, and that it must perform a JWI instruction in order to access nibbles that have been mapped to a different process.
  • a map (not shown) is therefore constructed to specify this mapping, treating L1 and SO as working registers, and ensuring that as many operations may be applied to them as possible. Difficulty in accessing certain register combinations is, in fact, substantially alleviated by the fact that registers are also accessible through the memory map, and can therefore be addressed using the absolute addressing mode of the extended instruction set.
  • condition field has shrunk to zero width. This means that only one (2°) condition may be specified with all instructions, except OP. For OP instructions, one bit of the address-mode field is unused and may be scavenged for use as a condition bit. This means that the critical control functions, BRA, JSR,
  • JWI and RTI may have two conditions associated with them, allowing normal program control. Note that these are the only four functions that the OP instruction possesses for this configuration. This is because it uses the codes corresponding to ST SR,y, of which there are only 4 possibilities, corresponding to the 4 possible combinations of registers.
  • the MA function to implement is coded into the address-mode and one bit of the register field.
  • code density is a critical parameter, since program memory is on-chip, and therefore contributes to the die size.
  • the benchmark code segments for different processors have been expressed in bits, thus eliminating any distortion of the results by differences in the processors' memory widths.
  • the results shown in Figure 7 represent the sum of the benchmark code segments for each processor, and it is interesting to notice that the range of code densities is quite modest. The majority of values lie within 157. of the average, the exceptions being the older Motorola designs.
  • the configurations of the SMILE processor represented in the figure have minimum register sizes of 4 (SMILE4), 6 (SMILE6) and 8 (SMILE8), and it can be seen that their code densities compare very favourably with their more established colleagues.
  • the functional specification of the scalable microcontroller allows scaling down to a memory size of 4 bits.
  • the use of this design in combination with silicon compilation tools makes it practical to match the size and functionality of a processor core to a given application, without having to maintain a number of independent processor designs in an ASIC library.
  • Features of the design include: a general-purpose register block containing all addressable registers, all of which have equal status, a primitive set of ten instructions with eight addressing modes: an extended instruction set' with four additional addressing modes (created by pre-assembler software), a condition field for every instruction. Simulations and comparisons with commercially available microcontrollers indicate that the instruction set is complete with respect to the application area of embedded control and that the SMILE design is competitive in terms of code density and execution speed.
  • the invention finds particular application in the field of medical implants and also in the telecommunications industry as an intelligent subsystem controlling signal processing circuits.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

Circuit intégré comprenant un élément de processeur à circuit intégré pouvant être mis à l'échelle dans lequel se trouve un bloc de registres formé de plusieurs registres destinés au stockage temporaire de données binaires, chaque registre ayant une largeur de données qui est un multiple d'un facteur commun de mise à l'échelle (WSR), ledit facteur de mise à l'échelle ayant une valeur minimum de quatre. La structure est basée sur un ensemble simple mais puissant d'instructions primaires qui ne change pas même si l'opération de mise à l'échelle modifie la largeur de la mémoire interne, les mots de la mémoire et les mots des instructions.
PCT/GB1993/002588 1992-12-18 1993-12-17 Element de processeur a circuit integre pouvant etre mis a l'echelle Ceased WO1994015279A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB929226463A GB9226463D0 (en) 1992-12-18 1992-12-18 Integrated circuits
GB9226463.9 1992-12-18

Publications (1)

Publication Number Publication Date
WO1994015279A1 true WO1994015279A1 (fr) 1994-07-07

Family

ID=10726848

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB1993/002588 Ceased WO1994015279A1 (fr) 1992-12-18 1993-12-17 Element de processeur a circuit integre pouvant etre mis a l'echelle

Country Status (2)

Country Link
GB (1) GB9226463D0 (fr)
WO (1) WO1994015279A1 (fr)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998012628A1 (fr) * 1996-09-23 1998-03-26 Arm Limited Compteur d'instruction d'un systeme de traitement de donnees
US5784602A (en) * 1996-10-08 1998-07-21 Advanced Risc Machines Limited Method and apparatus for digital signal processing for integrated circuit architecture
US5881259A (en) * 1996-09-23 1999-03-09 Arm Limited Input operand size and hi/low word selection control in data processing systems
US5881263A (en) * 1996-09-23 1999-03-09 Arm Limited Non-instruction base register addressing in a data processing apparatus
US5969975A (en) * 1996-09-23 1999-10-19 Arm Limited Data processing apparatus registers
WO2001042917A1 (fr) * 1999-12-09 2001-06-14 'ASSOCIATION MICROLOR', Association pour la promotion de la microélectronique en Lorraine Processeur configurable par l'utilisateur
WO2002010994A1 (fr) * 2000-07-28 2002-02-07 Delvalley Limited Processeur de donnees
KR101135837B1 (ko) 2009-09-02 2012-04-16 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 일정한 전력 밀도 스케일링을 위한 방법

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2013380A (en) * 1978-01-31 1979-08-08 Intel Corp Extended address single and multiple bit microprocessor
EP0248436A2 (fr) * 1986-06-04 1987-12-09 Hitachi, Ltd. Méthode et dispositif pour le traitement de données
EP0492970A2 (fr) * 1990-12-21 1992-07-01 Sun Microsystems, Inc. Procédé et dispositif pour étendre l'architecture d'ordinateur de trente-deux à soixante-quatre bits

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2013380A (en) * 1978-01-31 1979-08-08 Intel Corp Extended address single and multiple bit microprocessor
EP0248436A2 (fr) * 1986-06-04 1987-12-09 Hitachi, Ltd. Méthode et dispositif pour le traitement de données
EP0492970A2 (fr) * 1990-12-21 1992-07-01 Sun Microsystems, Inc. Procédé et dispositif pour étendre l'architecture d'ordinateur de trente-deux à soixante-quatre bits

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
ANDREWS AND FAWCETT: "The Zilog Z80000", IRE WESCON CONVENTION RECORD., vol. 29, no. 1/5, November 1985 (1985-11-01), NORTH HOLLYWOOD US, pages 1 - 9 *
N.MARGULIS: "i860 microprocessor internal architecure", MICROPROCESSORS AND MICROSYSTEMS, vol. 14, no. 2, March 1990 (1990-03-01), LONDON GB, pages 89 - 96 *
P.E.STANLEY: "Address size independence in a 16-bit mincomputer", 5TH ANNUAL SYMPOSIUM ON COMPUTER ARCHITECTURE,, 3 April 1978 (1978-04-03), pages 152 - 157 *
RASSET ET AL.: "A 32-bit RISC implemented in enhancement mode JFET GaAs", IEEE GLOBAL TELECOMMUNICATIONS CONFERENCE, vol. 1, 1 December 1986 (1986-12-01), HOUSTON,US,, pages 295 - 299 *
SOHIE AND KLOKER: "A digital signal processor with IEEE foating-point arithmetic", IEEE MICRO., vol. 8, no. 6, December 1988 (1988-12-01), NEW YORK, US, pages 49 - 67, XP011478626, DOI: doi:10.1109/40.16780 *

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998012628A1 (fr) * 1996-09-23 1998-03-26 Arm Limited Compteur d'instruction d'un systeme de traitement de donnees
US5881259A (en) * 1996-09-23 1999-03-09 Arm Limited Input operand size and hi/low word selection control in data processing systems
US5881263A (en) * 1996-09-23 1999-03-09 Arm Limited Non-instruction base register addressing in a data processing apparatus
US5881257A (en) * 1996-09-23 1999-03-09 Arm Limited Data processing system register control
US5969975A (en) * 1996-09-23 1999-10-19 Arm Limited Data processing apparatus registers
US5784602A (en) * 1996-10-08 1998-07-21 Advanced Risc Machines Limited Method and apparatus for digital signal processing for integrated circuit architecture
WO2001042917A1 (fr) * 1999-12-09 2001-06-14 'ASSOCIATION MICROLOR', Association pour la promotion de la microélectronique en Lorraine Processeur configurable par l'utilisateur
FR2802321A1 (fr) * 1999-12-09 2001-06-15 Ass Pour La Promotion De La Mi Processeur configurable par l'utilisateur
WO2002010994A1 (fr) * 2000-07-28 2002-02-07 Delvalley Limited Processeur de donnees
KR101135837B1 (ko) 2009-09-02 2012-04-16 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 일정한 전력 밀도 스케일링을 위한 방법

Also Published As

Publication number Publication date
GB9226463D0 (en) 1993-02-10

Similar Documents

Publication Publication Date Title
US6560692B1 (en) Data processing circuit, microcomputer, and electronic equipment
EP0780760B1 (fr) Dispositif de traitement de données avec extension du jeu d'instructions
KR100327776B1 (ko) 다중 명령세트를 사용하는 데이터 처리방법
EP1028382B1 (fr) Micro-ordinateur
US10514922B1 (en) Transfer triggered microcontroller with orthogonal instruction set
US5303358A (en) Prefix instruction for modification of a subsequent instruction
US6708268B1 (en) Microcontroller instruction set
KR0167005B1 (ko) 중앙처리장치
US5117488A (en) Microprogram controlled microprocessor having a selectively expandable instruction code length including independent description of operand addressing and a type of operation for an operand by single instruction in a common coding scheme
JP3805314B2 (ja) プロセッサ
WO1994015279A1 (fr) Element de processeur a circuit integre pouvant etre mis a l'echelle
US5742801A (en) Microprocessor to which additional instructions are added and instructions addition method thereof
CN1318957C (zh) 在程序控制流中实现改变的装置和方法
US7047396B1 (en) Fixed length memory to memory arithmetic and architecture for a communications embedded processor system
KR101497346B1 (ko) 명령으로서 데이터 값을 평가하기 위한 시스템 및 방법
JP2551167B2 (ja) マイクロコンピュータ
JP2556182B2 (ja) デ−タ処理装置
JP3570287B2 (ja) マイクロコンピュータ
US20030005269A1 (en) Multi-precision barrel shifting
US4866608A (en) Microprocessor with improved execution of instructions
JPH1020959A (ja) 低消費電力マイクロプロセッサ
JP2004005738A (ja) データ処理装置及び命令セット拡張方法
JPH02183341A (ja) マイクロコンピュータ
JPH06337791A (ja) プログラム変換装置およびプロセッサ

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP KR US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase