WO1994008356A1 - Semiconductor memory device - Google Patents

Abstract

This invention relates to a semiconductor memory device having input circuits to which external signals are connected. The memory device is equipped with a program circuit which includes fuses, wherein the type of memory is determined by a combination of blown and unblown fuses. The operation of the input stage of the input circuit of this memory device is controlled by the output of the program circuit. No external devices are necessary for selection of memory type by merely blowing the predetermined fuses after completion of a semiconductor fabrication process, without an increase in current consumed in the input circuit. Since there is no need for different photomasks for different types of memory, the mask management becomes easier. Further, management for individual types of memory becomes unnecessary in the production process, and therefore adjustment of the number of devices to be produced, stock adjustment and production management become easier.

Description

 Description Semiconductor storage device technology

 The present invention relates to a semiconductor memory device capable of switching from a common semiconductor substrate to a plurality of types after a semiconductor manufacturing process, and more particularly to a control method of an input stage of an input circuit thereof. Background art

 With the recent diversification of application fields of semiconductor memory devices, a method of manufacturing a plurality of types having the same storage capacity but different word configurations or different control functions from a common semiconductor substrate has been used.

 As an example, Fig. 9 is a diagram showing the external terminal arrangement of 256Kbit static random access memory (SRAM). The terminals are 15 address terminals from AO to A14, and the input / output from 101 to 1 08 It consists of 28 terminals, 8 terminals, VDD, VSS, and 3 control terminals. FIG. 9 (a) is a configuration diagram of an external terminal S having specifications including a write control terminal XWE, an output control terminal XOE, and a chip selection control terminal XC S as control terminals. Here, among the signal names used in each drawing and the description, those starting with X means signals of negative logic, and all control terminals in FIG. 9 (a) are of negative logic.

FIG. 9 (b) is a specification in which a positive logic chip selection control terminal CS2 is provided instead of XOE in the arrangement of FIG. 9 (a), and pin 22 is changed from XOE to CS2. Users of semiconductor storage devices The above two specifications are selectively used depending on the system configuration. In particular, the specifications with XCS1 and CS2 are used for battery backup applications.

 Fig. 7 is a circuit diagram showing a control signal input circuit of a conventional semiconductor memory device. Fig. 7 (a) is a control signal input circuit for XCS and X〇E specifications, and Fig. 7 (b) is a control signal input circuit for XCS1 and CS2 specifications. Is shown.

In FIG. 7A, a pad 20 is a bonding pad to which a chip selection signal XCS given from outside the device is connected, a pad, and a pad 22 are bonding pads to which an output control signal XOE is connected. The NOR gate 200 is an input stage for the chip select signal CS2 of positive logic.In this specification, CS2 is not used and one input of the NOR gate 200 is fixed to VDD, and the internal signal XC S2 a is always at the L level. The N 0 R gate 100 is an input stage for receiving the chip select signal XCS. One input is connected to Pad 20, and the other input is connected to XCS 2 a described above, and the internal control signal XC Output S 1 b. Here, since XCS2a is always at the L level, XCS1 is a signal synchronized with the external chip select signal XCS. N 0 R gate 300 is an input stage receiving an output control signal X 0 E. One input is connected to Pad 22 and the other input is connected to XC S 1 b described above. Outputs signal XOE a. Here, the NOR gate 300 operates in accordance with the XOE only when the chip select signal XCS is at the L level, that is, when the chip or the slave is selected. When the chip 3 is not selected, that is, when the chip is not selected, the NOR gate 300 operates. Operation is prohibited and the internal signal XOEa is fixed at H level. This is to prevent the memory device from outputting data overnight when it is not selected. It prevents unnecessary current consumption from flowing due to the potential fluctuation of the output control signal XOE. Similarly, the input stage of the address input circuit achieves low current consumption when the chip is not selected by taking the logic of the external address signal and XCSlb. Figure 7 (a) shows the operation waveform of the conventional semiconductor memory device with the circuit configuration shown in Fig. 8 (a) .The internal signals XCSlb, CS2b, and XOEa are used to form the internal control signals of the device. Used as a basic signal.

In the conventional semiconductor memory device shown in FIG. 7B, the positive logic chip selection control signal CS 2 is supplied to the pad 22, the negative input of the NOR gate 200 is supplied to the pad 22, and the input of the NOR gate 300 is The configuration is the same as that in Fig. 7 (a) except that one input is connected to VSS via a resistor. In this configuration, the internal signal XCS 2 a is the inverted signal of the positive logic chip selection control signal CS 2, and the internal signal XCS 1 b is a signal synchronized with XCS 1 when CS 2 is at the H level and 52 when the level is 52 The signal is fixed at H level. In addition, the internal signal XOEa is a signal of CS2 at H level and XCS1 at L level, that is, L level when the chip is selected, CS2 is at L level or XCS1 is at the H level, that is, H level signal when the chip is not selected. Becomes The operating waveforms of the conventional semiconductor memory device with the circuit configuration shown in Fig. 7 (b) are shown in Fig. 8 (b). As in Fig. 7 (a), the internal signals XCSlb, CS2b and XOEa are the internal control signals of the device. Is used as a basic signal for forming Here, in the conventional semiconductor memory device, the above-described switching of the type is performed by applying a part of a wiring photomask, for example, a metal mask to a common semiconductor substrate on which elements of an input circuit necessary for a plurality of types are arranged, as shown in FIG. ) And the specifications shown in Fig. 7 (b) for each product type. The type was changed during the process. In addition, the recognition of the product type after the end of the manufacturing process was performed visually by using a metal mask for each product type, placing a code or model number specific to the product type in the semiconductor device, and using a microscope. .

 Since the conventional semiconductor device is configured as described above, there are the following problems.

 Since the type switching is performed by partially changing the photomask, a large number of photomasks are required in accordance with the type development, which increases mask manufacturing costs and complicates mask management. Since the product type cannot be changed after the wiring process, production control by product type in the manufacturing process is required, and the production number cannot be adjusted after manufacturing.

 The present invention has been made in order to solve such a problem, and an object of the present invention is to provide a semiconductor memory device that can make necessary types after completion of a semiconductor manufacturing process without increasing manufacturing costs. I do. Disclosure of the invention

 A semiconductor memory device according to the present invention includes a program circuit including a fuse that can be cut, wherein an input circuit to which an external input signal is connected is controlled by the program circuit. The input stage of the predetermined input circuit is activated, and the type of the storage device is selected.

Also, a plurality of input circuits controlled by the program circuit may be connected to independent bonding pads, respectively. At this time, the type of storage device is switched by a combination of fuse cut of the program circuit. And the bonding are switched.

 A plurality of input circuits controlled by the program circuit may be connected to a common bonding pad, or a plurality of switch means controlled by the program circuit may be provided between the common bonding pad and the plurality of input circuits. May be provided. At this time, the type of the storage device is switched only by the combination of the fuse cutting of the program circuit.

 In any case, the input stage of the unnecessary input circuit is deactivated or the input potential is fixed, and no external bull-up or pull-down is required. It is possible to switch varieties without increasing the number of varieties.

 As described above, after the semiconductor manufacturing process is completed, a predetermined fuse is cut to select a product type, thereby eliminating the need for a photomask for each product type and facilitating mask management in accordance with reduction in mask manufacturing cost. In addition, product type management in the manufacturing process is not required, which makes it easy to adjust the number of production, inventory, and production management after manufacturing. Therefore, cost reduction and reduction of delivery time can be realized by reduction of management man-hour and management cost.

 In the semiconductor memory device of the present invention, when all the fuses of the program circuit are not blown, the input stage of the input circuit required for the type of the storage device which is the most shipped out of the plurality of input circuits controlled by the program circuit. It will be activated. In this way, by setting the type that does not blow the type selection fuse and set it to the type that has the largest shipment volume, cutting of the type selection fuse after the semiconductor manufacturing process is completed can be minimized, and the number of fuse cutting steps can be reduced. , Short delivery time can be realized.

Further, the semiconductor memory device of the present invention has a process for determining the type of the memory device. The fuse element of the program circuit has the same structure as the redundant fuse element that specifies the address of the redundant memory cell for repairing a defect. The cutting of the fuse element of the program circuit is performed in the same process as the cutting of the redundant fuse element.

 In addition, in the same process as the cutting of the fuse element in the program circuit, the unique dummy fuse is cut according to the type, and the type recognition of the device after the type selection is performed by checking whether the dummy fuse is cut or not, and determining whether the dummy fuse is cut. It may be performed by a combination.

 In this way, the structure of the fuse element in the program circuit is made the same as that of the redundant fuse, and the cutting of the fuse element in the program circuit is performed in the same process as the cutting of the redundant fuse. Since there is no need for an additional photomask, manufacturing process, or additional repair process or inspection process for cutting the fuse element, the present invention can be implemented without increasing manufacturing costs, inspection costs, manufacturing time, and inspection time. Can be implemented. Also, by cutting the dummy fuse at the same time as the cutting of the fuse element of the program circuit, it becomes easy to identify the type after the wafer is manufactured. Brief description of the drawings

 FIG. 1 is a circuit diagram of a semiconductor memory device showing a program circuit according to the present invention and an input circuit controlled by the program circuit.

 FIG. 2 is an explanatory diagram showing operation waveforms of the circuit shown in FIG.

FIG. 3 is a circuit diagram of a semiconductor memory device showing a program circuit according to the present invention and an input circuit in which a plurality of input circuits controlled by the program circuit are connected to a common bonding pad. FIG. 4 is an explanatory diagram showing operation waveforms of the circuit shown in FIG.

 FIG. 5 is a circuit diagram of a semiconductor memory device showing a program circuit according to the present invention, a plurality of input circuits controlled by the program circuit, and a plurality of switch means.

 FIG. 6 is an explanatory diagram showing operation waveforms of the circuit shown in FIG.

 FIG. 7 is a circuit diagram showing an input circuit of a conventional semiconductor memory device. FIG. 8 is an explanatory diagram showing operation waveforms of the circuit shown in FIG.

 FIG. 9 is an explanatory diagram showing an external terminal arrangement of a conventional semiconductor memory device.

 FIG. 10 is a circuit diagram showing a redundant decoder circuit for designating a redundant memory cell of a conventional semiconductor memory device.

 FIG. 11 is a layout diagram showing a configuration of a redundant fuse of a conventional semiconductor memory device.

 FIG. 12 is an explanatory diagram showing a sectional structure of a redundant fuse of a conventional semiconductor memory device. .

 FIG. 13 is a layout diagram showing a configuration of a dummy fuse for performing product type recognition according to the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

 [Example 1]

FIG. 1 shows a circuit diagram of a semiconductor memory device according to Embodiment 1 of the present invention. Pad 20 is a bonding pad to which a chip selection signal XCS given from outside the device is connected, Pad 22-1 is a bonding pad for an output control signal XOE, and Pad 22-2 is a positive logic chip selection. Bonding pad for control signal CS2. 1 is for semiconductor storage This is an example of a program circuit for selecting a product type, and consists of a low-resistance fuse element 10, a high-resistance 11, and inverters 12 and 13. Here, when the fuse is not blown, the connection point A between the fuse element 10 and the high resistance 11 is at the H level, so that the output B of the inverter 12 is at the L level and the output C of the impeller 13 is at the H level. On the other hand, after the fuse is blown, point A is at L level, and B and C are at H level and L level, respectively. Input stage receiving positive logic chip select signal CS 2 NOR gate 200 has one input connected to Pad 22-2, the other connected to output C of program circuit 1, and an input stage receiving output control signal X OE. NOR gate 300 has one input connected to Pad 22-1. Reference numeral 302 denotes an N-channel transistor having a gate connected to the output B of the program circuit 1, a drain connected to the input connected to the pad 22-1 of the NOR gate 300, and a source connected to the ground line. In the case of level, fix the input of Pad 22-1 to L level. Other circuits and connections in FIG. 1 are the same as those of the conventional device described in FIG. 7, and the description is omitted.

In FIG. 1, when the fuse element 10 of the program circuit 1 is not blown, the output B is at the L level, the output C is at the H level, the N-channel transistor 302 is off, the NOR gate 200 is inactive, and the NOR gate 200 is inactive. The output of 200 XCS2a is fixed at L level regardless of the potential of Pad22-2. Therefore, the internal signal XCS lb is a signal synchronized with the chip selection signal XC S given to Pad 20, and the internal signal XOE a is XC S 1 b at the L level, that is, the chip selection state, and Pad 22—1 Is low when the output control signal X0E applied to the L level is low. Where N channel Since the register 302 is always off, it does not limit the operation of X0E given to Pad 22-1. The operation waveform of the device at this time is shown in Fig. 2 (a), which is the same as the operation waveform diagram of the conventional device, Fig. 8 (a). By connecting to the bonding pad Pad 22-1 for the output control signal XOE with a bonding wire, the semiconductor memory device of XCS and XOE specifications shown in Fig. 9 (a) is realized. Also, no matter what level is given to Pad 22-2 or no signal is given, the internal operation waveform does not change, and no operating current or DC current flows through NOR gate 200.

On the other hand, when the fuse element 10 of the program circuit 1 is blown, the output B becomes H level and the output C becomes L level. The N-channel transistor 302 is turned on, the NOR gate 200 is activated, and the Pad 22 This is a gate for inverting the positive logic chip select signal CS2 provided to the second. Therefore, the internal signal XCS lb becomes a signal synchronized with XCS 1 when CS 2 is at H level, and becomes a signal fixed at H level when CS 2 is at L level. In addition, since the N-channel transistor 302 is always on, Pad 22-1 is fixed at the L level, and the internal signal X0Ea is a signal synchronized with the signal XCSlb. The operation waveform of the device at this time is shown in Fig. 2 (b), which is the same as the operation waveform diagram of the conventional device 8 (b), by cutting the fuse of the program circuit and bonding the 22-pin lead frame. By connecting to the bonding pad Pad 22-2 for the positive logic chip selection control signal CS2 with a wire, the semiconductor memory device of the XCS1 and CS2 specifications shown in FIG. 9B is realized. Where Pad22-1 is an N-channel transistor Since it is fixed at L level from 302, no operating current or DC current flows at NOR gate 300.

 As described above, in the first embodiment of the present invention, the input circuit to be activated is switched depending on whether or not the fuse of the program circuit is blown. Therefore, if the predetermined fuse of the program circuit is blown after one wafer process, the type of the storage device can be changed. Can be switched. This eliminates the need for a photomask for each product type, which is required in conventional equipment, and facilitates mask management to reduce mask manufacturing costs. In addition, product type management in the manufacturing process is not required, and the number of productions and inventory can be adjusted after manufacturing, making production management easier. Therefore, cost reduction and short delivery time can be realized by reducing management man-hours and management costs. At the same time, the input stage of the unnecessary input circuit has the potential fixed or inactive, so that the product can be switched without the need for external bull-up and pull-down.

In the first embodiment of the present invention, a plurality of input circuits are connected to independent bonding pads, respectively, and a lead frame receiving an external input signal is connected to the activated input circuit of the plurality of independent bonding pads. Since the type of the storage device can be selected by connecting to the pad, the present invention can be carried out without being restricted by the terminal position per lead frame shape of the storage device. In other words, even when the connection position of the lead frame is different for each product type because the package type or the terminal position on the package is different depending on the product type to be switched, the independent bonding pad is connected to the connection position of each lead frame. Therefore, the present invention can be implemented without being overly concerned with the bonding wire connection method. It is also possible to arrange the bonding pad as short as possible for each input circuit. The parasitic capacitance and parasitic resistance added to the element can be suppressed.

 [Example 2]

FIG. 3 shows a circuit diagram of a semiconductor memory device according to Embodiment 2 of the present invention. A pad 22 is a common bonding pad to which the output control signal X〇E or the positive logic chip selection control signal CS2 supplied from outside the device is connected. One input of the input stage NOR gate 200 and the input stage NAND gate 303 is commonly connected to Pad 22, and the other input is connected to the output C of the program circuit 1. Further, the internal signal XOEa is extracted from the NAND gate 304 to which the output of the NAND gate 303 and the output of the NOR gate 100 are connected. The other circuits and connections in FIG. 3 are the same as those in the conventional device described in FIG. 7, and the description is omitted. In FIG. 3, when the fuse element 10 of the program circuit 1 is not blown, the output C is at the H level, the NOR gate 200 is inactivated, and the output XC S2a is at the L level regardless of the potential of Pad 22. The fixed, NAND gate 303 is a gate that is activated and inverts the signal applied to Pad 22. Therefore, the internal signal CS la is a signal obtained by inverting the chip selection signal XC S given to Pad 20. If Pad 22 is used as the output control signal XOE bonding pad, the internal signal X〇E a When the output control signal XOE given to the level, that is, the chip selection state and given to the Pad 22 is at the L level, the signal becomes the L level. The operation waveform of the device at this time is shown in Fig. 4 (a), which is the same as the operation waveform diagram of the conventional device in Fig. 8 (a). By using it as XOE, the semiconductor memory device of XCS and XOE specifications shown in FIG. 9A is realized. Where the NOR gate 200 Since the H level is always supplied from the program circuit 1 as one input, the internal operation waveform does not change according to the signal level of Pad 22, and the operating current or DC current flows through the N〇R gate 200. Never.

 On the other hand, when the fuse element 10 of the program circuit 1 is blown, the output C goes to the L level, the NOR gate 200 is activated, and the signal applied to the Pad 22 is inverted. It is deactivated, and the output D is fixed at the H level regardless of the potential of Pad22. If Pad 22 is used as the bonding pad for the positive logic chip select signal CS2, NOR gate 200 will be the gate that inverts CS2, and the internal signal CS1a will be XCS1 when CS2 is at H level. When CS2 is at the L level, that is, when the chip is not selected, the signal is always at the L level. Since the NAND gate 303 is inactivated and its output D is always at the H level, the internal signal XOEa is a signal obtained by inverting the signal CS1a. The operation waveform of the device at this time is shown in Fig. 4 (b), which is the same as the operation waveform diagram of the conventional device, Fig. 8 (b). By using it as the selection signal CS2, the semiconductor memory device of XCS1, CS2 specification shown in Fig. 9 (b) is realized. Here, since the L level is always supplied from the program circuit 1 as one input of the NAND gate 303, the internal operation waveform does not change according to the signal level of the Pad 22, and the operating current is supplied by the NAND gate 303. Or, no current flows directly.

As described above, in the second embodiment of the present invention, the XCS and XOE specifications and the XCS1 and CS2 specifications depend only on whether or not the fuse of the program circuit 1 is disconnected. The kind of semiconductor memory device is switched in the same manner, and the bonding pads connected to the lead frame are common regardless of the kind. Here, as a typical example of the bonding pad area to which the input circuit is connected, together with the electrostatic protection circuit, one pad is required to have a size of about 500,000 square microns and a large area in the semiconductor device. In the second embodiment, the bonding pads are shared by connecting a plurality of input circuits to a common bonding pad, and the chip size and size of the storage device are reduced.

 [Example 3〗

FIG. 5 shows a circuit diagram of a semiconductor memory device according to Embodiment 3 of the present invention. Pad 22 is a bonding pad to which the output control signal X〇E or the positive logic chip selection control signal CS 2 applied from outside the device is connected. 2 is disposed between the bonding pad Pad 22 and the input stage NOR gate 200 and NOR gate 300 of the input circuit, and includes N-channel transistors 21 and 23 and P-channel transistors 22 and 24. Switch means comprising: The gates of N-channel transistor 21 and P-channel transistor 24 are connected to output B of program circuit 1, and the gates of N-channel transistor 23 and P-channel transistor 22 are connected to output C of program circuit 1, respectively. The conduction state of the switch means is controlled by the output of the program circuit. Input stage One input of NOR gate 200 is connected to Pad 22 via switch means 2, the gate is connected to output B of program circuit 1, and the source is connected to power supply line. It is connected to the drain of the channel transistor 202, and the other input is connected to VSS via a resistor. Input stage One input of NOR gate 300 is The gate is connected to the output B of the program circuit 1, the source is connected to the drain of the N-channel transistor 302 whose source is connected to the ground line, and the other input is connected to the internal circuit. Connected to signal XCS lb. The other circuits and connections in FIG. 5 are the same as those in the conventional device described in FIG. 7, and the description is omitted. In FIG. 5, when the fuse element 10 of the program circuit 1 is not blown, the output B is at the L level and the output C is at the H level, and the N-channel transistor 23 and the P-channel transistor 24 of the switch means 2 are conducting, and the N Channel transistor 21 and P-channel transistor 22 are turned off. At the same time, the gate is connected to the output B. Since the N-channel transistor 302 is turned off, Pad 22 is electrically connected to the input of the NOR gate 300, and one input of the NOR gate 200 is connected to Pad 22. The gate is fixed to the power supply potential by the P-channel transistor 202 connected to the output B. Therefore, the output XC S 2a of the NOR gate 200 is fixed at the L level irrespective of the potential of the Pad 22, and the NOR gate 100 is a gate that inverts the signal given to the Pad 20. At this time, the internal signal X CS lb is a signal synchronized with the chip selection signal XCS given to Pad 20, and if the output control signal X 0 E is connected to Pad 22, the internal signal X〇 E a becomes XCS 1 b L When the output control signal XOE given to the pad 22 and the pad 22 is at the L level, the signal becomes the L level. The operation waveform of the device at this time is shown in Fig. 6 (a), which is the same as the operation waveform of the conventional device in Fig. 8 (a). Using X and T as shown in Figure 9 (a); XCS and XOE specifications Semiconductor memory device is realized. Here, since the negative input of the NOR gate 200 is always supplied with the H level by the P-channel transistor 202, the internal operation waveform does not change according to the signal level of the Pad 22. No operating current or DC current flows.

On the other hand, when the fuse element 10 of the program circuit 1 is blown, the output B is at the H level and the output C is at the L level, and among the switch means 2, the N-channel transistor 23 and the P-channel transistor 24 are non-conductive, N-channel transistor 21 and P-channel transistor 22 become conductive. At the same time, the gate is connected to the output B. The P-channel transistor 202 is turned off, so that Pad 22 is electrically connected to the input of the NOR gate 200, and the other input of the NOR gate 300 is connected to Pad 22. However, the gate is fixed to the ground line potential by the N-channel transistor 302 whose gate is connected to the output B. Therefore, the NOR gate 200 is a gate for inverting the signal given to Pad 22, and the NOR gate 300 is a gate for inverting the internal signal XCS1b. If a positive logic chip select signal CS2 is connected to Pad22, the N〇R gate 200 is a gate that inverts CS2, and the internal signal XC S 1b is synchronized with 〇51 when C52 is at level 11. The signal CS2 is always at the L level, that is, the signal is always at the H level when the chip is not selected. Since one input of the NOR gate 300 is always at the L level, the internal signal XOEa is a signal synchronized with the signal XCS1b. The operation waveform of the device at this time is shown in Fig. 6 (b), which is the same as the operation waveform diagram of the conventional device in Fig. 8 (b) .The fuse of the program circuit is blown, and pin 22 is set to positive logic. Use as chip select signal CS2 As a result, the semiconductor memory device of the XCS 1 and CS2 specifications shown in FIG. 9B is realized. Here, since one input of the NOR gate 300 is always supplied with the L level by the N-channel transistor 302, the internal operation waveform does not change according to the signal level of the Pad 22. Or, no DC current flows.

 As described above, in the third embodiment of the present invention, the type of the semiconductor storage device of the XCS, 0 £ specification and # 31, CS2 specification is switched only by the presence or absence of the fuse cut of the program circuit 1, and the lead frame The same bonding pad is connected regardless of the product type. Therefore, in the third embodiment, the sharing of the bonding pad and the reduction of the chip size of the storage device are realized. Also, since only the input circuits necessary for operation are selectively connected by the switch means, the parasitic capacitance on the bonding pad, that is, the input terminal capacitance, is only the gate capacitance of the required input circuit and the required wiring capacitance. Become. In general, the input circuit that is switched when selecting a product due to circuit layout restrictions is not always located near the bonding pad to be connected, and the wiring indicated by Wl and W2 in Fig. 5 is several millimeters. Sometimes it becomes. For example, when a 3-mm metal wiring and one TTL-compatible NOR gate are connected, the parasitic capacitance of W1 is about 1 Bicofarad.In the third embodiment, the terminal due to this extra added capacitance is used. Increase in capacity-Product selection is possible without increasing current consumption and signal delay due to charging and discharging.

 [Example 4]

The semiconductor memory device according to the fourth embodiment of the present invention will be described again with reference to the circuit diagram of the semiconductor memory device in FIG. In Fig. 1, as described above, When the fuse element 10 of the program circuit 1 is not blown, it is set to XCS, X〇E specification. When the fuse element 10 is blown, it is set to XCS1, CS2 specification. In SRAM applications, the XCS 1 and CS 2 specifications are used for systems that use power-down mode, and are often used specifically for battery backup applications. On the other hand, in the specification with XOE instead of CS2, the activation of the output of the semiconductor storage device can be controlled by X〇E, and the data control of the data bus line of the system in which the outputs of multiple storage devices are connected in common is possible. Because it is easy to perform, it has a wide range of applications and accounts for more than 90% of the total SRAM shipments. In the fifth embodiment of the present invention, when the fuse of the program circuit is not blown, the specification is set so as to have the largest shipment of XOE, and only when the fuse is blown, the other type is set. In other words, it is not necessary to cut the fuse to set the X0E model with the largest shipment volume among multiple models, and it is only necessary to cut the fuse when setting to a model other than the X0E model. It will be possible to minimize the man-hour and time required for cutting the fuse after selecting the type. In addition to the above-mentioned SRAM example, by setting the type that will provide the largest shipment when the fuse of the program circuit is not blown, the number of steps and time required to cut the type selection fuse can be minimized. Becomes possible.

 [Example 5].

The semiconductor memory device according to the fifth embodiment of the present invention will be described again using the circuit diagram of the semiconductor memory device of FIG. 1 again. FIG. 10 shows a redundant decoder circuit of a conventional semiconductor memory device, and FIG. 1. A description will be given with reference to FIG. 12 showing the sectional structure of the redundant fuse. Of the present invention In the fifth embodiment, the circuit, structure, and layout of the ω fuse in the program circuit are the same as those of the redundant fuse.

In recent years, many semiconductor memory devices have redundant memory cells for improving the yield. FIG. 10 is a circuit diagram of a redundant decoder for designating a redundant memory cell of a conventional semiconductor memory device. The redundant program circuit 3 for programming a defective address, the redundant address decoder NAND gate 400, the NOR gate 401, and the redundant decoder are activated. It is composed of a redundant activation circuit 4. FIG. 10 illustrates an example of a redundant decoder that selects one redundant word line RWL by using complementary data of row addresses AO to A7 (address data of A2 to A7 is omitted). The redundancy program circuit 3 includes a low-resistance redundancy fuse element 30, a high-resistance element 31, invars 32 and 33, P-channel transistors 34 and 36, and an N-channel transistor 35. When the redundant fuse 30 is not blown, the connection point F AO of the redundant fuse element 30 and the high resistance 31 is at the H level, so that the output FA0N of the inverter 32 is at the L level, the output FA0P of the inverter 33 is at the H level, and P The channel transistor 34 and the N-channel transistor 35 are non-conductive, the P-channel transistor 36 is conductive, and the output R AO of the redundant program circuit 3 is fixed at the H level. On the other hand, when fuse 30 is disconnected, P-channel transistor 36 is turned off, P-channel transistor 34 and N-channel transistor 35 are turned on, and address data AO is connected to NAND gate 400. The redundancy activation circuit 4 includes a low resistance fuse element 40, a high resistance 41, and an inverter 42, and outputs an activation signal DENB for the redundancy decoder. In FIG. 10, when a redundant circuit is used, The fuse of the redundant program circuit 3 is appropriately cut to program the row address of the defective memory cell, and at the same time, the low-resistance fuse 40 of the redundant activation circuit 4 is cut. In this state, when the row address of the defective memory cell is input, all the inputs of the NAND gate 400 become H level and RPDAO 1 becomes L level. Similarly, RPDA23 to RPDA67 corresponding to the addresses A2 to A7 are also at the L level, and the redundant read line RWL output from the NOR gate 401 is selected. FIG. 11 is a layout diagram showing a redundant fuse 30, a high resistance 31, and a signal FAO lead-out portion of the redundant program circuit 3 of the conventional semiconductor memory device. The two-layer polysilicon and the one-layer metal (AL ). The redundant fuse 30 and the high resistance 31 are composed of the second layer of polysilicon (PLYB) 65, but the redundant fuse 30 has a pad open pad 66 to increase the thickness of the insulating film at the top of the fuse with an appropriate thickness in order to improve the cutting performance by laser. The high resistance 31 is formed by selectively not implanting impurities with the HR 67 after the PLYB lamination. One terminal of the redundant fuse 30 and the high resistance 31 has a single hole (THAB) 69, the first polysilicon (PLYA) 62 or 63, and the V DD metal 60 or GND metal 61 through the contact hole (CONT) 68. And the other terminals are connected to each other and drawn out as FAO via THAB 69 and PL YA64. The cutting of the fuse is performed by fusing PL YB with a laser.

FIG. 12 is a cross-sectional view taken along the line AB in FIG. 11, in which FIG. 12 (a) is a cross-sectional view in a state where the fuse is not blown, and FIG. 12 (b) is a cross-sectional view in a state where the fuse is blown. . In FIG. 12, 71 is an N-type semiconductor substrate, 72 is an element isolation layer such as LOCOS, 73 is an interlayer insulating film between PL YA and PL YB, 74 is an interlayer insulating film between PL YB and AL, 75 is a passivation film, and 76 is a protective film. In particular, as shown in FIG. 12 (b), the protective film 76 is entirely covered so as to cover the fuse blown portion, as shown in FIG. Applied.

 As shown in FIG. 1, the program circuit 1 is composed of a fuse element 10, a high resistance 11, and inverters 12 and 13, which are the redundant fuse elements of the redundant program circuit 3 shown in the conventional device diagram 10. 30, the high resistance 31, and the inverters 32 and 33 have the same circuit configuration. The circuit configuration can be the same, and the resistance values and dimensions of the fuse element 10 and the high resistance 11 can be the same. The layout of the fuse element 10 and the high resistance 11 can be the same as that of the conventional device shown in FIG. 11, and the cross-sectional structure of the fuse element 1 and the high resistance 11 is also the same as that of the conventional device shown in FIG. be able to.

 Therefore, by making the circuit, structure, and layout of the fuse element in the program circuit the same as those of the redundant fuse as in the fifth embodiment of the present invention, an additional photomask is required to manufacture the fuse element of the program circuit. A fuse element of a program circuit can be realized without using a wafer manufacturing process of a conventional device without using a semiconductor device or a manufacturing process. Therefore, in the fifth embodiment of the present invention, the present invention can be implemented without increasing the manufacturing cost and the manufacturing time.

 [Example 6〗

A semiconductor memory device according to Embodiment 6 of the present invention will be described. Embodiment 6 of the present invention relates to the fuse element 10 of the program circuit 1 shown in FIG. The cutting is performed in the same step as the cutting of the redundant fuse element 30 for designating the address of the redundant defective relief memory cell. The process of cutting the redundant fuse 30 of the conventional device will be described with reference to a cross-sectional view 12. The first pad opening step (hereinafter, PAD 1 step) for opening the upper part of the fuse and the bonding pad after the formation of the passivation film 75. First test step (TEST 1) to detect initial defective memory cell address using memory tester, etc., Repair step to cut redundant fuse corresponding to defective memory cell address by laser device, protection on top of device After forming the film 76, a second pad oven process (hereinafter, PAD 2 process) for opening the bonding pad portion, and a second test process (hereinafter, TEST 2) for selecting final non-defective products and defective products in the wafer state It is processed. Here, as described above, the semiconductor memory device of the present invention is a specific product among a plurality of products when all the fuses of the program circuit 1 are not cut, so that the defective memory cell address is detected by the TEST 1. Can be performed in the same manner as in the conventional apparatus. Further, since the fuse element 10 of the present invention has the same structure as the redundant fuse 30 of the conventional device, the fuse element 10 can be cut under the same condition in the same repair step as the cut of the redundant fuse 30. is there. Here, the cutting of the fuse element 10 in the repair process may be performed before the cutting of the redundant fuse 30 or after the cutting of the redundant fuse 30.

As described above, by cutting the fuse element 10 in the program circuit in the same step as the cutting of the redundant fuse 30 as in the sixth embodiment of the present invention, additional repair for cutting the fuse element 10 is performed. The fuse element can be cut without using the conventional process of manufacturing the conventional device without using any process or inspection process, and the present invention can be realized without increasing the manufacturing cost and manufacturing time. Can be implemented. Here, the present invention can also be implemented in a wafer manufacturing process without the PAD 2 process of forming the protective film 76 after the repair process in the above-described processes. I can do it.

 [Example 7]

FIG. 13 is a layout diagram of a semiconductor memory device according to Embodiment 7 of the present invention. In FIG. 13, 80 and 81 are metal patterns (AL) for product identification, and 82 and 83 are second-layer polysilicon (PLYB) corresponding to metal patterns 80 and 81, respectively. The dummy fuses 86, 87, 88 and 89, 90, 91 are formed together with the pad openings 84, 85. Here, the cutting of the dummy fuse is performed simultaneously with the cutting of the fuse element 10 in the aforementioned program circuit, and the dummy fuse corresponding to the type is cut. This makes it easy to identify the product type after one wafer is manufactured by visually observing the cut dummy fuse and the corresponding metal pattern for product type identification. For example, if the dummy fuses 86, 87, 88 are blown, the first specification of multiple types is used.If the dummy fuses 89, 90, 91 are blown, the second specification is used. If it has not been disconnected, it can be identified as a third specification. In the embodiment of FIG. 13, the dummy fuse has the same structure as the redundant fuse element, so that an additional photomask and a manufacturing process are unnecessary for manufacturing the dummy fuse. Since it can be performed in the same process as the cutting of the fuse, there is no increase in the repair process. Therefore, in Example 7 of the present invention, easy product type identification can be performed without increasing manufacturing cost and manufacturing time.

Industrial applicability

 As described above, the semiconductor memory device provided with the type switching by the program circuit including the fuse is not limited to the switching of the 0 ^ specification of 51 ^^ and the CS2 specification. As another application example, the present invention can be applied to the selection of an address input circuit and a data input / output circuit required for operation in switching between types having different word configurations with the same storage capacity. It is also applicable to switching of input circuits in switching operation modes such as page mode and static column mode of dynamic random access memory, and is also effective in switching positive logic and negative logic of input circuits. .

 Further, the configuration of various fuse circuits is not limited to a combination of resistors, and may be a circuit configuration combining a resistor and a transistor or a capacitance. The fuse is blown by a laser as an example, but may be blown by a current.

Claims

The scope of the claims 1. A semiconductor memory device having a plurality of input circuits to which an external input signal is connected, comprising: a program circuit including a cuttable fuse, wherein an input stage of at least one of the plurality of input circuits is a program circuit Wherein the input stage of a predetermined input circuit is activated according to a combination of the fuse disconnection, and the type of the storage device is selected.  2. The semiconductor memory device according to claim 1, wherein a plurality of input circuits controlled by a program circuit are respectively connected to independent bonding pads, and at least one of the plurality of input circuits is controlled by an output of the program circuit. The input stage of one of the input circuits is activated, and the remaining input circuits have the input potential of the input stage fixed or the input stage is inactive, and the lead frame receiving an external input signal is connected to the activated input circuit. A semiconductor memory device characterized in that the type of the memory device is selected by connecting to the bonding pad.  3. The semiconductor memory device according to claim 1, wherein a plurality of input circuits controlled by a program circuit are connected to a common bonding pad, and at least one of the plurality of input circuits is output by an output of the program circuit. A semiconductor characterized in that an input stage of an input circuit is activated, and the remaining input circuits and other input stages are inactive, and the common bonding pad is connected to a lead frame receiving an external input signal regardless of the type of device. Storage device. 4. The semiconductor memory device according to claim 1, further comprising a plurality of switch means disposed between the bonding pad and the plurality of input circuits, An input stage of the input circuit and a conduction state of the switch means are controlled by a program circuit, and an input stage of a predetermined input circuit is activated in accordance with a combination of cutting of a fuse of the program circuit, and a predetermined switch is provided. The input means of the input stage is fixed or the input stage is deactivated, the remaining switch means is non-conductive, and the type of storage device is selected. Semiconductor storage device.  5. In the semiconductor memory device according to claim 1, when all the fuses of the program circuit are not blown, the plurality of input circuits controlled by the program circuit are required for a type of the storage device having the largest shipment quantity. A semiconductor memory device, wherein an input stage of an input circuit is set to be activated.  6. The semiconductor memory device according to claim 5, wherein the input circuit controlled by the program circuit is an input circuit for an output control signal (output enable), and all the fuses of the program circuit are not blown. A semiconductor memory characterized in that at least an input stage of the input circuit for output control is activated and the output control terminal is provided. 7. The semiconductor memory device according to claim 1, wherein the fuse element of the program circuit that determines the type of the storage device has the same structure as the redundant fuse element that specifies the address of the redundant memory cell for repairing a defect. A semiconductor memory device characterized by the above-mentioned. 8. In the semiconductor memory device according to claim 1, disconnection of the fuse element of the program circuit that determines the type of the storage device is the same as disconnection of the redundant fuse element that specifies the address of the redundant memory cell for repairing a defect. A semiconductor memory device characterized by the following steps: 9. In the semiconductor memory device according to claim 1, a dummy fuse unique to a type is cut in the same step as the cutting of a fuse element in a program path, and the type recognition of the device after selection of the type is performed by cutting the dummy fuse. A semiconductor memory device which can be performed by the presence or absence of a fuse or by a combination of blown dummy fuses.