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WO1993022720A3 - Verfahren zur erzeugung des kehrwertes eines divisors durch schrittweise annäherung - Google Patents

Verfahren zur erzeugung des kehrwertes eines divisors durch schrittweise annäherung Download PDF

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Publication number
WO1993022720A3
WO1993022720A3 PCT/AT1993/000074 AT9300074W WO9322720A3 WO 1993022720 A3 WO1993022720 A3 WO 1993022720A3 AT 9300074 W AT9300074 W AT 9300074W WO 9322720 A3 WO9322720 A3 WO 9322720A3
Authority
WO
WIPO (PCT)
Prior art keywords
symmetrical
circuit
divisor
quotient
division
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/AT1993/000074
Other languages
English (en)
French (fr)
Other versions
WO1993022720A2 (de
Inventor
Cornell Vacariu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JOHANN KAMLEITHNER Firma
JOHANN KAMLEITHNER FA
Original Assignee
JOHANN KAMLEITHNER Firma
JOHANN KAMLEITHNER FA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by JOHANN KAMLEITHNER Firma, JOHANN KAMLEITHNER FA filed Critical JOHANN KAMLEITHNER Firma
Publication of WO1993022720A2 publication Critical patent/WO1993022720A2/de
Publication of WO1993022720A3 publication Critical patent/WO1993022720A3/de
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5332—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by skipping over strings of zeroes or ones, e.g. using the Booth Algorithm
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/4824—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices using signed-digit representation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/535—Dividing only
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/535—Dividing only
    • G06F7/537—Reduction of the number of iteration steps or stages, e.g. using the Sweeny-Robertson-Tocher [SRT] algorithm
    • G06F7/5375—Non restoring calculation, where each digit is either negative, zero or positive, e.g. SRT
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/02—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word
    • H03M7/06—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word the radix thereof being a positive integer different from two

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)

Abstract

Es wird ein neues Verfahren und eine rein hardwaremäßig gebildete Divisionsschaltung symmetrischer Architektur anhand der Figur beschrieben, die annäherungsweise, rekursiv und bidirektional einen Quotienten aus einem Dividenden und einem Divisor erzeugt. Somit kann die Berechnung mit dem höchstwertigen oder niederstwertigen Stellenwert oder gleichzeitig, in einer Parallelverarbeitung mit den beiden Extremen des Divisors/Dividenden/Quotienten beginnen. Deswegen besteht die Divisionsschaltung aus vier Teilen, wobei je zwei symmetrisch sind. Die linke Hauptschaltung (1), die mit der rechten Nebenschaltung (3) symmetrisch ist, verarbeitet den Divisor und steuert mittels der zwei Steuersignale D/I und AS die linke Nebenschaltung (2), die mit der rechten Nebenschaltung (4) symmetrisch ist und den Dividenden verarbeitet, um den Quotienten zu erzeugen. Die zwei symmetrischen Teile können unabhängig voneinander, also getrennt, arbeiten, womit es möglich ist, zwei verschiedene Divisionsoperationen mittels der zwei symmetrischen Hälften gleichzeitig auszuführen. Der Divisionsvorgang kann also bidirektional oder einseitig gerichtet (linksbündig bzw. rechtsbündig) durchgeführt werden. Die Operanden können in einem nicht-redundanten Format oder in einem mit Vorzeichen versehenen Digit-Format dargestellt werden, wobei mittels der Darstellungsstrategie der 'nicht-benachbarten nicht-Null Trits' der 'carry-ripple' Übertrag verhindert wird und der absolute Wert der Mantisse (M) nach dem Normalisierungsvorgang einem auf '1' zentrierten Bereich gehören wird.
PCT/AT1993/000074 1992-04-30 1993-04-29 Verfahren zur erzeugung des kehrwertes eines divisors durch schrittweise annäherung Ceased WO1993022720A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
AT89292 1992-04-30
ATA892/92 1992-04-30

Publications (2)

Publication Number Publication Date
WO1993022720A2 WO1993022720A2 (de) 1993-11-11
WO1993022720A3 true WO1993022720A3 (de) 1994-03-31

Family

ID=3502239

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/AT1993/000074 Ceased WO1993022720A2 (de) 1992-04-30 1993-04-29 Verfahren zur erzeugung des kehrwertes eines divisors durch schrittweise annäherung

Country Status (2)

Country Link
AU (1) AU3946593A (de)
WO (1) WO1993022720A2 (de)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3777132A (en) * 1972-02-23 1973-12-04 Burroughs Corp Method and apparatus for obtaining the reciprocal of a number and the quotient of two numbers
US4011439A (en) * 1974-07-19 1977-03-08 Burroughs Corporation Modular apparatus for accelerated generation of a quotient of two binary numbers
EP0353041A2 (de) * 1988-07-26 1990-01-31 THORN EMI plc Gerät und Verfahren zur Verarbeitung von Signalen mit Hilfe von modifizierter Vorzeichenziffernarithmetik

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3777132A (en) * 1972-02-23 1973-12-04 Burroughs Corp Method and apparatus for obtaining the reciprocal of a number and the quotient of two numbers
US4011439A (en) * 1974-07-19 1977-03-08 Burroughs Corporation Modular apparatus for accelerated generation of a quotient of two binary numbers
EP0353041A2 (de) * 1988-07-26 1990-01-31 THORN EMI plc Gerät und Verfahren zur Verarbeitung von Signalen mit Hilfe von modifizierter Vorzeichenziffernarithmetik

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
D. YUN ET AL.: "time-space optimal systolic array divider using redundant binary representation", PROCEEDINGS OF THE SECOND INTERNATIONAL CONFERENCE ON COMPUTERS AND APPLICATIONS, 23-27 JUNE 1987, BEIJING, CHINA., 1987, IEEE, NEW YORK, USA., pages 833 - 838 *
K. HWANG: "Computer arithmetic", 1979, J. WILEY & SONS, NEW YORK, USA. *
M. ERCEGOVAC ET AL.: "On-the-fly Rounding for Division and Square Root", PROCEEDINGS OF 9TH SYMPOSIUM ON COMPUTER ARITHMETIC, SANTA MONICA, CA, USA, 6-8 SEPT. 1989., 1989, WASHINGTON, DC, USA, IEEE COMPUTER SOCIETY PRESS, USA, pages 169 - 173, XP000135365 *
W. DALY ET AL.: "A High-Speed Arithmetic Unit Using Tunnel Diodes", IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS, October 1963 (1963-10-01), NEW YORK US, pages 503 - 511 *

Also Published As

Publication number Publication date
AU3946593A (en) 1993-11-29
WO1993022720A2 (de) 1993-11-11

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