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WO1993019528A1 - Circuits a verrouillage mos et synchronisateurs incorporant ces circuits - Google Patents

Circuits a verrouillage mos et synchronisateurs incorporant ces circuits Download PDF

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Publication number
WO1993019528A1
WO1993019528A1 PCT/EP1992/000643 EP9200643W WO9319528A1 WO 1993019528 A1 WO1993019528 A1 WO 1993019528A1 EP 9200643 W EP9200643 W EP 9200643W WO 9319528 A1 WO9319528 A1 WO 9319528A1
Authority
WO
WIPO (PCT)
Prior art keywords
node
inverter
channel
clocked
pass gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP1992/000643
Other languages
English (en)
Inventor
Jan A. Van Geloven
Stephen M. Kruse
Ronald L. Cline
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Philips Semiconductors Inc
Original Assignee
Philips Gloeilampenfabrieken NV
VLSI Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV, VLSI Technology Inc filed Critical Philips Gloeilampenfabrieken NV
Priority to PCT/EP1992/000643 priority Critical patent/WO1993019528A1/fr
Publication of WO1993019528A1 publication Critical patent/WO1993019528A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • H03K3/356052—Bistable circuits using additional transistors in the input circuit using pass gates
    • H03K3/35606—Bistable circuits using additional transistors in the input circuit using pass gates with synchronous operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/356147—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit using pass gates
    • H03K3/356156—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit using pass gates with synchronous operation

Definitions

  • the present invention relates to MOS integrated circuits and particularly to improved latches and flip-flops suitable for use in synchronizers.
  • the invention is particularly intended for implementation in a CMOS or BiCMOS integrated circuit. It is intended to be suitable for realization as a gate-array but could be realized in 'standard cell' or 'full-custom' forms.
  • bistable circuits there exists a wide variety of bistable circuits in CMOS technology and others for the handling of digital signals.
  • An important class of bistable circuits comprises those which receive asynchronous data and are controlled by a clock signal so that they may provide a data output in which transitions are synchronized to the system clock.
  • One example of such a circuit is a D-latch, which according to the state of a clock signal operates in a 'transparent' mode in which the input data transitions appear after some delay at the latch output and a latched mode in which the state of the output is maintained nothwithstanding transitions in the input data.
  • Another example is a D-type flip-flop wherein a transition of the input data causes a transition in the output data only at a time determined by a clock signal transition.
  • bistable circuit the term including latches and flip-flops
  • metastability a well known phenomenon known as metastability, which arises when a transition in the asynchronous input data occurs in time close to a transition in a controlling clock signal. Then the circuit samples an insufficiently well defined input signal and, instead of achieving one or other of its
  • metastable failure cannot be eliminated in digital systems wherein asynchronous data occurs or is permitted, but much effort has been devoted to reducing the incidence or consequences of metastable failure, particularly by a variety of expedients aimed at increasing the mean time between failure. Some of these expedients and the causes and nature of metastable failure are discussed, for example, by Horstmann et al, IEEE Journal of Solid State Circuits, Vol 24 No. 1 February 1989, pages 146 - 157, Kim et al, IEEE Journal of Solid State Circuits, Vol 25 No.
  • This may be regarded as having six measures or metrics, viz (i) set-up and hold time at the data input; (ii) propagation delay from a clock edge or transition to a transition in the direct (Q) output of the circuit; (iii) layout area of the circuit; (iv) power dissipation; (v) capacitance at the data and clock inputs; and (vi) metastability resolution time ( ⁇ ) .
  • measures or metrics viz (i) set-up and hold time at the data input; (ii) propagation delay from a clock edge or transition to a transition in the direct (Q) output of the circuit; (iii) layout area of the circuit; (iv) power dissipation; (v) capacitance at the data and clock inputs; and (vi) metastability resolution time ( ⁇ ) .
  • ⁇ metastability resolution time
  • bistable circuits particularly latches which may, for example, be employed in cascade to provide a master-slave flip-flop suitable as a synchronizer.
  • the invention is based on a latch which comprises a pass gate, preferably an n-channel gate, which is clock controlled, an inverting feed-forward buffer and a clocked inverter constituting a feedback buffer.
  • a 'particular embodiment of the invention is constituted by a master-slave flip-flop comprising two such latches arranged in cascade, being operable in complementary manner in response to a common system clock.
  • Such an implementation of a latch can be configured to employ a relatively small number of devices and the topology allows various parallel transistors to be added for increased loop gain within the latch, yet allows the minimization of the capacitance at important nodes of the circuit.
  • Such circuit enhancements especially within the master latch, improves the synchronizer performance of the overall flip-flop, without significantly degrading the normal propagation delay.
  • Figure 1 illustrates a CMOS synchronizer flip-flop constituted by two latches according to the invention
  • Figure 2 is a schematic illustration of a buffered clock supply for use with the synchronizer shown in Figure 1;
  • Figure 3 is an idealized diagram of part of a physical realization of the flip-flop shown in Figure 1.
  • FIG. 1 of the drawings illustrates a CMOS master-slave flip-flop composed of two cascaded D-type master and slave latches 1 and 2.
  • Each latch comprises a pass gate followed by an inverting feed-forward buffer with a clocked inverter for feedback.
  • the input coupler is preferably an n-channel pass gate, rather than either a clocked inverter (which would increase the propagation delay) or a complementary transmission gate having both p-channel and n-channel devices (which would increase the capacitance of the crucial resolving node, in this case a node mi ) .
  • a data input D is coupled to an input buffer 3, preferably constituted in this embodiment by a CMOS inverter, which is coupled by way of a pass gate 4 composed in this embodiment by an n-channel transistor of which the gate is coupled to receive the complement CLN of a clock signal.
  • the pass gate is connected to a master input node mi connected to the input terminal of a feed-forward inverting buffer 5, constituted by a CMOS inverter.
  • the output node m of this inverter is coupled to the input node mi by way of a feedback inverter constituted by a clocked inverter 6.
  • This inverter has p-channel transistors 6a and 6b disposed in series between the (positive) drain supply rail 7 and a central node 9 and n-channel transistors 6c and 6d disposed in series between the central node and the relatively negative source supply rail 8.
  • the devices 6a and 6d adjacent the supply rails receive the inverted clock signal CLN and the clock signal CL at their gates and the gates of the pair of transistors 6b and 6c are connected to the output node mo.
  • the slave latch 2 is topologically similar to the latch 1 and comprises an n-channel pass gate 10, an input node s_i , a feed-forward inverting buffer 11 between the node si and an output node so and a clocked feedback inverter 12.
  • the inverter 12 is configured in a manner similar to the inverter 6 but the clock inputs for the inverter 6 and the transmission gate are arranged in complementary fashion to those for the inverter 12 and the transmission gate 10 because the latch 2 is operated so that its latched mode occurs contemporary with the transparent mode of the master latch and vice versa.
  • the output node s_o of the slave latch is coupled by way of an output buffer 13 to provide an output Q.
  • Figure 2 illustrates a clock buffering circuit for the clock signal.
  • a nominally square wave clock signal CP is received at an input terminal and is coupled through an inverter 21 to provide a complementary clock output CLN and also by way of a further CMOS inverter 22 to provide a clock output CL.
  • the gate terminal of the n-channel pass gate (4 or 10) is controlled by a signal which is identical to the clock signal controlling the p-channel transistors (6a or 12a) in the clocked feedback inverter of the same latch.
  • the inverse or complementary signal controls the n-channel transistor (6d or 12d) .
  • this inverse or complementary signal CL is delayed relative to the signal CLN which controls the n-channel pass gate, owing to the propagation delay of the inverter 22.
  • the various devices shown in Figures 1 and 2 are accompanied by p/n legends having different coefficients.
  • the coefficient indicates the width of the respective channel, relative to normal width.
  • the ⁇ particular coefficients shown for p and n for the various devices are by way of example.
  • the p-channel transistor has twice the width of normal whereas the n-channel device is the same width as normal. It will be appreciated that, to balance the conduction difference between n-channel and p-channel devices due to differences in carrier mobilities, the p-channel devices are normally designed to be larger than the n-channel devices.
  • the p-channel device is made a two-times integral multiple of the n-channel to accomplish this balance.
  • a nominal balanced inverter is sized 2p/ln. It will be appreciated that other gate array embodiments may vary the ratio of the inverter 3 by an appropriate factor without departing from the basic function of the circuit.
  • the circuit as described is well adapted for implementation as a gate array and particularly for providing the devices with multiples of the normal width in order to achieve a variety of beneficial effects.
  • the pass gates 4 and 10 are provided in order to minimize the capacitance at the nodes which influence the resolution of a metastable condition, i.e. the master input node mi , the master output node mo and the slave input node s_i .
  • the width (and thus conductance) of pass gate 4 at the input to the master latch is increased to minimize the setup/hold characteristic of the synchronizer flip-flop.
  • the inverting buffer 5 in the master stage has both p and n transistors of extra width, in this embodiment composed of a plurality of parallel p-channel devices and n-channel devices respectively, in order to increase the ⁇ loop gain within the master latch. This has a direct effect on the behaviour of the latch when resolving a metastable condition.
  • Loop gain can be further increased by configuring the ' clocked feedback inverters 6 and 12 in a so-called 'non-cascode' arrangement, wherein the devices which are driven by the clock signals are the ones that are closest to the power rails 7 and 8.
  • These clocked transistors should be greater than nominal width in order to increase the gain of the clocked inverter. In a gate-array embodiment this would be constituted by multiple parallel devices, with the possibility of shared diffusions as previously described, to minimize the additional capacitance.
  • the actual plurality of such parallel devices is limited by the 'law of diminishing returns' , since additional transistors will increase overall stray capacitance, power dissipation, and latch area.
  • the synchronizer performance of the flip-flop is further enhanced by making inverter 5 symmetric with respect to devices 6b and 6c in the clocked inverter, and by having equal p and n transistor widths in these components of the master latch, the gain-bandwidth product being maximized when the p and n transistors are of equal width.
  • the inverters which determine the loop gain in the master latch are both sized 2p/2n.
  • the inverting buffer 11 in the slave stage 2 has increased width p and n devices. In this case however the channel widths are not increased by the same multiple, there being three p-channel devices and two n-channel devices. The purpose of this is to shift the switching point of the inverter.
  • the output of the master stage is metastable, it will linger at approximately (Vdd-Vss)/2, i.e. half way between the voltages of the drain supply rail and the source supply rail.
  • the inverter 5 and the clocked inverter 6 are arranged to have channel widths such that their switching point is at or near this balanced voltage.
  • the switching point is chosen to be lower than this balanced point, while the buffer has greater than nominal drive.
  • the level shifting serves to compensate for the degradation of a logic ' 1' level following the n-channel pass gate 10.
  • the p:n ratio and increased width of the inverter 11 devices both serve to reduce propagation delay during normal flip-flop switching, in addition to inhibiting the propagation of a metastable condition.
  • the diffusions adjacent the input node may be merged to decrease the capacitance at this node and thereby increase the switching speed, to reduce susceptibility to metastability.
  • the transistors in the master latch's feedback inverter may be constituted by multiple devices in order to increase the gain and thereby the switching speed.
  • the input buffer 3 is of nominal size to minimize setup/hold time and input capacitance, while the output buffer 13 is of nominal size to minimize propagation delay and to provide balanced rise and fall times on the Q output. '
  • the initial clock buffer 21 drives a larger capacitance than the second clock buffer 22, and it has a widened n-channel device to lower its switching threshold. On a rising transition of clock input CP the transition on internal clocks CLN and CL can thus be initiated more quickly.
  • Figure 3 illustrates in an idealized manner an n-channel pass gate, which has a polysilicon gate electrode 30 extending over a diffusion region 31 which is common to the multiplicity of devices constituting the pass gate and which is provided with a contact 32 (constituting the node mi or si ) and diffusion contacts (such as contact 33) for the multiple devices.

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  • Logic Circuits (AREA)

Abstract

Un synchronisateur MOS comprend deux circuits à verrouillage D en cascade; chacun de ces circuits comprend une porte de passage à n canaux, un circuit tampon CMOS d'inversion à action anticipée et un inverseur à contre-réaction CMOS cadencé. Le synchronisateur possède des dispositifs de largeur augmentée à différents endroits destinés à augmenter le gain de la boucle et la porte de passage comprend plusieurs transistors dont les n+ diffusions sont réunies de manière à minimiser la capacitance au noeud d'entrée du circuit tampon d'inversion à action anticipée.
PCT/EP1992/000643 1992-03-19 1992-03-19 Circuits a verrouillage mos et synchronisateurs incorporant ces circuits Ceased WO1993019528A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/EP1992/000643 WO1993019528A1 (fr) 1992-03-19 1992-03-19 Circuits a verrouillage mos et synchronisateurs incorporant ces circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP1992/000643 WO1993019528A1 (fr) 1992-03-19 1992-03-19 Circuits a verrouillage mos et synchronisateurs incorporant ces circuits

Publications (1)

Publication Number Publication Date
WO1993019528A1 true WO1993019528A1 (fr) 1993-09-30

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2736746A1 (fr) * 1995-07-13 1997-01-17 Sgs Thomson Microelectronics Circuit de memorisation d'etats
US5854565A (en) * 1995-10-06 1998-12-29 Qualcomm Incorporated Low power latch requiring reduced circuit area
WO2000031871A1 (fr) * 1998-11-25 2000-06-02 Nanopower, Inc. Bascules perfectionnees et autres circuits logiques et techniques pour perfectionner les traces de circuits integres

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3428393A1 (de) * 1984-08-01 1986-02-13 Siemens AG, 1000 Berlin und 8000 München Taktgesteuerte kippschaltung
EP0424222A1 (fr) * 1989-10-17 1991-04-24 Thomson Composants Microondes Circuit intégré logique, à temps de basculement réglable

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3428393A1 (de) * 1984-08-01 1986-02-13 Siemens AG, 1000 Berlin und 8000 München Taktgesteuerte kippschaltung
EP0424222A1 (fr) * 1989-10-17 1991-04-24 Thomson Composants Microondes Circuit intégré logique, à temps de basculement réglable

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE 1991, pages 29.4.1 - 29.4.6 GABARA 'Metastability of CMOS Master/Slave Flip-Flops' cited in the application *
IEEE JOURNAL OF SOLID-STATE CIRCUITS. vol. 24, no. 1, February 1989, NEW YORK US pages 146 - 157 HORSTMANN ET AL. 'Metastability Behavior of CMOS ASIC Flip-Flops in Theory and Test' cited in the application *
IEEE JOURNAL OF SOLID-STATE CIRCUITS. vol. 25, no. 4, August 1990, NEW YORK US pages 942 - 951 LEE-SUP ET AL. 'Metastability of CMOS Latch/Flip-Flop' cited in the application *
IEEE JOURNAL OF SOLID-STATE CIRCUITS. vol. 27, no. 1, January 1992, NEW YORK US pages 128 - 130 F.ROSENBERG ET AL. 'Comments on "Metastability of CMOS Latch/Flip-Flop"' cited in the application *
RITTER S.: "STATISCHE CMOS-SCHALTUNGSTECHNIK.", RFE RADIO FERNSEHEN ELEKTRONIK., HUSS MEDIEN GMBH, BERLIN., DE, vol. 38., no. 12., 1 January 1989 (1989-01-01), DE, pages 755 - 757., XP000096635, ISSN: 1436-1574 *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2736746A1 (fr) * 1995-07-13 1997-01-17 Sgs Thomson Microelectronics Circuit de memorisation d'etats
US5854565A (en) * 1995-10-06 1998-12-29 Qualcomm Incorporated Low power latch requiring reduced circuit area
WO2000031871A1 (fr) * 1998-11-25 2000-06-02 Nanopower, Inc. Bascules perfectionnees et autres circuits logiques et techniques pour perfectionner les traces de circuits integres
US6198324B1 (en) 1998-11-25 2001-03-06 Nanopower Technologies, Inc. Flip flops
US6252448B1 (en) 1998-11-25 2001-06-26 Nanopower Technologies, Inc. Coincident complementary clock generator for logic circuits
US6297668B1 (en) 1998-11-25 2001-10-02 Manopower Technologies, Inc. Serial device compaction for improving integrated circuit layouts
US6333656B1 (en) 1998-11-25 2001-12-25 Nanopower Technologies, Inc. Flip-flops

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