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WO1992016995A1 - Convertisseur d'energie commutable a tension nulle - Google Patents

Convertisseur d'energie commutable a tension nulle Download PDF

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Publication number
WO1992016995A1
WO1992016995A1 PCT/GB1992/000450 GB9200450W WO9216995A1 WO 1992016995 A1 WO1992016995 A1 WO 1992016995A1 GB 9200450 W GB9200450 W GB 9200450W WO 9216995 A1 WO9216995 A1 WO 9216995A1
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WO
WIPO (PCT)
Prior art keywords
switch means
primary
voltage
switch
coupled
Prior art date
Application number
PCT/GB1992/000450
Other languages
English (en)
Inventor
David Anthony Smith
Original Assignee
Astec International Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Publication of WO1992016995A1 publication Critical patent/WO1992016995A1/fr

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/22—Conversion of DC power input into DC power output with intermediate conversion into AC
    • H02M3/24—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters
    • H02M3/28—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
    • H02M3/325—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer

Definitions

  • the present invention relates to DC-to-DC switching power converters which transfer power from a source supply at a given voltage potential to a
  • the invention relates to the control of energy in transformers of DC-to-DC forward converters.
  • the forward converter is a common circuit topology used to transform electric energy from a source at a given potential to a destination load at a
  • the forward converter requires fewer components than other converter
  • the standard forward converter comprises a transformer having a primary winding, a secondary winding, and a third winding.
  • the primary winding is coupled to a source of power, usually DC power, via a primary switch and the secondary winding is coupled to a load via two
  • the primary switch generally comprises a semiconductor switching device such as a field-effect transistor (FET) or e bipolar-junction transistor (BJT).
  • FET field-effect transistor
  • BJT bipolar-junction transistor
  • the third winding is coupled to the power source via a rectifying diode and serves to reset the ferromagnetic core of the transformer when the primary switch is opened.
  • the transformer's third winding provides a current path for discharging the transformer's magnetizing current, which is created when the primary winding is energized.
  • the standard forward converter is particularly well suited for low and medium power-conversion
  • the core-reset operation in the forward converter using the third winding is not as efficient as other core-reset operations in other converter
  • the rectifier in series with the third winding causes an amount of power dissipation and, more importantly, the addition of a third winding to the transformer increases the transformer's dimensions and thereby reduces the transformer efficiency by increasing the core losses, the resistance of each winding, and the self inductance of each winding.
  • the forward converter only uses the first quadrant of the transformer's core B-H
  • the power dissipation in the primary switch when it is switched on (a turn-on event) is greater than the power dissipation in comparable
  • the power dissipation in a switch during a switching event depends upon the product of the voltage across the switch and the current through the switch.
  • the voltage difference across the primary switch changes from a value equal to the input voltage of the power source to a value near zero when the switch is closed.
  • the primary current begins immediately since the forward converter provides current to the secondary winding immediately upon energizing the primary winding.
  • auxiliary switch is operated counter to the primary switch, i.e., the auxiliary switch is open when the primary switch is closed and closed when the primary switch is open.
  • the storage capacitor and auxiliary switch operate to capture and store the transformer's magnetizing current, which was built up when the primary winding was energized, and then to return the magnetizing current to the transformer in a manner which resets the
  • present invention provides improvements to the basic forward-converter topology by reducing the power
  • the present invention recognizes that the magnetizing current in the forw a rd converter's
  • transformer is a source of energy that could be used to reduce the voltage across the converter's primary switch to a value near zero volts before the primary switch is closed to energize the primary winding.
  • a reduction of voltage to near zero volts in magnitude (either positive or negative in value) just prior when the primary switch is closed greatly reduces the power dissipation in the primary switch means and is referred to as a zero-voltage-switching condition.
  • the present invention applies to a power converter having a transformer, including a primary winding and a secondary winding, the secondary winding being coupled to an output load, and a primary switch means connected in series between the primary winding and a voltage source.
  • the primary switch means causes energy to be stored in the
  • the present invention encompasses circuitry for isolating the loading effects of the secondary winding from the converter's transformer in a time interval preceding the closing of the primary switch means and for utilizing the magnetizing energy stored in the transformer to reduce the voltage across the primary switch to a value near zero before the primary switch means is closed.
  • circuitry comprises a storage capacitor and a first switch means coupled in series with the storage
  • the series combination of the storage capacitor and the first switch means is coupled in parallel with a selected one of the transformer
  • the isolation and utilization circuitry further comprises a second switch means connected in series with the secondary winding of the transformer and a switch control means for operating the first and second switch means in relation to the ON-period and OFF-periods of the primary switch means.
  • the switch control means closes the first switch substantially when the primary switch means opens and opens the first switch means prior to when the primary switch means closes to create a zero-voxwage switching condition across the primary switch means when the primary switch means is next closed.
  • the switch control means opens the second switch means
  • the second switch means remains open in the portion of the converter's switching cycle prior to the closing of the primary switch means such that the loading effects from the secondary winding are isolated from the converter's transformer.
  • the isolation of the loading effects from the secondary winding create a zero-voltage-switching across the primary switch means which the primary switch means is next closed.
  • the switch control means further comprises means for closing the first switch means after the primary switch means is opened so as to create a zero-voltage-switching condition across the first switch means.
  • switch control means further comprises means for operating the second switch means in response to the voltage detected across the secondary winding, thus making the switch control circuitry for the second switch means autonomous from the switch control
  • FIGURE 1 is a circuit diagram of the standard forward converter according to the prior art.
  • FIGURE 2 is a timing diagram of key voltages and currents of the standard forward converter shown in FIGURE 1.
  • FIGURE 3 is a circuit diagram of a modified forward converter having a series combination of a storage capacitor and auxiliary switch coupled in parallel with the primary transformer winding according to the prior art.
  • FIGURE 4 is a first timing diagram of key voltages and currents of the modified forward converter shown in FIGURE 3 under light loading conditions.
  • FIGURE 5 is a second timing diagram of key voltages and currents of the modified forward converter shown in FIGURE 3 under heavy loading conditions.
  • FIGURE 6 is a circuit diagram of an exemplary embodiment of the forward converter according to the present invention.
  • FIGURE 7 is a timing-requirement diagram showing the operation of the first and second switch means of the exemplary embodiment of the forward converter shown in FIGURE 6.
  • FIGURE 8 is a first timing diagram of key voltages and currents of the exemplary embodiment of the forward converter shown in FIGURE 6 under a first switching-event sequence.
  • FIGURE 9 is a second timing diagram of key voltages and currents of the exemplary embodiment of the forward converter shown in FIGURE 6 under a second switching-event sequence.
  • FIGURE 10 is a partial block diagram of the forward converter shown in FIGURE 6 showing exemplary embodiments of the primary switch means and the first switch means according to the present invention.
  • FIGURE 11 is circuit diagram of an exemplary embodiment of the switch control means according to the present invention.
  • FIGURE 12 is a partial block diagram of the forward converter shown in FIGURE 6 showing exemplary embodiments of the second switch means according to the present invention and of an autonomous switch control means for the second switch means according to the present invention.
  • the basic topology of the forward converter is shown at 1000 in FIGURE 1 and comprises a transformer 1020 having a primary winding 1022 and secondary winding 1024, a primary switch means 1040 (S PR ) connected in series with primary winding 1022, and rectifiers 1050 (CR1) and 1060 (CR2) which direct power from secondary winding 1024 to a load 1074.
  • Transformer 1020 further comprises a third winding 1026, which provides a means for resetting the core of transformer 1020, as discussed below in greater detail.
  • a voltage source 1010 having a value of V 0 supplies forward converter 1000 with power and a choke inductor 1070 (L OUT ) and a load capacitor 1072 (C OUT ) are used to filter the power delivered to load 1074. Additionally, converter 1000 comprises a capacitor 1032 (C S ) for representing the stray
  • transformer 1020 (parasitic) capacitance associated with primary winding 1022 and switch means 1040.
  • an imaginary inductor is used to model the effects of the magnetizing energy of transformer 1020.
  • the modeling inductor is indicated in phantom as inductor 1023 in FIGURE 1 and is coupled in parallel with primary winding 1022.
  • the magnetizing effects of transformer 1020 can be readily analyzed in the form of a
  • inductor 1023 is not a real component of converter 1000 but rather an imaginary modeling component which aids in explaining the
  • the voltage across primary winding 1022 is designated as V P
  • the voltage across secondary winding 1024 is designated at V S
  • the voltage across the third winding 1026 is designated as V T .
  • Each of these winding voltages is referenced such that the positive terminal coincide3 with the magnetic reference dot shown in FIGURE 1.
  • node voltages of significance there are two node voltages of significance.
  • V 1 the voltage at this node with respect to ground
  • node V 1 the voltage at this node with respect to ground
  • node V 2 the voltage at this node with respect to ground
  • node V 2 the voltage at this node with respect to ground
  • the current flowing into third winding 1026 at the positive terminal is designated as I T
  • the current flowing into primary winding 1022 at the positive terminal is designated as I T
  • I 1 the current flowing into inductor 1023 from voltage source 1010 is designated as I M
  • I P the total primary current flowing into both inductor 1023 and winding 1022 from voltage source 1010
  • I CS The current flowing into Capacitor 1032 (C S ) from node V 2 is designated as I CS .
  • Rectifiers 1050 (CR1) and 1060 (CR2) have the current reference
  • I CR1 and I CR2 respectively, where the current references flow into the anode terminals of each rectifier.
  • the current flowing through choke inductor 1070 (L OUT ) is designated by the current reference designation I LOUT , where the current reference flows toward load 1074.
  • the current flowing through load 1074 is designated by the current reference designation
  • I LOAD I LOAD , where the current reference flows from choke inductor 1070 to ground.
  • primary winding 1022 and secondary winding 1024 are taken to have the same number of turns.
  • the dot notations for windings 1022 and 1024 indicate their polarities.
  • an imaginary inductor 1023 (L M ) is indicated, in phantom, in the circuit diagram for transformer 1020 to model the effects of the magnetizing flux and
  • magnetizing current of transformer 1020 As well known in the transformer art, a current must be provided to one of windings of a real transformer to provide the magnetomotive force required to overcome the magnetic reluctance of the transformer's core. This current is known as the magnetizing current and is generally provided to the primary winding of the transformer.
  • magnetizing current can be electrically modeled by a phantom inductor coupled in parallel with the primary winding of an ideal transformer, as shown by inductor 1023. This is because the magnetizing current is proportional to the time integral of the voltage
  • the inductance value L M of the phantom modeling inductor 1023 is set to a value representative of the core reluctance of transformer 1020, as well known in the transformer art.
  • the magnetizing current is a parasitic effect and does not exist in an ideal transformer. As such, the magnetizing current component in the primary winding circuit is not transformed into current in the secondary winding.
  • the current flowing in secondary winding 1024 is related to the current flowing into primary winding 1022 and is not related to the current flowing in inductor 1023.
  • primary winding 1022, secondary winding 1024, and third winding 1026 function as an ideal transformer while inductor 1023 functions to account for the magnetizing current in transformer 1020.
  • the above mentioned current I P represents the current flowing into the primary winding of a real transformer
  • the above mentioned current I M represents the component of primary current I P needed to overcome the reluctance of the real transformer
  • the above mentioned current I 1 represents the component of primary current I P which is actually transformed over to the secondary winding of the real transformer.
  • inductor 1023 can be coupled in parallel with secondary winding 1024 rather than with primary winding 1022 to represent the magnetizing current.
  • the magnetizing current causes energy to be stored in the transformer's core when the transformer's primary winding is energized by the closing of primary switch means 1040. This energy is stored in the form of magnetic flux in the core and is referred to as the magnetizing flux.
  • the magnetizing flux must be
  • the flux energy is discharged by discharging the magnetizing current through one of the transformer's windings.
  • the discharging process is formally known as resetting the core.
  • third winding 1026 of transformer 1020 is coupled in series with a rectifier 1030 and the series combination is coupled across voltage source 1010.
  • Rectifier 1030 is oriented to direct the flow of current into the positive terminal of voltage source 1010 and the reference dot of third winding 1026 is opposite to that of primary winding 1022.
  • current is conducted in third winding 1026 towards voltage source 1010 when the voltage V T across third winding 1026 is less than or equal to -V 0 .
  • third winding 1026 is taken to have the same number of turns as primary winding 1022.
  • magnetizing current through third winding 1023 is detailed below in the discussion of the operation of forward converter 1000.
  • the operation of the forward converter 1000 is governed by primary switch means 1040 which causes converter 1000 to enter an ON-period when it is closed and to enter an OFF-period when it is open.
  • primary switch means 1040 When primary switch means 1040 is closed, magnetizing current and magnetic energy build up in inductor 1023 of
  • transformer 1020 due to the voltage applied across inductor 1023 by voltage source 1010.
  • the magnetizing current in magnetizing inductor 1023 increases at a constant rate with respect to time (i.e., the waveform of the magnetizing current has a positive linear slope).
  • the voltage across primary winding 1022 is also applied to secondary winding 1024 by transformer action and a current in secondary winding 1024 is induced to flow through rectifier 1050 towards load 1074.
  • a current equal in magnitude to the current in secondary winding 1024 is generated in primary winding 1022 by transformer action.
  • Current flow through third winding 1026 is blocked by rectifier 1030 due to the orientation of rectifier 1030 and the polarity of third winding 1026.
  • the magnetizing current in inductor 1023 continues to flow into capacitor C S until the voltage V 1 equals 2V 0 , at which point the voltage across third winding 1026 is equal to -V 0 and a current begins to flow in third winding 1026 via rectifier 1030.
  • the winding voltages V P , V S and V T of transformer 1020 are clamped to a value of V 0 , thus preventing any further charging of capacitor C S .
  • the waveform of the magnetizing current has a negative, linear slope and the waveform of the current in
  • secondary winding 1024 is constant at zero amperes. The magnetizing current decreases until the magnetic energy built up in transformer 1020 during the ON-period is completely transferred to voltage source 1010 or until primary switch means 1040 is closed again.
  • the duty-cycle is adjusted to meet the power requirements of the load, with a higher duty-cycle providing more power to the load.
  • the duration of one ON-period and the subsequent OFF-period is often referred to as the switching cycle.
  • the OFF- period is often referred to as the "fly-back" phase due to the abrupt reversals in the voltages and changes of the currents of the transformer windings. It is also referred to as the "reset” phase since the magnetic energy and flux in the transformer core
  • the voltage that develops across primary switch means 1040 during the OFF-period is greater than the value provided by voltage source 1010 and is referred to as the "reset" voltage.
  • the output voltage V OUT is equal to the input voltage V 0 times the duty cycle, as expressed in the form of a fraction (i.e., divided by 100%). This is because the output voltage V OUT adjusts to a voltage level such that the time-integrated voltage applied across choke inductor 1070 during each switching cycle is equal to zero, under steady state conditions.
  • T ON the voltage applied to choke inductor 1070 is (V 1 -V OUT ) volts.
  • T OFF the voltage applied to choke inductor 1070 is (-VOUT) volts. Setting the time- integrated voltage to zero (i.e., T ON (V 0 -V OUT ) 0
  • each winding of transformer 1020 has the same number of turns and has no parasitic resistance and transformer 1020 is operated in the linear regime of its B-H characteristic.
  • each rectifier has a nominal voltage drop for forward conducting current, near zero current conduction for reverse applied voltage and has a nominal amount of reverse- recovery current.
  • the output voltage across load 1074 is taken to be constant at a value of one third the input voltage (V 0 /3).
  • load 1074 is taken to be resistive in nature without loss of generality.
  • FIGURE 2 The operation of primary switch means 1040 is shown in graph 2001 in FIGURE 2.
  • Graph 2001 is in a form of a time line which indicates the ON-periods where primary switch means 1040 (S pR ) is closed and the OFF-periods where primary switch means 1040 is open.
  • the winding voltages V P , V S and V T and the voltage V 1 are shown in graph 2002 in FIGURE 2.
  • the total primary current I P and the current I CS into capacitor C S are shown in graph 2003
  • the magnetizing current I M in inductor 1023 and the current I 1 in primary winding 1022 are shown in graph 2004, and the current I T in third winding 1026 is shown in graph 2005 in FIGURE 2.
  • the output voltage V OUT at load 1074 and the voltage V 2 are shown in graph 2006
  • the currents I CR1 and I CR2 in rectifiers 1050 (CR1) and 1060 (CR2) are shown in graph 2007, and the current I LOUT in choke inductor 1070 and the current I LOAD in load 1074 are shown in graph 2008 in FIGURE 2.
  • the rectifier current I CR1 supports the inductor current I LOUT during the ON-periods and that the rectifier current I CR2 supports the inductor current I LOUT during the OFF-periods.
  • the voltage across all three windings is set by voltage source 1010 at a value of V 0 , with the voltage V 1 across primary switch means 1040 at near zero volts, as shown in graph 2002.
  • the application of V 0 across the secondary winding causes rectifier 1050 (CR1) to fully support the current in choke inductor 1070.
  • the rectifier current I CR1 is
  • the magnetizing current I M increases at a constant rate determined by the voltage applied across inductor 1023 and the magnetizing inductance of inductor 1023, as also shown in graph 2004.
  • the total primary current I P is equal to the sum of I 1 and I M and is shown in graph 2003.
  • capacitor 1032 C S
  • V 1 The charging current into capacitor C S is shown as I CS in graph 2003.
  • V 0 the current in the primary and secondary windings ceases, as described above, and rectifier 1060 (CR2) supports the current I LOUT of choke inductor 1070.
  • V 1 reaches 2V o and the transformer winding voltages V P , V S , and V T reach -V 0
  • the magnetizing current I M reverses polarity and flows into primary winding 1022 (I 1 ), where it is transformed over to third winding 1026 (I T ) and discharged back into voltage source 1010.
  • This process is shown in graphs 2004 and 2005 and occurs during the first part of the OFF-period.
  • the time required to discharge the magnetizing current is roughly equal to the duration of the ON-period because the voltage applied to inductor 1023 during the first part of the OFF-period is equal in magnitude, but opposite in sign, to the voltage applied to inductor 1023 during the ON-period.
  • the winding voltages V P , V S , and V T return to zero volts and the voltage V 1 return to a value of V 0 .
  • the currents in the primary circuit and secondary winding 1024 cease while the current in rectifier 1060 continues to support the current I LOUT.
  • the second part of the OFF-period may be characterized as dead-time since transformer 1020 is neither providing power to the secondary circuit nor having its core reset. The dead time allows converter 1000 to increase the duty cycle, i.e., increase the duration of the ON-period while decreasing the OFF-period, toward 50% in order to provide more power to load 1074, if needed.
  • transformer 1020 which is usually constructed with a core of soft
  • the core Due to physical properties of the ferromagnetic material, the core can only support a maximum amount of magnetic flux density, B. Since the magnetic flux ⁇ is proportional to the magnetic flux density B by the number of turns and the cross-sectional area of the winding, the core can only support a maximum amount of magnetic flux and, hence, magnetizing current. This amount is referred to as the saturation flux value. Beyond the saturation flux value, the transformer ceases to operate.
  • the saturation of magnetic flux limits the amount of power that converter 1000 may provide to load 1074 during each ON-period.
  • the number of turns in each winding can be increased or the cross-sectional area can be increased. Either of these increases, however, increases the parasitic resistances of the windings and thereby decreases the efficiency of converter 1000.
  • converter 1000 only uses the first quadrant of the transformer's B-H curve and, hence, only uses one half of the transformer's flux range. If both the first and third quadrant of the transformer's B-H curve are used instead of only the first quadrant, the transformer of a forward converter can be re-designed to reduce the winding resistances and thereby increasing the
  • Primary switch means 1040 generally comprises a semiconductor device such as a field-effect transistor (FET) or a bipolar-junction transistor (BJT).
  • FET field-effect transistor
  • BJT bipolar-junction transistor
  • the present invention addresses this power conversion loss by providing means for driving the voltage across the primary switch means to near zero volts before the primary switch means is closed.
  • the condition whereby the voltage across the primary switch means is driven to zero volts before the primary switch is closed is herein referred to as a zero-voltage-switching condition.
  • the power dissipation during this transition is much less than the dissipation in the transition from the OFF-period to the ON-period, typically between one and two orders of magnitude less. The difference is
  • transistor device either FET or BJT, and an explanation of the difference is not necessary in order to
  • forward converter 1000 Another operational aspect of forward converter 1000 relates to the voltaga stress on primary switch means 1040 during the OFF-period.
  • the voltage across primary winding 1022 reverses and adds with voltage source 1010 to produce a voltage stress on primary switch means 1040 approximately equal twice the input voltage V 0 .
  • This voltage stress affects the reliability of forward converter 1000 directly and the conversion efficiency indirectly.
  • the indirect effect on efficiency is explained below as follows. Due to the material properties of semiconductor devices, FET and BJT devices can only withstand a predetermined maximum voltage, known as a breakdown voltage, across their conduction terminals before the devices are destroyed.
  • Vinciarelli does not, however, address the direct power dissipation losses in the primary switch means during transitions between the ON and OFF-periods. Such direct power dissipation losses become more significant as the switching frequency increases since the duration of each switching event comprises a larger fraction of each switching cycle duration as the switching frequency increases. As the present invention builds on the teachings of prior art active clamp circuits, an exemplary such circuit is discussed in greater detail below with reference to FIGURES 3 through 5.
  • Such a modified forward converter is shown at 3000 in FIGURE 3 and is disclosed in an article by B. Carsten, entitled “High Power SMPS Require Intrinsic Reliability," PCI Proceedings, March 1982, pp. 456-471 as well as in U.S. Patent No. 4,441,146 issued to
  • the topology of forward converter 3000 is similar to the topology of forward converter 1000 with the exception that third winding 1026 and rectifier 1030 of converter 1000 are replaced by a series combination of a storage capacitor 3034 and an auxiliary switch means 3030. The latter two components are used to control the reset of the transformer core during the OFF-period, as explained below. With the exception of storage capacitor 3034 and auxiliary switch means 3030, each element of converter 3000 is the same as a
  • the number designation for each element of converter 3000 is set to be equal to the number designation of the corresponding element in converter 1000 plus a value of two-thousand.
  • an imaginary inductor is used to model the effects of the magnetizing energy of transformer 3020.
  • the modeling inductor is indicated in phantom as inductor 3023 in FIGURE 3 and is coupled in parallel with primary winding 3022.
  • the magnetizing effects of transformer 3020 can be readily analyzed in the form of a magnetizing current.
  • Storage capacitor 3034 and auxiliary switch means 3030 are coupled in series to one another. One terminal of the series combination is coupled to the switched terminal of primary winding 3022 (at node V 1 ) and the other end is coupled to a constant voltage reference, which is the positive terminal of voltage source 3010 in this case.
  • Storage capacitor 3034 and auxiliary switch means 3030 comprise means, for
  • auxiliary switch means 3030 comprise means for causing converter 3000 to use the third quadrant of transformer 3020's B-H characteristic. These means are explained below in greater detail.
  • I P , I CS , I CR1 , I CR2 , I LOUT , and I LOAD shown in FIGURE 3 have the same designations and references as the
  • forward converter 3000 As with forward converter 1000, the operation of forward converter 3000 is governed by primary switch means 3040, which causes converter 3000 to enter an ON- period when switch means 3040 is closed and to enter an OFF-period when switch means 3040 is open.
  • Auxiliary switch means 3030 operates counter to primary switch means 3040 by opening when primary switch means 3040 closes and by closing when primary switch means 3040 opens. The operation of converter 3000 is explained in greater detail below with the assumption that the voltage at the positive terminal of capacitor 3034 with respect to ground is greater than V 0 , which is the voltage value of voltage source 3010.
  • auxiliary switch means 3030 is open, a voltage of V 0 appears across secondary winding 3024 causing a secondary current to flow through rectifier 3050 and a corresponding current to flow in primary winding 3022 due to transformer action.
  • a magnetizing current builds up in inductor 3023 at a constant rate due to the application of a constant voltage of V 0 across inductor 3023 by voltage source 3010.
  • the capacitance of storage capacitor 3034 is taken to be large enough so that the voltage across storage capacitor 3034 does not substantially change during the OFF-period. Since a constant negative voltage is being applied to inductor 3023 during the OFF-period, the magnetizing current I M decreases at a constant rate, thereby acting to reset the transformer core. If the OFF-period is sufficiently long, the decrease in I M continues to the point where current I M reverses direction and flows out of storage capacitor 3034 and into voltage source 3010.
  • the time-integrated voltage across inductor 3023, and hence across each winding of transformer 3020, should be zero for each switching cycle, otherwise the magnetic flux in the core of transformer 3020 will saturate within a finite number of switching cycles.
  • the voltage V C across capacitor 3034 is at a value which sets the time-integrated voltage across inductor 3023 to zero during each switching cycle. This value is referred to as the required value for V C which prevents core saturation and may be determined as follows.
  • T ON a voltage of +V 0 is applied to inductor 3023 by voltage source 3010.
  • the voltage applied to inductor 3023 is the negative of the voltage across storage capacitor 3034: -V C .
  • the time-integrated voltage during each switching cycle is determined as:
  • Time Integrated Voltage T ON ⁇ V 0 - T OFF ⁇ V C (1) Setting the time integrated voltage to zero and solving for the required value of V C , which sets the time- integrated voltage to zero, results in:
  • V CSS represents the required value of V C for preventing core saturation during steady state operations and the symbol DC represents the given duty cycle.
  • the waveform for the magnetizing current I M must be centered around a value of zero amperes in order to prevent a net charge accumulation or depletion on storage capacitor 3034 during the OFF-period. Otherwise, the voltage V C would shift away from the required V CSS value.
  • the voltage V C departs from the value V CSS in order to shift the I M waveform so that it is centered around zero amperes.
  • the I M waveform is initially shifted upwards and centered around a positive current value, the shifted waveform will cause a net charge to flow into storage capacitor C C , thereby raising the voltage V C .
  • the higher V C voltage causes the magnetizing current to decrease at a faster rate during the OFF-period, thereby shifting the I M waveform down to center the I M waveform around zero amperes within a finite number of switching cycles.
  • the shifted waveform will cause a net charge to flow out of storage capacitor C C , thereby lowering the voltage V C .
  • the lower V C voltage causes the
  • V CSS voltage value for storage capacitor 3034 is reached by the transient charging or discharging of storage capacitor 3034. If the voltage across storage capacitor 3034 is less than V CSS , It takes a longer time duration to reverse the current-flow
  • the waveform for the magnetizing current is not centered around a value of zero amperes.
  • inductor 3023 serves to reset the magnetic flux in the transformer's core at a point inside the third quadrant of the transformer's B-H characteristic.
  • transformer 3020 increases the utilization of the transformer's core and, hence, the structure of transformer 3020 may be re designed to decrease the dissipation losses in
  • each winding of transformer 3020 has the same number of turns and has no parasitic resistance and transformer 3020 is operated in the linear regime of its B-H characteristic.
  • each rectifier has a nominal voltage drop for forward conducting current, near zero current conduction for reverse applied voltage and has a nominal amount of reverse-recovery current.
  • the output voltage across load 3074 is taken to be constant at a value of V 0 /3.
  • load 3074 is taken to be resistive in nature without loss of generality.
  • Graph 4001 is in the form of a time line which indicates the ON-periods where primary switch means 3040 (S PR ) is closed and the OFF-periods where primary switch means 3040 is open.
  • Graph 4009 is also in the form of a time line and indicates when auxiliary switch means 3030 (S A ) is closed and when auxiliary switch means 3030 is open.
  • the winding voltages V P and V S and the voltage V 1 are shown in graph 4002 in FIGURE 4.
  • the total primary current I P and the current I CS into capacitor C S are shown in graph 4003
  • the magnetizing current I M in inductor 3023 and the current I 1 in primary winding 3022 are shown in graph 4004
  • the current I CC flowing into storage capacitor 3034 is shown in graph 4005 in FIGURE 4.
  • the output voltage V OUT at load 3074 and the voltage V 2 are shown in graph 4006, the currents I CR1 and I CR2 in rectifiers 3050 (CR1) and 3060 (CR2) are shown in graph 4007, and the current I LOUT in choke inductor 3070 and the current I LOAD in load 3074 are shown in graph 4008 in FIGURE 4.
  • the rectifier current I CR1 supports the inductor current I LOUT during the ON-periods and that the rectifier current I CR2 supports the inductor current I LOUT during the OFF-periods.
  • the voltage across primary winding 3022 and secondary winding 3024 is set by voltage source 3010 at a value of V 0 with the voltage V 1 across primary switch means 3040 at. near zero volts, as shown in graph 4002.
  • the application of V 0 across the secondary winding causes rectifier 3050 (CRl) to fully support the current in choke inductor 3070.
  • the transformer action of transformer 3020 Via the transformer action of transformer 3020, the
  • rectifier current I CR1 is replicated in the current I 1 of primary winding 3022, as shown in graph 4004. Also during the ON-period, the magnetizing current I M
  • inductance of inductor 3023 as also shown in graph 4004.
  • the magnetizing current during steady-state conditions is centered around a value of zero amperes, as shown in graph 4004.
  • the total primary current I P is equal to the sum of I 1 and I M and is shown in graph 4003.
  • auxiliary switch means 3030 is open and, as such, and the current I CC into capacitor 3034 is zero, as shown in graph 4005.
  • auxiliary switch means 3030 begins to close. During this switching transition, the magnetizing current in inductor 3023 initially flows into capacitor 3032 (C S ) and raises the voltage V 1 towards the voltage on capacitor 3034. Once auxiliary switch means 3030 closes, the magnetizing current in inductor 3023 flows into storage capacitor 3034. As mentioned above, the capacitance value of storage capacitance 3034 is
  • the rate of decrease in I M is equal in magnitude to half of the rate of increase in I M during the ON-period since the magnitude of applied voltage across inductor 3023 during the OFF-period is half the magnitude during the ON-period.
  • I M reverses sign and flows out of storage capacitor 3023.
  • the waveform of I M during the OFF-period is reflected in the waveforms for the total primary current I P , as shown in graph 4003, and for the storage capacitor current I CC , as shown in graph 4005.
  • Forward converter 3000 has two main advantages as compared with forward converter 1000 shown in FIGURE 1. First, the waveform of magnetizing current I M is centered around zero amperes, indicating that the third quadrant of the transformer core's B-H characteristic is being utilized. This provides a larger range of
  • transformer 3020 can be optimized to lower the winding resistances and reduce power dissipation, as discussed above. Secondly, the voltage stress applied to the primary switch means 3040 during the OFF-period is reduced compared to that across primary switch means 1040 since the voltage applied to primary switch means
  • the voltage V 1 can be reduced to zero volts in this manner before primary switch means 3040 is closed, thereby significantly reducing the power
  • the present invention identifies the causes which prevent zero voltage switching and provides means for overcoming these causes.
  • a short delay period, or time duration, is introduced between the end of the OFF-period and the beginning of the ON-period where both primary switch means 3040 a,nd auxiliary switcn means 3030 remain open.
  • This time period is shown at 4020 in FIGURE 4 and. is referred to as delay period 4020 for the purposes of this discussion.
  • the magnetizing current I P through inductor 3023 is negative at the beginning of delay period 4020. Since both switch means 3040 and 3030 are open, no definite voltage is applied across inductor 3023 and primary winding 3022. Under this condition, the magnetizing current I M begins to flow through stray capacitor 3032, thereby reducing tne voltage V 1 from 3V 0 /2 towards zero volts.
  • the magnetizing current continues to reduce the voltage V 1 until the voltage V 1 reaches a value of V 0 .
  • the voltages V P across primary winding 3022 and V S across secondary winding 3024 become positive and the secondary circuit begins conducting current through rectifier 3050 (I CR1 ).
  • a current (I 1 ) flows in primary winding 3022 which is equal in magnitude to the current flowing in secondary winding 3024. This current flow in primary winding 3022 diverts some or all of the magnetizing current away from stray capacitor 3032. If the
  • magnetizing current is equal to the magnetizing current less the current flowing in choke inductor 3070.
  • the voltage V 1 cannot be reduced to zero volts due to the loading effects on secondary winding 3024. In some cases, the reduction of voltage V 1 ends at a positive voltage.
  • the current through choke inductor 3070 is greater than the magnetizing current I M during the beginning of delay period 4020 and oftentimes throughout delay period 4020. In this case, the
  • magnetizing current decreases voltage V 1 only to a value of V 0 volts, at which point all of the magnetizing current I M is diverted into secondary winding 3024, via primary winding 3022, and the voltage V 1 is clamped at a value of V 0 .
  • the remainder of the current flow in choke inductor 3070 is provided by rectifier 3060, which clamps voltage V 2 near zero volts.
  • timing diagram 5000 in FIGURE 5 shows conditions where the current through choke inductor 3070 is greater than the magnetizing current during the delay period.
  • Timing diagram 5000 comprises graphs 5001 through 5009 and a delay period 5020.
  • Graphs 5001 through 5009 display the same information as graphs 4001 through 4009, respectively, as shown in FIGURE 4.
  • magnetizing current shown in graph 5004 is diverted in primary winding 3022, as shown by I 1 in graph 5004, which sets the current in secondary winding 3024 equal to the magnetizing current, as shown by I CR1 in graph 5007.
  • the voltage V 1 is thereby clamped at a value of V 0 volts and a zero-voltage-switching condition cannot be achieved.
  • the above described mechanism which diverts magnetizing current into secondary winding 3024 and resulting voltage clamping of the transformer windings during the delay period have thus far not been discussed nor addressed in the prior art.
  • the present invention has recognized this diversion mechanism and clamping effect as a major hindrance to achieving a zero-voltage- switching condition for primary switch means 3040 in forward converter 3000 under all loading conditions. As discussed below, the present invention seeks to
  • the forward converter according to the present invention is shown at 100 in FIGURE 6. Forward
  • converter 100 comprises a voltage source 110 (V 0 ) for providing electrical energy, a transformer 120 (T1) having a primary winding 122 and secondary winding 124, and a primary switch means 140 (S PR ) coupled in series with primary winding 122 and voltage source 110 for selectively coupling energy from voltage source 110 to transformer 120.
  • Forward converter 100 furthermore
  • converter 100 includes a capacitor 132 (C S ) coupled between the switched terminal of primary winding 122 and ground for representing the combined stray (parasitic) capacitances of primary winding 122, primary switch means 140, and first switch means 130.
  • each of primary winding 122, primary swirch means 140, and first switch means 130 may include a parasitic capacitance, resulting from the non-ideal elements used in implementing each of these components.
  • the parasitic capacitance of each of these components may, for example, be represented by a parasitic
  • each parasitic capacitor being coupled between its respective component terminal and ground.
  • capacitor 132 further comprises a fixed-value capacitor in addition to the parasitic capacitances so as to provide a more predictable capacitance value for capacitor 132, thereby increasing the manufacturing consistency of converter 100.
  • an imaginary inductor is used to model the effects of the magnetizing energy of transformer 120.
  • the modeling inductor is indicated in phantom as inductor 123 in FIGURE 6 and is coupled in parallel with primary winding 122.
  • the magnetizing effects of transformer 120 can be readily analyzed in the form of a magnetizing current.
  • the use of modeling inductor 123 in this manner is well known to the transformer art and not a real component of converter 100, but rather an imaginary modeling component which aids in explaining the characteristic behavior of the magnetizing energy in real transformer 120.
  • forward converter 100 For directing and controlling the flow of power from transformer 120 to an output load 174, forward converter 100 further comprises a second switch means coupled in series with said secondary winding for controlling the flow of current to load 174, and a rectifier 160 (CR2) coupled in parallel with the series combination of second switch means 150 and secondary winding 124.
  • Converter 100 further includes a choke inductor 170 (L OUT ) coupled between second switch means 150 and load 174, and a load capacitor 172 (C OUT ) coupled in parallel with load 174.
  • the current through load 174 is represented by the symbol I LOAD and, for the purposes of discussion and without loss of generality, is taken to be constant. Choke inductor 170 (L OUT ) and load capacitor 172 (C OUT ) provide means for filtering the power delivered to load 174.
  • Forward converter 100 further comprises a switch control means 180 for generating signals to control the operation of primary switch means 140, first switch means 130, and second switch means 150.
  • Switch control means 180 comprises a port 181 coupled to primary switch means 140, a port 182 coupled to first switch means 130, and a port 183 coupled to second switch means 150.
  • Port 181 transmits a signal which controls the operation of primary switch means 140
  • port 182 transmits a signal which controls the operation of first switch 130
  • port 183 transmits a signal which controls the operation of first switch 150.
  • the voltage across primary winding 122 is designated as V P
  • the voltage across secondary winding 124 is designated at V S .
  • Each of these winding voltages is referenced such that the positive terminal coincides with the magnetic reference dot shown in FIGURE 6.
  • the voltage at this node with respect to the negative terminal of voltage source 110 is designated as V 1 and the node itself is referred to as node V 1 .
  • the voltage at this node with respect to the negative terminal of secondary winding 124 is designated as V 2 and the node itself is referred to as node V 2 .
  • the following currents in converter 100 are significant.
  • the current flowing into primary winding 122 at the positive terminal is designated as I 1
  • the current flowing into inductor 123 from voltage source 110 is designated as I M
  • the total primary current flowing into both inductor 123 and winding 122 from voltage source 110 is designated as I P .
  • the current flowing into stray capacitor 132 (C S ) from node V 1 is designated as I CS and the current flowing into storage capacitor 134 (C C ) from node V 1 is designated as I CC .
  • the current flowing into second switch means 150 from secondary winding 124 is designated as I S2 and the current flowing out of the cathode terminal of rectifier 160 is designated as I CR2 .
  • the current flowing through choke inductor 170 (L OUT ) is designated by the current reference designation I LOUT , where the current reference flows toward load 174.
  • the current flowing through load 174 is designated by the current reference designation I LOAD , where the current reference flows from choke inductor 170 to ground.
  • primary winding 122 and secondary winding 124 are taken to have the same number of turns.
  • the dot notations for windings 122 and 124 indicate their polarities.
  • An inductor 123 (L M ) is included, in phantom, in the circuit diagram for transformer 120 to model the effects of the magnetizing flux and
  • magnetizing current of transformer 120 As mentioned above, a magnetizing current must be provided to one of windings of a real transformer to provide the magnetomotive force required to overcome the magnetic reluctance of the transformer's core. For a real transformer, the magnetizing current can be
  • the above mentioned current I M represents the component of primary current I P needed to overcome the. magnetic reluctance of the real
  • forward converter 100 is governed by primary switch means 140, which causes converter 100 to enter an ON-period when switch means 140 is closed and to enter an OFF-period when switch means 140 is open.
  • First switch means 130 operates substantially counter to primary switch means 140 by closing substantially when primary switch means 140 opens to start an OFF-period and by opening prior to when primary switch means 140 closes to start an ON-period.
  • Second switch means 150 operates substantially synchronously with primary switch means 140 by closing substantially when primary switch means 140 closes and Ly opening substantially when primary switch means 140 opens.
  • V 0 is the voltage value of voltage source 110.
  • first switch means 130 and second switch means 150 are discussed in greater detail with reference to a timing diagram shown at 200 in
  • FIGURE 7 which shows the timing requirements for the operations of first and second switch means 130,150 with respect primary switch means 140.
  • a single switching cycle having an ON-period followed by an OFF-period is shown in graph 201.
  • the opening and closing operations of primary switch means 140, which define the ON- and OFF-periods, is shown in graph 205 in FIGURE 7.
  • the high sections of graph 205 indicate the time durations where primary switch means 140 is closed and the low sections indicate the time durations where primary switch means 140 is open.
  • the operation and timing requirements for first switch means 130 is shown in graph 210 and the operation and timing requirements for second switch means 150 is shown in graph 220 in FIGURE 7.
  • Timing window 212 Shown in graph 210 is a timing window 212 in which switch control means 180 closes first switch means 130.
  • Timing window 212 is illustrated using a series of parallel skew lines (/).
  • timing window 212 is of a predetermined length and immediately follows the end of the ON-period. Timing window 212 does not preferably intersect with the ON-period. This is because, as discussed in greater detail below, the delay in closing first switch means 130 with respect to the opening of primary switch means 140 may be used to create a zero-voltage-switching condition for first switch means 130.
  • a predetermined time delay 214 in which first switch means 130 is opened before primary switch means 140 is closed.
  • the time delay in closing first switch means 130 with respect to the opening of primary switch means 140 in timing window 212 may be used to provide a zero-voltage-switching condition for first switch means 130 and the time delay 214 between the opening of first switch means 130 and the closing of primary switch means 140 provides a zero-voltage-switching condition for primary switch means 140.
  • second switch means 150 is open during time delay 214 and, thereby, prevents the loading on secondary winding 124 from diverting the magnetizing current away from stray capacitor 132.
  • timing window 222 Shown in graph 220 is a timing window 222 in which switch control means 130 closes second switch means 150.
  • timing window 222 is of a predetermined length and immediately follows the end of the OFF-period. Timing window 222 preferably does not intersect with the OFF-period. This is because, as discussed in greater detail below, the delay in closing second switch means 150 with respect to the closing of primary switch means 140 may be used to allow primary switch means 140 to reach a full conduction state before primary switch means 140 has to conduct the reflected secondary
  • timing window 224 in which switch control means 180 opens second switch means 150.
  • timing window 222 is of a predetermined length which starts during the ON-period and ends before the closing of first switch means 130 in timing window 212.
  • second switch means 150 is opened synchronously with the opening of primary switch means 140.
  • the opening of second switch means 150 after the opening of primary switch means 140 may be used to direct the current in secondary winding 124, as reflected in primary winding 122, into stray capacitor 132 before first switch means 130 is closed. This reduces the amount of magnetizing current required to charge
  • second switch means 150 may be opened before the opening of primary switch means 140, as shown at the dotted line 226 in graph 220.
  • This opening may be used to reduce the current in secondary winding 124 and the corresponding reflected current in primary winding 122 before primary switch means 140 is opened.
  • only the magnetizing current component remains in primary winding 122 when primary switch means 140 is opened, thereby reducing the power dissipation and current stresses on primary switch means 140.
  • the reduction of such stresses is important during high-load (i.e., high duty-cycle) conditions.
  • the opening of second switch means 150 in timing window 224 may be varied to minimize the power dissipation losses in primary switch means 140.
  • Timing Diagram 200 Also shown in Timing Diagram 200 is a first switching-event sequence 230 and a second switching- event sequence 240, which are used later with reference to FIGURES 8 and 9 in discussing the operation of
  • Sequences 230 and 240 each divides a single switching cycle into six continuous, non-overlapping segments: segments 1, 2, 3, 4, 5, and 6 for sequence 230 and segments 1, 2', 3', 4', 5 and 6 for sequence 240.
  • the boundary of each segment is defined by a switching event in one of the switch means, 130, 140, and 150.
  • Sequence 230 corresponds to the case-where second switch means 150 is opened after primary switch means 140 is opened, as shown in window 224
  • sequence 240 corresponds to the case where second switch means 150 is opened before primary switch means 140 is opened, as indicated by line 226.
  • Exemplary qualitative steady-state waveforms for the key voltages and currents of forward converter 100 under switching-event sequences 230 and 240 are shown in timing diagram 300 in FIGURE 8 and a timing diagram 400 in FIGURE 9, respectively.
  • each winding of transformer 120 has the same number of turns and has no parasitic resistance and transformer 120 is operated in the linear regime of its B-H
  • rectifier 160 has a nominal voltage drop for forward conducting current, a near zero current conduction for reverse applied voltage and a nominal amount of reverse-recovery current. To simplify the discussion of forward converter 100 and without loss of generality, the output voltage across load 174 is taken to be constant at a value of
  • load 174 is taken to be resistive in nature and an exemplary duty-cycle of 33.3%, which is consistent with an output voltage V OUT of V 0 /3, is used for primary switch means 140.
  • FIGURE 8 the operation of primary switch means 140 is shown in graph 301, the operation of first switch means 130 is shown in graph 302, and the
  • second switch means 150 is shown in graph 303.
  • Graphs 301-303 are each in the form of a time line waveform which indicates that its corresponding switch means is closed when the waveform is high and that its corresponding switch means is open when the waveform is low.
  • Sequence 230 of FIGURE 7 is reproduced as sequence 304 in FIGURE S.
  • the operation of primary switch means 140 is shown in graph 401
  • the operation of first switch means 130 is shown in graph 402
  • second switch means 150 is shown in graph 403.
  • Graphs 401-403 are each in the form of a time line waveform which indicates that its
  • Sequence 240 of FIGURE 7 is reproduced as sequence 404 in FIGURE 9.
  • the time- scale during each of these segments is expanded by roughly an order of magnitude with respect the time- scale used during segments 2/2', and 5 (i.e., the waveforms are "stretched out" during segments l, 3/3', 4/4' and 6).
  • the winding voltages V P and V S and the voltage V 1 are shown in graph 310.
  • the total primary current I P and the current I CS into capacitor C S are shown in graph 320
  • the magnetizing current I M in inductor 123 and the current I 1 in primary winding 122 are shown in graph 330
  • the current I CC flowing into storage capacitor 134 is shown in graph 340 in FIGURE 8.
  • the output voltage V OUT at load 174 and the voltage V 2 are shown in graph 350
  • the currents I S2 and 1 CR2 in second switch means 150 and rectifier 160 (CR2) are shown in graph 360
  • the current I LOUT in choke inductor 170 and the current I LOAD in load 174 are shown in graph 370 in FIGURE 8.
  • the winding voltages V P and V S and the voltage V 1 are shown in graph 410.
  • the total primary current IP and the current I CS into capacitor C S are shown in graph 420
  • the magnetizing current I M in inductor 123 and the current I 1 in primary winding 122 are shown in graph 430
  • the current I CC flowing into storage capacitor 134 is shown in graph 440 in FIGURE 9.
  • the output voltage V OUT at load 174 and the voltage V 2 are shown in graph 450
  • the currents I S2 and I CR2 in second switch means 150 and rectifier 160 (CR2) are shown in graph 460
  • the current I LOUT in choke inductor 170 and the current I LOAD in load 174 are shown in graph 470 in FIGURE 9.
  • primary switch means 140 comprises a
  • segment 1 is sufficiently long to allow the transistor switching device to reach a full conducting state (i.e., lowest conducting resistance) after being switched on at the beginning of segment 1.
  • the conductio. of current in secondary 124 is held off until segment 2/2', at which time the transistor switching device of primary switch means 140 has lowered its ON-resistance to the point that the addition of the reflected secondary current will not substantially raise the voltage across the device's conducting terminals and, hence, will not increase the power dissipation in the device.
  • second switch means 150 is closed.
  • the voltage of V 0 appearing across secondary winding 124 and the closing of switch means 150 causes a current to flow through secondary winding 124 and a corresponding current to flow in primary winding 122, due to transformer action.
  • the magnetizing current in inductor 123 continues to increase at a constant rate due to the application of a constant voltage of V 0 across inductor 123 by voltage source 110. During this segment, power is transferred to the secondary circuit from the primary circuit.
  • First switch means 130 may then be closed with zero volts across its conduction terminals, a zero-voltage-switching condition, to start segment 5.
  • a zero-voltage-switching condition for switch means 130 is shown at 312 in graph 310, where voltage V 1 reaches the voltage on the positive terminal of storage capacitor 134.
  • the voltage on the positive terminal of storage capacitor 134 is equal to 3/2V 0 .
  • first switch means 130 may be closed with zero volts across its conduction terminals, a zero- voltage-switching condition, to start segment 5.
  • FIGURE 9 the zero-voltage-switching condition is shown at 412 in graph 410, where voltage V 1 reaches the voltage on the positive terminal of storage capacitor 134.
  • the voltage on the positive terminal of storage capacitor 134 is equal to 3/2V 0 .
  • primary switch means 140 and second switch means 150 are opened and first switch means 130 is closed.
  • the voltage across primary winding 122 and secondary winding 124 is set at a negative value equal to the voltage V C across storage capacitor 134, approximately -V 0 /2.
  • the magnetizing current I M is diverted away from charging stray
  • the capacitance of storage capacitor 134 is large enough so that the voltage across storage capacitor 134 does not substantially change during segment 5. (The zero-voltage switching on
  • segment 6 the magnetizing current is diverted away storage capacitor 134 towards stray capacitor 132, where it discharges stray capacitor 132. As a result, the voltage V 1 is reduced in value towards zero volts. Unlike converter 3000, the secondary circuit in converter 100 is prevented from interfering with the discharging of stray capacitor 132 since second switch means 150 is opened during segment 6. At the end of segment 6, voltage V 1 is decreased to a value of zero volts and primary switch means 140 is closed with a zero-voltage-switching condition to start segment 1.
  • the time-integrated voltage across inductor 123 should be zero for each switching cycle during the steady-state
  • Capacitor 134 is at a value which sets the time-integrated voltage across inductor 123 to zero during each switching cycle. This value is referred to as the required value for V C which prevents core saturation and is similar to the required value V CSS determined for forward converter 3000. Given the additional segments present for converter 100, specifically segments 1, 3/3', 4/4' and 6, the calculation of the exact value for V CSS is more complex. In practice, however, the
  • duration of segments 1, 3/3', 4/4' and 6 are extremely small compared to the duration of segments 2/2' and 5, and the above equation (2) for V CSS in converter 3000 serves as a good approximation for V CSS in converter 100.
  • the voltage V C and the magnetizing current I M interact so as to center the I M waveform around a value of substantially zero
  • V CSS for storage capacitor 134 is reached during power-up
  • the input voltage (V 0 ) is set at 300V to deliver a typical output current of 1.0A at an output voltage ( OUT ) of
  • Primary switch means 140 comprises a field-effect transistor having a breakdown voltage of 800V and an on-resistance of 3 ohms (part number IRFBE30 from International Rectifier
  • first switch means 130 comprises a field-effect transistor having a breakdown voltage of 800V and an on-resistance of 6 ohms (part number IRFBE20 from International Rectifier Corporation), and second switch means 150 comprises a field-effect transistor having a breakdown of 600V and an on-resistance of 2.2 ohms (part number IRFBC30 from International Rectifier
  • storage capacitor 134 (C C ) has a capacitance of approximately 2200pF
  • stray capacitor 132 (C S ) has a capacitance of approximately 140pF
  • transformer 120 has an
  • switch control means 180 shown in FIGURE 6 may comprise a digital
  • microprocessor for generating the control signals for primary switch means 140, first switch means 130, and second switch means 150 according to the timing
  • FIGURE 7 Given the inductance L M of the magnetizing inductor 123 and capacitance C S of stray capacitor 132, the duration of the segments 1, 2/2', 3/3', 4/4', 5 and 6 required for providing zero-voltage switching can be calculated as a function of duty-cycle for the steady-state operation of converter 100. These values may be stored in a conventional memory accessible to the microprocessor and the microprocessor may select the appropriate value for each segment as dictated by the then current value of the duty-cycle.
  • switch control means 180 In a further microprocessor-based embodiment of switch control means 180, it may be appreciated that active voltage sensors may be coupled to primary switch means 140 and first switch means 130 for detecting zero-voltage conditions across their respective switch means. The microprocessor of switch control means 180 may then use this information in setting the duration of segments 3/3', 4/4' and 6 rather than using predetermined stored values for such segments.
  • the advantage of this more active approach is that the zero-voltage-switching conditions may be achieved in transient conditions as well as steady-state conditions. Additionally, the zero-voltage-switching conditions are no longer
  • forward converter 100 may be constructed with components having wider parameter ranges and tolerances, leading to higher yields and lower unit costs in the manufacturing of forward converter 100.
  • Embodiments 540 and 530 are shown in the context of a partial block diagram 500 of forward converter 100, which is shown in FIGURE 6.
  • Primary switch means 540 comprises a parallel
  • Primary switch means 540 is oriented in forward
  • first switch means 530 comprises a parallel combination of a rectifier 531 and a switch means 532.
  • First switch means 530 is oriented in forward converter 100 such that rectifier 531 conducts a current directed from voltage node V 1 to storage capacitor 134 (e . g. , the anode of rectifier 531 is coupled to voltage node V 1 ).
  • Rectifier 541 conducts current from voltage source 110 to the node V 1 when the voltage between node V 1 and the negative terminal of voltage source 110 becomes zero or negative.
  • this condition occurs when voltage V 1 is driven to zero volts in segment 6, as shown at points 311 and 313.
  • the current in primary switch means 540 may be conducted by rectifier 541 during the first part of segment 1 and, possibly, segment 2/2', if switch means 542 is not closed. If switch means 542 remains open, rectifier 541 will continue to conduct current during segments 1 and 6 as long as the primary current, shown at graph 320 in FIGURE 8 and 420 in FIGURE 9, remains negative.
  • the incorporation of rectifier 541 with switch means 540 provides a relatively wide window in which switch means 542 may be closed with respect to the opening of first switch means 530.
  • rectifier 531 conducts current from node V 1 to the positive terminal of storage capacitor 134 when the voltage at node V 1 is equal to or greater than the voltage at the positive terminal of capacitor 134.
  • this condition occurs when the voltage V 1 is being driven to a high positive voltage at the end of segments 4/4' by the magnetizing current I M , as shown at 312 and 412, respectively.
  • switch means 532 is not closed, the current in first switch means 530 may be conducted by rectifier 531 during the first part of segment 5 since the direction of the magnetizing current is the same as the conducting direction of rectifier 531, as shown at graphs 330,340 and 430,440 in FIGURES 8 and 9.
  • rectifier 531 will continue to conduct the current through first switch means 530 until the magnetizing current I M reverses direction half-way through segment 5, assuming steady-state operating conditions. The closing of switch means 532 may then be delayed until the midpoint of segment 5, assuming steady-state
  • rectifier 531 with switch means 530 provides a
  • switch means 532 may be closed with respect the the opening of primary switch means 540.
  • rectifier 531 comprises means for detecting a zero-voltage-switching condition across first switch means 530 and means for initially conducting current through switch means 530 upon the occurrence of a zero-voltage-switching condition across switch means 530.
  • rectifier 541 comprises means for detecting a zero-voltage-switching condition across primary switch means 540 and means for initially conducting current through switch means 540 upon the occurrence of a zero-voltage-switching condition across switch means 540.
  • the timing for the closing of switch means 532 and switch means 542 is not as critical.
  • the detecting and conducting means provided by rectifiers 531 and 532 may be used in a number of ways, as described below.
  • first switch means 530 and primary switch means 540 may be controlled by the
  • switch control means 180 determines the length of each segment as a function of the duty-cycle.
  • switch means 542 of primary switch means 540 is operated as shown in graph 205 in FIGURE 7 and switch means 532 of first switch means 530 is operated as shown in graph 210 in FIGURE 7.
  • This implementation would ensure zero-voltage-switching conditions for steady-state operating conditions and for some, but not all, transient conditions and parameter variations. More specifically, zero-voltage switching would occurs for those transient conditions and
  • zero-voltage-switching can occur for the above latter cases. This may be accomplished by increasing the delay in closing switch means 532 (first switch means 530) after the opening of primary switch means 540, which normally equal to the sum of segments 3 and 4/4', and by increasing the delay in closing switch means 542 (primary switch means 540) after the opening of first switch means 530, which is normally equal to the duration of segment 6. Under steady-state
  • the increase of the delay in closing switch means 532 causes rectifier 531 to conduct and to
  • switch means 530 and 540 may be used with an embodiment of switch control means 180 which is less complex than the above
  • the delay in closing switch means 542 (primary switch means 540) after the opening of switch means 532 (first switch means 530) is set to a predetermined, fixed value. Since a fixed delay value is used, the
  • the fixed delay value is applicable to a predetermined range of duty-cycles and is set to the longest time duration for segment 6 in the given range of duty-cycles.
  • rectifier 541 begins to conduct at the same point switch means 542 is closed. As the duty-cycle increases with respect to the lowest value, rectifier 541 conducts prior to the closing of switch means 542 and pro/ides for zero-voltage switching for primary switch means 540.
  • the delay in closing switch means 532 (first switch means 530) after the opening of switch means 542 (first switch means 540) may be set to a predetermined, fixed value for a predetermined range of duty-cycles.
  • sequence 230 shown in
  • the fixed delay value is set to the longest time duration of the sum of segments 3 and 4 in the given range of duty-cycles. Assuming a steady-state operation for converter 100, the longest duration for the sum of segments 3 and 4 occurs for the lowest duty- cycle in the given range. In the case of sequence 240, shown in FIGURE 7, the fixed delay value is set to the longest time duration of segment 4' in the given range of duty-cycles. Assuming a steady-state operation for converter 100, the longest duration for segment 4' also occurs for the lowest duty-cycle in the given range.
  • rectifier 531 begins to conduct at the same point switch means 532 is closed. As the duty-cycle increases with respect to the lowest value, rectifier 531 conducts prior to the closing of switch means 532 and provides for zero-voltage switching for primary switch means 530.
  • the input PWM duty-cycle signal to port 601 may be generated by means well known to the power-supply switching art and an illustration of such means is not necessary in order to understand the present invention and enable one of ordinary skill in the art to make and use the present invention.
  • the signal applied to port 601 may be generated by the UC1825 High Speed PWM
  • the UC1825 Controller compares the voltage of the load, such as load 174 in FIGURE 6, against a predetermined target value and varies the duty cycle of its PWM output signal so as to keep the voltage of the load at the target value.
  • Control means 600 further comprises two two-input NOR gates 620 and 630, an inverter 640, and three delay units 650, 660, and 670.
  • the duty-cycle signal at input port 610 is coupled to an input of NOR gate 620 and, via inverter 640, to an input of NOR gate 630.
  • the output of NOR gate 620 is coupled to the other input of NOR gate 630 via delay unit 660.
  • the output of NOR gate 630 is coupled to the other input of NOR gate 620 via delay unit 650.
  • the output of NOR gate 630 provides the control signal for primary switch means S PR (shown at 540 in FIGURE 10 and at 140 in FIGURE 6) and the output of NOR gate 620 provides the control signal for first switch means S 1 (shown 530 in FIGURE 10 and at 130 in FIGURE 6).
  • the coupling of NOR gates 620, 630, delay units 650, 660, and inverter 640 in the above described manner comprise means well known in the digital clocking art for generating two non-overlapping clock signals (ports 610 and 611) from a single input clock signal (port 601).
  • the signal value at port 610 follows the signal value at input port 601 and the signal value at port 611 follows the inversion of the signal value at input port 601.
  • the signal transition at port 610 from a logic-high level to a logic-low level (falling edge) follows the falling edge transition at input port 601 with substantially no delay. This is because the output of delay unit 660 is at a logic-low level prior to this transition, thus allowing the output signal from inverter 640 to determine the output of NOR gate 630.
  • the signal transition at port 610 from a logic-low level to a logic-high level (rising edge) follows the rising edge transition at input port 601 with a delay substantially determined by delay unit 660 (delay unit 2). This is because both input signals to
  • NOR gate 630 are both at logic-high levels just prior to the rising edge transition at port 601 and both inputs of NOR gate 630 must be at logic-low levels to cause a rising edge transition at port 610, with the last input of NOR gate 630 being changed to a logic-low level by delay unit 660.
  • transition at port 611 from a logic-high level to a logic-low level follows the rising edge transition at input port 601 with substantially no delay. This is because the output of delay unit 650 is at a logic-low level prior to this transition, thus allowing the signal at input port 601 to determined the output of NOR gate 620.
  • the signal transition at port 611 from a logic-low level to a logic-high level (rising edge) follows the falling edge transition at input port 601 with a delay substantially determined by delay unit 650 (delay unit 1).
  • both input signals to NOR gate 620 are both at logic-high levels just prior to the falling edge transition at port 601 and both inputs of NOR gate 620 must be at logic-low levels to cause a rising edge transition at port 611, with the last input of NOR gate 620 being changed to a logic-low level by delay unit 650.
  • non-overlapping control signals are generated at output ports 610 and 620 with a delay Dl (determined by delay unit 650) occurring between the falling edge of the signal at port 610 and the rising edge of the signal at port 611 and a delay D2 (determined by delay unit 660) occurring between the falling edge of the signal at port 611 and the rising edge of the signal at port 610.
  • Dl determined by delay unit 650
  • D2 determined by delay unit 660
  • port 601 comprises means for receiving a PWM duty cycle signal generated by standard control means in the switching power supply art.
  • NOR gates 620, 630, delay units 650,660, and inverter 640 comprise means, responsive to the received duty cycle signal, for generating a first control signal at port 610 which directs the operation of the primary switch means and a second control signal at port 611 which directs the operation of the first switch means.
  • each of the first and second control signals have a first state (logic-high level) indicating that its respective switch means is to be closed and a second state (logic-low level) indicating that its respective switch means is to be open.
  • the first and second control signals are generated such that only one of the control signals is in the first state (logic-high level) and are referred to as "non- overlapping" signals.
  • control means 600 For generating the control signal for secondary switch means S 2 shown at 550 in FIGURE 10 (or at 150 in FIGURE 6), control means 600 further comprises a delay unit 670 coupled between the output of NOR gate 630 and output port 612.
  • the control signal for primary switch means S PR propagates through delay unit 670, thus generating a control signal for second switch means S 2 which follows the control signal for primary switch means S PR and is delay by a fixed amount. In this manner, control means 600 provides a switching sequence similar to sequence 230 shown in FIGURE 7.
  • delay unit 670 as coupled to NOR gate 630, comprises means for generating a third control signal at port 612 to direct the
  • the logic-low level state of the third control signal comprises a first state indicating that second switch means S 2 is to be closed (logic-high level) and that the logic-high level state of the third control signal comprises a second state indicating that second switch means S 2 is to be opened.
  • the third control signal enters its first state (logic-high level) a predetermined time duration after the first control signal at port 610 enters its first state, and the third control signal at port 612 enters its second state (logic low level) a predetermined time duration after the first control signal at port 610 enters its second state.
  • each of the delay units 650, 660 and 670 may comprise a first digital inverter having its input as the input of the delay unit and its output coupled to the input of a second digital inverter, the output of the second inverter being the output of the delay unit.
  • the delay introduced by this delay unit would be equal to the sum of the propagation delays of the two digital inverters.
  • Such an exemplary delay unit may further comprise a standard RC delay circuit coupled between the output of the first digital inverter and the input of the second digital inverter for introducing addition delay time, if required.
  • a further object of the present invention is to provide a switch control means for the second switch means S 2 (150 or 550) of the present invention which is autonomous from the switch control means for primary switch means 140 and first switch means 130, shown in FIGURE 6. As will be made apparent below, the
  • FIGURE 12 an exemplary embodiment of second switch means 150 is shown at 750 in FIGURE 12.
  • Embodiments 730 and 750 are shown in the context of a partial block diagram 700 of forward converter 100, which is shown in FIGURE 6.
  • the present invention recognizes that a control signal for controlling second switch means 150 may be derived from the voltage across secondary winding 124 in the following manner. Referring back to timing diagram 300 shown in FIGURE 8, it may be seen that for switching sequence 230 (of FIGURE 7), the voltage waveform V S for secondary winding 124 crosses zero volts, as indicated at a point 314 in FIGURE 8, at substantially the same time secondary switch means 150 is closed. The zero crossing occurs as V S changes from a positive value to a negative value and is referred to as a negative
  • secondary switch means 150 thereafter opens a time duration after the voltage waveform V S for secondary winding 124 crosses zero volts, indicated at a point 315 in FIGURE 8, as V S changes from a negative value to a positive value. This is referred to as a positive transition due to the positive slope of the V S waveform.
  • secondary switch means 150 may be controlled in response to the voltage V S of secondary winding 124 by detecting the transitions of the V S waveform with respect to a predetermined voltage value, e.g., zero volts, and by directing second switch means 150 to open a short time (short time duration) after voltage V S makes a negative transition through the predetermined voltage value and to close a somewhat longer time (longer time duration) after voltage V S makes a positive transition through the predetermined voltage value.
  • the length of the second duration may be chosen (i.e., made large enough) such that second switch means 150 is closed after primary switch means 140 closes for a wide range of duty-cycles and load conditions.
  • a switch control means may be constructed for second switch control means 150 which may be autonomous from the switch control means for primary switch means 140 and first switch means 130.
  • Such an autonomous switch control means is provided by switch control means 730 shown in FIGURE 12.
  • Autonomous switch control means 730 comprises a series combination of a resistor 732 and a Zener diode 734 which is coupled in parallel across secondary winding 124.
  • the the cathode terminal of Zener diode 734 is coupled to a node 738 and the anode terminal of Zener diode 734 is connected to the negative terminal of secondary winding 124, which serves as a secondary-side ground.
  • Resistor 732 is connected between the positive terminal of secondary winding 124 and node 738.
  • a rectifier 736 is coupled in parallel with Zener diode 734 with its cathode terminal coupled to the secondary-side ground.
  • a positive voltage of, for example, 4.8V is generated at node 738 by Zener diode 734 when a positive potential appears across secondary winding 124 to direct current towards load 174.
  • a negative voltage appears across secondary winding 124, a negative voltage of approximately -0.6V is generated at node 734 by rectifier 736. As such, it may be
  • resistor 732, diode 734, and rectifier 736 comprise detection means for detecting the voltage across secondary winding 124 and for generating a signal at node 738 having a first state (4.8V, logic high) when the voltage across secondary winding 124 is positive and a second state (-0.6V, logic low) when the voltage across secondary winding 124 is negative.
  • Autonomous switch control means 730 further comprises a delay generation means responsive to the signal at node 738 for generating a switch control signal at a node 746 to control second switch means 750.
  • the control signal at node 746 has a first state (logic-high) for directing second switch means 750 to close and a second state (logic low) for directing second switch means 750 to open.
  • the delay generation means comprises a first inverter 740 having an input coupled to node 738 and an output, a second inverter 745 having an input coupled to the output of first inverter 740 and an output terminal coupled to node 746 for providing the control signal.
  • Inverters 740 and 745 are powered by the potential difference between a conventional digital V CC supply (for.
  • inverter 745 has a logic low state at around zero volts and a logic high state at around V CC (+5) volts.
  • inverter 745
  • the delay generation means of control means 730 further comprises a delay means having a rectifier 741, a resistor 742 and a capacitor 744 for introducing first and second predetermined time delays into the signal propagation between first inverter 740 and second
  • the delay means introduces a first predetermined signal propagation delay between first inverter 740 and second inverter 745 when the output of inverter 740 makes a transition from a logic-low level to a logic-high level. Additionally, the delay means introduces a second predetermined signal propagation delay between first inverter 740 and second inverter 745 when the output of inverter 740 make a transition from a logic-high level to a logic-low level.
  • the anode terminal of rectifier 741 is connected to the output of inverter 740 and the cathode terminal of rectifier 741 is connected to the input of inverter 745 at a node 743.
  • Capacitor 744 is coupled between the input of inverter 745 and ground and resistor 742 is also coupled between the input of inverter 745 and ground.
  • rectifier 741 When the output of inverter 740 makes a transition from a logic-low level to a logic-high level, rectifier 741 conducts and current from inverter 740 charges capacitor 744 to raise the voltage at node 743.
  • the component values of rectifier 741, resistor 742, and capacitor 744 are chosen in a manner well known in the art such that the voltage at node 743 rises to a logic-high value in a time duration which is relatively short with respect to the switching cycle time. This provided the above first predetermined signal propagation delay.
  • rectifier 741 blocks current from flowing from capacitor 744 into inverter 740 and, as such, the charge on capacitor 744 supporting the voltage on node 743 is discharged to ground by resistor 742.
  • the component values of resistor 742 and capacitor 744 are chosen in a manner well known in the art such that the voltage at node 743 falls to a logic-low level in a time duration which is relatively longer than the rise time duration for the voltage at node 743. This provides the above second predetermined signal propagation delay
  • inverter 745 means other than rectifier 741, resistor 742, capacitor 744, and the particular
  • arrangement of these components may by used to provide the first and second predetermined propagation delays.
  • the control signal at node 746 tracks the detected signal at node 738 and is delayed with respect the signal at node 738 by one of two predetermined time durations, the time duration being selected by the direction of the logic transition (positive transition and negative transition). As a result, the control signal at node 746 enters its first state (logic-high level) a first predetermined time duration after the signal at node 738 enters its first state (logic-high level), the first predetermined time duration being related to the second (longer) signal propagation delay generated by resistor 742 discharging capacitor 744.
  • control signal at node 746 enters its second state (logic-low level) a second predetermined time duration after the signal at node 738 enters its second state (logic-low level), the second predetermined time duration being related to the first (shorter) signal propagation delay generated by the charge of capacitor 744 through rectifier 741.
  • the control signal generated at node 746 in this way is provided to
  • Second switch means 750 comprises an n-channel enhancement-type field effect transistor 752 having a gate terminal, a drain terminal connected to secondary winding 124, and a source terminal coupled to node V 2 shown in FIGURE 6.
  • the coupling means of switch control means 730 further comprises a coupling
  • transformer 780 having a first winding 782 and a second winding 784.
  • First winding 782 has a first terminal coupled to node 746 for receiving the switch control signal and a second terminal coupled to the secondary- side ground.
  • Second winding 784 has a first terminal coupled to the gate of transistor 752 and a second terminal coupled to the source of transistor 752.
  • the magnetic reference convention for transformer 780 is such that a reference dot appears at the first terminals of windings 782 and 784.
  • transformer 780 provides means for translating the potential voltage generated at node 746 to a potential difference generated across the gate and source terminals of transistor 784.
  • transistor 752 conducts current between its drain and source terminals when the control signal at node 746 is in its first state (logic- high level) since the positive voltage at node 746 is translated by transformer 780 to provide a positive gate-to-source voltage for transistor 752.
  • transformer 780 comprises means for coupling the control signal at node 746 to transistor 752 of second switch means 750.
  • a resistor 786 may be included in series with second winding 784 to damp any oscillations that may occur by any resonance formed by the gate capacitance of transistor 752 and the leakage inductance of second winding 784.
  • field effect transistor 750 may further include a parasitic substrate diode, as indicated at 754 in FIGURE 12.
  • the inclusion of parasitic substrate diode 754 depends upon the particular transistor component used for transistor 752. If parasitic substrate diode 754 exists as part of field effect transistor 752, an undesired current will be conducted from the source terminal to the drain terminal when a negative drain-to-source voltage is applied across transistor 752.
  • a blocking rectifier 756 coupled in series between the drain terminal of transistor 752 and secondary winding 124 may be included. As shown in FIGURE 12, blocking rectifier 756 is oriented such that current conducted by parasitic substrate diode 754 is prevented from entering secondary winding 124. If transistor 752 does not include parasitic substrate diode 754, blocking
  • rectifier may be removed so as to directly couple the drain of transistor 752 to secondary winding 124.

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  • Dc-Dc Converters (AREA)

Abstract

On décrit un circuit d'utilisation du courant de magnétisation dans le transformateur d'un convertisseur pour remettre à zéro le noyau du transformateur et pour obtenir une condition de commutation à tension nulle au niveau de l'interrupteur du primaire du convertisseur. Le convertisseur comprend un transformateur muni d'un enroulement primaire et d'un enroulement secondaire, l'enroulement secondaire étant couplé à une charge de sortie et l'interrupteur du primaire étant relié en série entre l'enroulement du primaire et une source de tension. La fermeture de l'interrupteur du primaire a pour résultat le stockage d'énergie dans le transformateur, et l'ouverture de l'interrupteur du primaire provoque la libération de l'énergie du transformateur. Le circuit d'utilisation comprend une combinaison en série d'un condensateur de stockage et d'un premier interrupteur relié en parallèle à l'un des enroulements du transformateur pour recevoir l'énergie libérée par le transformateur. L'énergie ainsi libérée est utilisée pour remettre à zéro le noyau du transformateur et pour créer une condition de commutation à tension nulle au niveau de l'interrupteur du primaire. Un deuxième moyen d'interruption est relié en série avec le deuxième enroulement du tranformateur et est utilisé pour empêcher que les effets de la charge imposée par le secondaire interrompent la création de la condition de commutation à tension nulle.
PCT/GB1992/000450 1991-03-13 1992-03-12 Convertisseur d'energie commutable a tension nulle WO1992016995A1 (fr)

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US07/668,587 US5173846A (en) 1991-03-13 1991-03-13 Zero voltage switching power converter

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US5309344A (en) 1994-05-03
US5331533A (en) 1994-07-19

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