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WO1991010261A1 - Structure d'interconnexion pour dispositif semiconducteur utilisant un isolateur en polyimide - Google Patents

Structure d'interconnexion pour dispositif semiconducteur utilisant un isolateur en polyimide Download PDF

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Publication number
WO1991010261A1
WO1991010261A1 PCT/US1990/007401 US9007401W WO9110261A1 WO 1991010261 A1 WO1991010261 A1 WO 1991010261A1 US 9007401 W US9007401 W US 9007401W WO 9110261 A1 WO9110261 A1 WO 9110261A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
polyimide
over
metal
aperture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1990/007401
Other languages
English (en)
Inventor
Maureen A. Anthony
Melanie Chow
Louis L-C Hsu
Rajiv V. Joshi
James F. White
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of WO1991010261A1 publication Critical patent/WO1991010261A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

Definitions

  • the present invention is directed generally to semiconductor devices and processes and more particularly to an interconnection structure for semiconductor devices utilizing a polyimide insulator.
  • LSI and VLSI very large scale integrated circuit
  • Such electrical contacts and interconnections are formed in multiple levels, adjacent interconnect levels being separated by layers of insulating material. Vias or holes are formed through the insulating layers to accommodate contacts to the devices and contacts between levels.
  • Such interconnect structures are referred to in the art as "personalization” or "back-end metallization” .
  • U.S. patent no. 4,822,753 to Pintchovski et al. shows a device structure including an aluminum line connected to a suicided device region by a tungsten stud.
  • the tungsten stud which includes a titanium-nitride via liner, extends through an insulating layer comprised of an oxide, a nitride, or a glass.
  • Many techniques are known in the art whereby this structure can be extended upward (i.e. away from the surface of the semiconductor device) to provide multiple levels of wiring.
  • polyimides exhibits a low dielectric constant which makes it particularly desirable for use as the insulating layer in the above-described interconnect structures.
  • U.S. patent no. 4,560,436 to Bukhman et al. shows a process of forming tapered vias in a polyimide insulating layer.
  • Polyimides also suffer from certain disadvantages, not the least of which is the frangible nature of the material itself. Polyimides are particularly susceptible to contamination and subsequent breakdown caused by the materials and processes conventionally used in semiconductor processing. Many etchants, for example, are very detrimental to polyimide, as are many of the metals used to make the interconnections.
  • European patent application EPA 0 195 977 by Manley et al. shows a process wherein polyimide is used to provide planar insulating levels in a personalization structure for a field effect transistor (FET) .
  • FET field effect transistor
  • the polyimide insulator preferably covered with silicon dioxide, is etched to provide vias. The bottoms of these vias are treated to act as an activator, for example by roughening the polyimide, so as to attract selectively deposited tungsten.
  • This process of using polyimide insulator with selectively deposited tungsten is repeated to provide a multi-level interconnect structure.
  • the Manley et al. process suffers from several significant disadvantages, including the tendency for the tungsten metal to damage the exposed polyimide.
  • the use of selectively deposited tungsten is not readily adaptable to device surfaces of varying topology, as shallow vias will over-fill while deep vias are being filled.
  • Selective deposition of metals does not fill vias well, i.e. it tends to leave voids, for example due to out-gassing of the unprotected polyimide (termed
  • An object of the present invention is to provide a new and improved semiconductor interconnect structure utilizing polyimide as an insulator, and a method of manufacturing the same.
  • Another object of the present invention is to provide such a method and apparatus which is readily applicable for forming interconnections to device structures having features of varying heights.
  • a further object of the present invention is to provide such a method and apparatus which accommodates the use of different types of conductors at different levels in the structure.
  • a semiconductor structure comprising: a substrate of semiconductor material including a device region on a surface of the substrate whereat it is desired to provide a conductive contact; a layer of polyimide over the surface of the substrate; an aperture in the layer of polyimide exposing the device region; a lining of metal over the surface of the aperture; and, a stud of refractory metal filling the lined aperture so as to form a conductive contact to the device region.
  • a process comprising the steps of: providing a substrate of semiconductor material including a device region on a surface of the substrate whereat it is desired to provide a conductive contact; forming a layer of polyimide over the surface of the substrate; forming an aperture in the layer of polyimide to expose the device region; forming a lining of metal over the surface of the aperture in the polyimide layer; depositing a layer of refractory metal conformally over the substrate so as to substantially fill the lined aperture in the polyimide layer; and planarizing the refractory metal layer; whereby a conductive contact is formed to the device region.
  • FIGS. 1-9 are cross-sectional views showing consecutive steps in the fabrication of a field-effect transistor (FET) including an interconnect structure constructed accordance with the present invention.
  • FET field-effect transistor
  • FIGS. 10-12 are cross-sectional views highlighting a feature of the present invention utilized to overcome an undercutting problem encountered when etching vias in polyimide.
  • FIG. 1 shows a field-effect (FET) transistor 20 fabricated on a major surface 22 of an N ⁇ silicon substrate 24.
  • FET 20 includes highly doped P + source and drain regions 26, 28, respectively, these source and drain regions formed adjoining surface 22 and spaced by a channel region 30 of substrate 24 therebetween.
  • a gate structure is provided including a conductive gate contact 32 overlying and spaced from the surface of channel 30 by a thin layer 34 of insulating material.
  • Contact 32 comprises, for example, metal or doped polysilicon
  • insulator 34 comprises, for example, thermally grown silicon dioxide ⁇ SiO bombard) .
  • FET 20 further includes oxide sidewall spacers
  • FET 20 and electrically isolating the FET from other devices (not shown) formed in substrate 24.
  • FET 20 with its associated features comprises a conventional device in the art, and many methods are known for manufacturing the same.
  • the detailed method of constructing FET 20 with isolation region 40 does not comprise part of the present invention, and need not be detailed herein.
  • a thin layer 44 of an inorganic insulating material preferably silicon nitride (Si-,N.) , is deposited conformally over the structure described above, including FET 20 and field isolation region 40.
  • Layer 44 is formed, for example, to a thickness of about 2,000 Angstroms. Layer 44 functions to block out mobile ion contamination from subsequently deposited materials.
  • a layer 46 of polyimide is deposited over layer 44 to a thickness greater than that of the step-height 48 between the top of contact 32 and surface 22 - for example to a thickness of about 2.5 micrometers.
  • Polyimide 46 preferably comprises a thermally stable polyimide capable of sustaining high temperature operation in the range of about 450-500 degrees centigrade, for example PIQ L-100 as available from the Hitachi Corporation.
  • a layer 49 of epoxy or resin is spun in a conventional manner onto the surface of polyimide layer 46 so as to yield a plan- arized upper surface 48A.
  • the device of FIG. 2 is then subjected to a blanket etching process, for example a reactive ion etch (RIE) using oxygen plasma, which is continued through layer 49 and into layer 46 so as to planarize the top surface of poly ⁇ imide layer 46.
  • RIE reactive ion etch
  • polyimide layer 46 is shown with upper surface 46A planarized in the manner described above.
  • a layer 50 of inorganic insulating material for example comprising silicon nitride, silicon dioxide, or glass, is deposited onto the surface of layer 46 to a thickness of about 3,500 Angstroms.
  • layer 50 comprises an important feature of the present invention, functioning variously as: an etch stop, a polishing stop, and as a getterer to protect the underlying polyimide from damage by subsequent processing steps.
  • Via 54 extends from the surface of layer 50 downward through layers 50, 46, and 44, to expose a surface portion of gate contact 32. Vias 52 and 54 likewise extend downward through the same layers to expose surface portions of source and drain regions
  • Vias 52, 54, 56 are formed, for example, by using a CF. plasma to etch through layer 50, an oxygen plasma to etch through layer 46, and, after removing the photoresist mask, another CF. plasma to etch through the exposed portion of layer 44.
  • etching polyimide layer 46 with an oxygen plasma permits complete, and even over-etching without damage to underlying substrate
  • a thin layer 58 of a conductive material is deposited conformally over the structure.
  • Layer 58 is selected to form a diffusion barrier between layers 48, 50 and a subsequently deposited refractory metal, and preferably comprises a two layer structure: a first layer of titanium (Ti) , and a second level of titanium-nitri.de (TiN) .
  • Layer 58 can be formed, for example, by first sputtering titanium conformally over the device to a thickness of about 500 Angstroms, and then sputtering titanium-nitride conformally over the titanium to a thickness of about 500 Angstroms.
  • tungsten layer 60 is formed by chemical vapor deposition (CVD) of the tungsten at a temperature in the range of about 300-420 degrees centigrade and at a pressure in the range of about 5-50 Torr.
  • CVD chemical vapor deposition
  • This CVD process can utilize a conventional tungsten source gas, for example WFg+SiH 4 +H 2 .
  • tungsten layer 60 is able to fill vias 52, 54, and 56 evenly and without gaps, even when the vias have very high aspect ratios - i.e. on the order of 1:4.
  • inorganic layer 50 functions to protect polyimide layer 46 from the degrading and corrosive effects of the metal formation processes, particularly of the corrosive effects of the gas used in the CVD tungsten process.
  • Layer 58 functions to improve the adhesion of tungsten layer 60 to the device, and to lower the contact resistance of the tungsten to the underlying device regions.
  • FIG. 7A shows an alternate embodiment of the invention wherein layers 50 and 46 have been removed by etching and replaced with a silicon dioxide (or quartz) insulator 63.
  • Layers 46 and 50 can be re ⁇ moved, for example, by RIE processing with a CF./0 2 plasma.
  • Layer 63 can be deposited using a conventional chemical vapor oxide deposition (CVD) process, and then planarized using a conventional chemical-mechanical polishing process to yield the structure shown in FIG. 7A.
  • CVD chemical vapor oxide deposition
  • a thin layer 64 of a conductive material is deposited conformally over the device and used as an etch stop for a subsequently deposited, thicker layer 66 of conformally deposited conductive material. Layers 64 and 66 are required to have differing etch characteristics.
  • layer 64 can comprise sputter-deposited copper formed to a thickness of about 0.1 micrometers
  • layer 66 can comprise a multilevel structure including a first layer of sputter deposited Ti formed to a thickness of about 0.5 micrometers overlain by a second layer of sputter-deposited aluminum-copper alloy ( ⁇ lCu) formed to a thickness of about 0.5 micrometers.
  • ⁇ lCu sputter-deposited aluminum-copper alloy
  • Aperture 68 can be formed, for example, by using a BCl 3 , Cl 2 , CC1. RIE plasma to etch down to etch stop layer 64, and an HF dip to remove the exposed portion of layer 64.
  • metal lines 64A/66A, 64B/66B can be formed using a conventional lift-off process.
  • second interconnection level 70 including polyimide insulator 72 and metal-filled vias/studs 74, 76, and 78.
  • Via 76 extends through insulator 72 into contact with interconnect 66A (and hence FET gate contact 32)
  • vias 74 and 76 similarly extend into contact with interconnects 66A (and hence FET ⁇ ource region 26) and 66B (and hence FET drain region 28) , respectively.
  • each level being defined as one layer of polyimide insulator (i.e. layer 46) supporting metal-filled vias (i.e. vias 52, 54, 56) and overlying metal interconnects (i.e. interconnects 66A, 66B) .
  • FIG. 10 shows a,silicon substrate 80 supporting overlying, consecutive layers of silicon nitride 82, polyimide 84, and silicon nitride 86. (It will be appreciated that this is substantially the same insulator structure shown in FIG. 3 above.)
  • An aperture 88 is shown extending from the surface of layer 86 into contact with layer 82, the aperture having been over-etched with an O ⁇ plasma so as to form an undercut 90 underneath of masking silicon nitride layer 86.
  • a conventional photolithographic mask over layer 86 is understood, and not shown.
  • silicon nitride layer 86 is removed, simultaneously with the exposed portion of layer 82 in aperture 88, using, for example, a CF. RIE plasma etchant.
  • a barrier metal layer 92 and blanket tungsten deposition 94 are formed in the manner described above.
  • tungsten layer 94 is chemically-mechanically polished to the top of layer 84, providing filled via 94 ⁇ .
  • the desirable layer of inorganic is then reapplied, for example a layer 96 of silicon nitride, and further processing is continued in accordance with the present invention.
  • the present invention thus can accommodate over-etching of the vias with no significant changes in process or process complexity.
  • the interconnect structure provides significant advantages over the prior art structures, including:
  • the present invention has particular application in the manufacturing of semiconductor devices, including bipolar, FET, and bi-FET devices, and is particularly useful with very large scale integrated circuits (VLSI) requiring multiple levels of wiring to contact densely-packed devices.
  • VLSI very large scale integrated circuits

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

Une structure à semiconducteur comprend un substrat en matière semiconductrice comprenant une région dispositif sur une surface du substrat ou on désire former un contact conducteur. Une couche plane en polyimide est disposée sur la surface de substrat, et une couche en matière inorganique est disposée sur la couche de polyimide. L'ouverture est formée dans la couche de polyimide exposant la région dispositif, et une garniture en métal est formée sur la surface de l'ouverture dans la couche de polyimide de manière à constituer une barrière de diffusion. Une couche en métal refractaire remplit l'ouverture garnie dans la couche de polyimide de manière à former un contact conducteur dans la région du dispositif.
PCT/US1990/007401 1990-01-04 1990-12-13 Structure d'interconnexion pour dispositif semiconducteur utilisant un isolateur en polyimide Ceased WO1991010261A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US46069590A 1990-01-04 1990-01-04
US460,695 1990-01-04

Publications (1)

Publication Number Publication Date
WO1991010261A1 true WO1991010261A1 (fr) 1991-07-11

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EP (1) EP0507881A1 (fr)
JP (1) JPH05504446A (fr)
WO (1) WO1991010261A1 (fr)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2702089A1 (fr) * 1993-02-25 1994-09-02 Mitsubishi Electric Corp Transistor à effet de champ et procédé pour sa production.
EP0601951A3 (fr) * 1992-12-11 1995-01-04 Ibm Procédé pour améliorer la résistance de couche d'un dispositif comportant un transistor à effet de champ.
GB2268329B (en) * 1992-06-29 1996-09-11 Intel Corp Methods of forming an interconnect on a semiconductor substrate
EP0740334A3 (fr) * 1995-04-27 1997-05-28 Siemens Ag Procédé de gravure isotrope - hautement sélectif par rapport au tungstène - de silicium
EP0809281A3 (fr) * 1996-05-20 1997-12-10 Texas Instruments Incorporated Améliorations aux ou relatives aux dispositifs semi-conducteurs
US5817572A (en) * 1992-06-29 1998-10-06 Intel Corporation Method for forming multileves interconnections for semiconductor fabrication
WO1998044548A1 (fr) * 1997-04-03 1998-10-08 Micron Technology, Inc. Procede de formation dans le substrat d'un semi-conducteur d'une ouverture de contact jouxtant une tranchee d'isolement
US6323540B1 (en) 1998-06-10 2001-11-27 Micron Technology, Inc. Semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass, and a semiconductor structure
DE102006015096A1 (de) * 2006-03-31 2007-10-11 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Verringerung der durch Polieren hervorgerufenen Schäden in einer Kontaktstruktur durch Bilden einer Deckschicht
EP2135274A4 (fr) * 2007-04-05 2011-07-27 Freescale Semiconductor Inc Première pile diélectrique intercouche pour mémoire non volatile

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0150403A1 (fr) * 1983-12-27 1985-08-07 International Business Machines Corporation Structure métallique à niveaux multiples et procédé de fabrication de celle-ci
US4560436A (en) * 1984-07-02 1985-12-24 Motorola, Inc. Process for etching tapered polyimide vias
EP0261846A1 (fr) * 1986-09-17 1988-03-30 Fujitsu Limited Méthode pour former, sur la surface d'un dispositif semi-conducteur, une couche métallique contenant du cuivre
US4822753A (en) * 1988-05-09 1989-04-18 Motorola, Inc. Method for making a w/tin contact
EP0312986A1 (fr) * 1987-10-22 1989-04-26 Siemens Aktiengesellschaft Procédé de décapage du tungstène avec une sous-couche de nitrure de titane dans des trous de contact de circuits intégrés
EP0343269A1 (fr) * 1988-05-26 1989-11-29 Fairchild Semiconductor Corporation Système d'interconnexion à hautes performances pour un circuit intégré

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0150403A1 (fr) * 1983-12-27 1985-08-07 International Business Machines Corporation Structure métallique à niveaux multiples et procédé de fabrication de celle-ci
US4560436A (en) * 1984-07-02 1985-12-24 Motorola, Inc. Process for etching tapered polyimide vias
EP0261846A1 (fr) * 1986-09-17 1988-03-30 Fujitsu Limited Méthode pour former, sur la surface d'un dispositif semi-conducteur, une couche métallique contenant du cuivre
EP0312986A1 (fr) * 1987-10-22 1989-04-26 Siemens Aktiengesellschaft Procédé de décapage du tungstène avec une sous-couche de nitrure de titane dans des trous de contact de circuits intégrés
US4822753A (en) * 1988-05-09 1989-04-18 Motorola, Inc. Method for making a w/tin contact
EP0343269A1 (fr) * 1988-05-26 1989-11-29 Fairchild Semiconductor Corporation Système d'interconnexion à hautes performances pour un circuit intégré

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2268329B (en) * 1992-06-29 1996-09-11 Intel Corp Methods of forming an interconnect on a semiconductor substrate
US5612254A (en) * 1992-06-29 1997-03-18 Intel Corporation Methods of forming an interconnect on a semiconductor substrate
US5817572A (en) * 1992-06-29 1998-10-06 Intel Corporation Method for forming multileves interconnections for semiconductor fabrication
EP0601951A3 (fr) * 1992-12-11 1995-01-04 Ibm Procédé pour améliorer la résistance de couche d'un dispositif comportant un transistor à effet de champ.
FR2702089A1 (fr) * 1993-02-25 1994-09-02 Mitsubishi Electric Corp Transistor à effet de champ et procédé pour sa production.
EP0740334A3 (fr) * 1995-04-27 1997-05-28 Siemens Ag Procédé de gravure isotrope - hautement sélectif par rapport au tungstène - de silicium
EP0809281A3 (fr) * 1996-05-20 1997-12-10 Texas Instruments Incorporated Améliorations aux ou relatives aux dispositifs semi-conducteurs
US5960304A (en) * 1996-05-20 1999-09-28 Texas Instruments Incorporated Method for forming a contact to a substrate
US5866465A (en) * 1997-04-03 1999-02-02 Micron Technology, Inc. Semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass
WO1998044548A1 (fr) * 1997-04-03 1998-10-08 Micron Technology, Inc. Procede de formation dans le substrat d'un semi-conducteur d'une ouverture de contact jouxtant une tranchee d'isolement
US6084289A (en) * 1997-04-03 2000-07-04 Micron Technology, Inc. Semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass, and a semiconductor structure
US6184127B1 (en) 1997-04-03 2001-02-06 Micron Technology, Inc. Semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass, and a semiconductor structure
US6323540B1 (en) 1998-06-10 2001-11-27 Micron Technology, Inc. Semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass, and a semiconductor structure
DE102006015096A1 (de) * 2006-03-31 2007-10-11 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Verringerung der durch Polieren hervorgerufenen Schäden in einer Kontaktstruktur durch Bilden einer Deckschicht
US7528059B2 (en) 2006-03-31 2009-05-05 Advanced Micro Devices, Inc. Method for reducing polish-induced damage in a contact structure by forming a capping layer
DE102006015096B4 (de) * 2006-03-31 2011-08-18 Globalfoundries Inc. Verfahren zur Verringerung der durch Polieren hervorgerufenen Schäden in einer Kontaktstruktur durch Bilden einer Deckschicht
EP2135274A4 (fr) * 2007-04-05 2011-07-27 Freescale Semiconductor Inc Première pile diélectrique intercouche pour mémoire non volatile
US8435898B2 (en) 2007-04-05 2013-05-07 Freescale Semiconductor, Inc. First inter-layer dielectric stack for non-volatile memory

Also Published As

Publication number Publication date
JPH05504446A (ja) 1993-07-08
EP0507881A1 (fr) 1992-10-14

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