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WO1988006764A3 - Systeme de processeurs vectoriels paralleles en grand nombre - Google Patents

Systeme de processeurs vectoriels paralleles en grand nombre Download PDF

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Publication number
WO1988006764A3
WO1988006764A3 PCT/US1988/000456 US8800456W WO8806764A3 WO 1988006764 A3 WO1988006764 A3 WO 1988006764A3 US 8800456 W US8800456 W US 8800456W WO 8806764 A3 WO8806764 A3 WO 8806764A3
Authority
WO
WIPO (PCT)
Prior art keywords
processing elements
path
processing
stage
processor
Prior art date
Application number
PCT/US1988/000456
Other languages
English (en)
Other versions
WO1988006764A2 (fr
Inventor
Robert S Grondalski
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Priority to JP63504209A priority Critical patent/JPH02503243A/ja
Publication of WO1988006764A2 publication Critical patent/WO1988006764A2/fr
Publication of WO1988006764A3 publication Critical patent/WO1988006764A3/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17381—Two dimensional, e.g. mesh, torus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)

Abstract

Un système de processeurs vectoriels comprenant une pluralité d'éléments de traitement comprenant chacun un processeur (22A) et un module (23A) de mémoire associé, le système comprend en outre un réseau routeur (30) sur lequel chaque élément de traitement peut transférer des messages à d'autres éléments de traitement sélectifs, un mécanisme par lequel un processeur peut transmettre des données à un des quatre processeurs voisins les plus proches. De plus, les éléments de traitement sont divisés en groupes, chacun avec quatre éléments de traitement, dans lesquels un des éléments de traitement peut accéder à des données dans les modules de mémoire des autres éléments de traitement. Le réseau d'acheminement transfère des messages dans une pluralité de phases de transfert, chaque étape connectant la phase suivante au moyen d'itinéraires d'accès de communications qui sont divisés en groupes, chaque groupe, à son tour, étant associé à des signaux d'adresses sélectionnés. Un circuit de test de continuité d'itinéraire d'accès de communications associé à chaque itinéraire détecte toute discontinuité dans l'itinéraire d'accès de communications et invalide l'itinéraire. Ainsi, la phase de traitement peut essayer de transférer un message sur un autre itinéraire d'accès associé aux mêmes adresses.
PCT/US1988/000456 1987-02-24 1988-02-16 Systeme de processeurs vectoriels paralleles en grand nombre WO1988006764A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63504209A JPH02503243A (ja) 1988-02-16 1988-02-16 大規模並列アレイ処理装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US018,937 1987-02-24
US1893787A 1987-02-25 1987-02-25

Publications (2)

Publication Number Publication Date
WO1988006764A2 WO1988006764A2 (fr) 1988-09-07
WO1988006764A3 true WO1988006764A3 (fr) 1988-12-15

Family

ID=21790510

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1988/000456 WO1988006764A2 (fr) 1987-02-24 1988-02-16 Systeme de processeurs vectoriels paralleles en grand nombre

Country Status (3)

Country Link
EP (1) EP0303696A1 (fr)
CA (1) CA1312960C (fr)
WO (1) WO1988006764A2 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05506526A (ja) * 1990-01-05 1993-09-22 マスパー・コンピューター・コーポレイション クワッドクロスバー及びハイパーバーパーソナリティを備えるラウタチップ
JPH05506113A (ja) * 1990-01-05 1993-09-02 マスパー・コンピューター・コーポレイション 並列プロセッサメモリシステム
US5313590A (en) * 1990-01-05 1994-05-17 Maspar Computer Corporation System having fixedly priorized and grouped by positions I/O lines for interconnecting router elements in plurality of stages within parrallel computer
US5280474A (en) * 1990-01-05 1994-01-18 Maspar Computer Corporation Scalable processor to processor and processor-to-I/O interconnection network and method for parallel processing arrays
US5243699A (en) * 1991-12-06 1993-09-07 Maspar Computer Corporation Input/output system for parallel processing arrays
US6266342B1 (en) * 1998-04-08 2001-07-24 Nortel Networks Limited Adaption resource module and operating method therefor

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4051551A (en) * 1976-05-03 1977-09-27 Burroughs Corporation Multidimensional parallel access computer memory system
WO1983002180A1 (fr) * 1981-12-14 1983-06-23 Western Electric Co Unite de processeur d'interface
EP0171856A1 (fr) * 1984-08-14 1986-02-19 Telecommunications Radioelectriques Et Telephoniques T.R.T. Processeur pour le traitement de signal et structure de multitraitement hiérarchisée comportant au moins un tel processeur
EP0261034A2 (fr) * 1986-09-18 1988-03-23 Digital Equipment Corporation Système massif de réseau de processeurs parallèles

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4051551A (en) * 1976-05-03 1977-09-27 Burroughs Corporation Multidimensional parallel access computer memory system
WO1983002180A1 (fr) * 1981-12-14 1983-06-23 Western Electric Co Unite de processeur d'interface
EP0171856A1 (fr) * 1984-08-14 1986-02-19 Telecommunications Radioelectriques Et Telephoniques T.R.T. Processeur pour le traitement de signal et structure de multitraitement hiérarchisée comportant au moins un tel processeur
EP0261034A2 (fr) * 1986-09-18 1988-03-23 Digital Equipment Corporation Système massif de réseau de processeurs parallèles

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Patent Abstracts of Japan, volume 7, no. 121 (P-199)(1266), 25 May 1983; & JP-A-5839360 (TOKYO SHIBAURA DENKI K.K.) 8 March 1983 *
Wescon Technical Papers, 30 October - 2 November 1984, (Anaheim, California, US), B. Beims: "Multiprocessing capabilities of the MC68020 32-bit Microprocessor", pages 1-16 *

Also Published As

Publication number Publication date
CA1312960C (fr) 1993-01-19
WO1988006764A2 (fr) 1988-09-07
EP0303696A1 (fr) 1989-02-22

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