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WO1982003954A1 - Circuit d'alimentation de courant - Google Patents

Circuit d'alimentation de courant Download PDF

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Publication number
WO1982003954A1
WO1982003954A1 PCT/US1981/000578 US8100578W WO8203954A1 WO 1982003954 A1 WO1982003954 A1 WO 1982003954A1 US 8100578 W US8100578 W US 8100578W WO 8203954 A1 WO8203954 A1 WO 8203954A1
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WO
WIPO (PCT)
Prior art keywords
current
phase
load
supply circuit
power supply
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Ceased
Application number
PCT/US1981/000578
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English (en)
Inventor
John P Hoffman
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Individual
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Individual
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Priority to PCT/US1981/000578 priority Critical patent/WO1982003954A1/fr
Publication of WO1982003954A1 publication Critical patent/WO1982003954A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/02—Conversion of AC power input into DC power output without possibility of reversal
    • H02M7/04—Conversion of AC power input into DC power output without possibility of reversal by static converters
    • H02M7/12—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/145—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means
    • H02M7/155—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only
    • H02M7/162—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only in a bridge configuration
    • H02M7/1623—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only in a bridge configuration with control circuit

Definitions

  • This invention relates generally to a power supply circuit and, more particularly, to a power supply circuit for supplying power to an inductive load in response to a 3-phase AC source.
  • the power supply can be controlled to adjust or change the current through the load.
  • the power supply can be, for example, a DC supply generated from a 3-phase AC source and the load can be, for example, an inductive load. Current will build up or decay in response to the supply being coupled to or decoupled from the load.
  • the inductive load can be an eddy current dynamometer which is used to control the speed of an engine.
  • the power supply can be a DC supply of one magnitude or polarity of voltage which is coupled to the inductive load to build up current through the load in response to a command for reduced engine speed and/or a DC supply of a different magnitude or polarity of voltage to the load to decay current through the load in response to a command for increased engine speed.
  • the commanded engine speed may have to be reached so rapidly, that the response time for achieving current build-up or decay cannot occur sufficiently quickly for either command due to the above-mentioned constraints.
  • the present invention is directed to overcoming one or more of the problems as set forth above.
  • a power supply circuit having a load, means for conducting current of a 3-phase AC source, and triggerable means for coupling the current of the 3-phase AC source between said conducting means and said load, the improvement comprising means for generating a reference phase signal in response to one reference phase voltage of the 3-phase AC source, and means for triggering said triggerable means at preselected phase angles of the 3-phase AC source relative to the reference phase signal to control the current through the load.
  • the power supply circuit of the present invention couples the current of the 3-phase AC source between the coupling means and the load, at various phase angles relative to the reference phase voltage, to control the current through the load. A maximum rate of current build-up or decay through the load is obtained at preselected phase angles.
  • Figs. 1A - 7A illustrate voltage wave ⁇ forms of a 3-phase AC source used to explain the theory of operation of the present invention for control of current build-up through a load.
  • Figs. IB - 7B show current flow through a circuit portion of a power supply circuit of the present invention at times corresponding to phase angles shown, respectively, in Figs. lA - 7A;
  • Figs. 8A - 13A and Fig. 13A' illustrate voltage waveforms of the 3-phase AC source used to explain the theory of operation of the present invention for control of current decay through a load;
  • Figs. 8B - 12B show current flow through a circuit portion of the power supply circuit of the present invention at times corresponding to phase angles shown, respectively, in Figs. 8A - 13A;
  • Fig. 14A is a composite illustration for explaining current build-up and current decay through a load?
  • Fig. 15 is a schematic illustration of an embodiment of the present invention.
  • Figs. 16A - 16C show the relationship between phase voltages of the 3- ⁇ hase AC source, phase angles and counts of a counter
  • OMPI Fig. 16D is a tabulation of counter states corresponding to a maximum rate of current build-up and decay through a load.
  • FIG. 1A shows voltage waveforms of a
  • Fig. IB illustrates a circuit portion 10 of a power supply circuit to be fully described in connection with Fig. 15.
  • Circuit portion 10 has three current carrying lines or conductors A, B, C, and a load 12, such as an inductive load, through which current can build-up or decay.
  • Three silicon controlled rectifiers 1, 2, 3 have their cathodes connected in common to side 12a of load 12 and their anodes connected, respectively, to lines A, B, C.
  • Three silicon controlled rectifiers 4, 5, 6 have their anodes connected in common to side 12b of load 12 and their cathodes connected, respectively, to lines B, C, A.
  • Voltage AB is followed in time or phase at 120° by voltage BC, which is followed in time or phase at an additional 120° by voltage CA. At the time or phase angles shown by the arrow in Fig. 1A, voltage AB is positive, increasing, and approaching a peak value or maximum. If, at this time, trigger or gate pulses are supplied simultaneously to the control gates of SCR 1 and SCR 4, then current will begin to flow on line A, through SCR 1, load 12 and SCR 4 onto line B, as shown in Fig. IB.
  • a voltage AC which is the inverse of voltage CA, becomes more positive than voltage AB and is approaching a maximum. If, at this time, gate pulses are supplied to the control gates of SCR 1 and SCR 5, then, as shown in Fig.
  • Figs. 1A - 7A and Figs. IB - 7B demonstrates that current through the load 12 is increased by gating "on" the SCRs 1-6 at the proper time and in the proper order.
  • the SCRs 1-6 are gated "on” at these particu ⁇ lar times, current build-up through the load 12 will occur at a maximum rate, given the magnitude of the 3-phase AC source voltage and the inductance of the load 12.
  • the times or phase angles at which the SCRs 1-6 are gated "on” are relative to the start of one voltage of the 3-phase AC source, e.g., voltage AB.
  • Fig. 10A voltage CB is less negative than voltage CA but is about to become more negative.
  • SCR 4 is gated “on” and the current from the load 12 will flow through SCR 3 and SCR 4, as shown in Fig. 10B. If voltage CB were not less negative than voltage CA at the time SCR 4 is triggered “on", the current would not transfer from SCR 6 to SCR 4. SCR 6 soon turns off since it now becomes deprived of the holding current needed to keep it on.
  • phase AC is about to become most negative and current shifts from phase AB to phase AC.
  • the above-described operational sequence for current decay repeats until the load 12 can no longer forward bias the SCRs 1-6 or until it is required again to build up current in the load 12.
  • the energy in the load 12 is transferred efficiently to the lines A, B, C by forcing current into whichever of the three phase voltages is the most negative.
  • the times or phase angles at which the SCRs 1-6 are gated "on" are relative to the start of one voltage of the 3-phase AC source, e.g., voltage AB.
  • phase CA is positive and conducting when the current-down mode becomes active. It is equally likely that any of the phases may be positive and conducting when the current-down mode becomes active. In any case, the result will differ from Fig. 13A only in that a phase other than phase CA may be conducting as its terminal voltage changes from positive to negative.
  • Fig. 13A' An example of a transition is shown in Fig. 13A'.
  • a less-abrupt transition method is possible including one similar to the up- to-down transition in which the conducting phase is allowed to naturally commutate from a negative to positive polarity.
  • the method chosen here is simplest to implement and is very fast. While other transi ⁇ tions would be more expensive, and slower, they would be desirable if necessary to stay within the di/dt specifications of the SCRs used.
  • Fig. 14A is a composite drawing which shows the actual voltage applied during current build-up in the load 12, and the voltage across the load 12 during current decay.
  • Fig. 15 illustrates one embodiment of a power supply circuit 20 which includes the load 12 and means 22 for conducting current of a 60 cycle, 3-phase AC source, which includes lines A, B, C.
  • a triggerable means 24 couples the current of the 3- phase AC source between the conducting means 22 and the load 12.
  • the means 24 includes SCRs 1-6 which are connected to lines A, B, C as previously de ⁇ scribed.
  • the remainder of power supply circuit 20 constitutes a control means 26 which controls the triggering or gating "on" of SCRs 1-6 to perform the operational sequences described above for build- up or decay of current through load 12.
  • Control means 26 includes a means 27 for generating a reference signal in response to one reference phase voltage of the 3-phase AC source, e.g., voltage AB.
  • a transformer 28 of means 27 has its primary winding connected to lines A, B and steps down the sinusoidal reference phase voltage AB to, for example, 120 volts.
  • An adjustable phase sensor 30 of means 27 receives the stepped-down sinusoidal reference voltage AB from transformer 28 and produces a +15 VAC, 60Hz. square wave version or reference signal of reference phase voltage AB on an output line 32 that is approximately 180° out-of- phase from the voltage AB.
  • Phase sensor 30 is ad ⁇ justable with a potentiometer (not shown) to adjust the phase of the reference signal on line 32 to the needed phase relationship.
  • a pair of Schmitt triggers 33 additionally square and produce the reference sig ⁇ nal on an output line 34.
  • Control means 26 also includes a means 35 for triggering or gating "on" the triggerable means 24 at predetermined phase angles of the 3-phase AC source relative to the reference phase voltage AB and in response to the reference signal on line 34 to control the conduction of current through SCRs 1-6.
  • a dividing means 36 of triggering means 35 divides a cycle of the reference phase voltage AB into a plurality of phase angles, e.g., in 6° increments, and generates signals representing the plurality of phase angles.
  • a phase lock loop 37 of dividing means 36 locks on the incoming 60Hz. reference signal on line 34 and multiples this signal by 60 to produce a clock signal of 3600Hz. on an output line 38.
  • a monostable multivibrator 40 is triggered by the low to high transition or beginning of each 60Hz. reference signal on line 34 to produce a reset pulse on an output line 42.
  • a counter means 44 of dividing means 36 counts the pulses of the 3600Hz. clock signal being received on line 38 and includes a units counter 46 having counter states or outputs 0-9 and a tens counter 48 having counter states or outputs 0-5.
  • Each one count of the counter means 44 is equal to 6° of phase as measured from the positive swing of the reference phase voltage AB.
  • a counter state of 8 equals 48°
  • a counter state of 30 equals 180° from this positive swing..
  • Each such counter output thus is a signal representing one of these pluralities of phase angles of reference phase voltage AB.
  • Counter 46 and counter 48 are reset to 0 by the output pulse of multivibrator 40 on the line 42. Consequently, counter means 44 will have counted to 60 when counter 46 and counter 48 are reset to 0, which count equals one full cycle or 360° of the reference phase voltage AB.
  • a decoding means 50 of triggering means 35 decodes the signals representing the plurality of phase angles, i.e., the outputs of counter means 44, and generates SCR triggering or gating pulses to gate "on" selected SCRs 1-6 at these times or phase angles.
  • Decoding means 50 has a decoder logic network 52 which includes six sets of gates 54, 56, 58, 60, 62, 64. Each set 54-64 has three NAND gates whose outputs drive an Or gate. Thus, for example, set 54 has three NAND gates 54-1, 54-2 and 54-3 whose outputs drive an Or gate 54-4, set 56 has three NAND gates 56-1, 56-2 and 56-3 whose outputs drive an Or gate 56-4, etc.
  • Each set 54-64 of three NAND gates has inputs connected to the various outputs of counter 46 and counter 48, as shown in Fig. 15.
  • gate 54-1 has one input connected to counter output 10
  • gate 54-2 has one input connected to counter output 20
  • gate 54-3 has one input con- nected to counter output 30.
  • gate 62-1 has one input connected to counter output 20
  • gate 62-2 has one input connected to counter output 30, and gate 62-3 has one input connected to counter output 40.
  • Decoding means 50 also has means 66 for preselecting any of the plurality of outputs of counter means- 44 to decode, and hence any of the phase angles of reference phase voltage AB.
  • Pre ⁇ selecting means 66 includes jumper selectable line P and jumper selectable line Q.
  • Line P is select ⁇ ively connectable to units counter 46 and activates one of the NAND gates in each of the sets 54-64 for the purpose of controlling the rate of current decay.
  • line P is connectable to any one of counter outputs 1-9 of counter 46 and is connected as an input to gate 54-3, gate 56-3, gate 58-3, etc.
  • Line Q is selectively connectable to units counter 46 and activates the remaining two NAND gates of each set
  • line Q is selectively connectable to any one of counter outputs 1-9 of counter 46 and is connected as an input to gate 54-1 and gate 54-2, an input to gate 56-1 and 56-2, an input to gate 58-1 and gate 58-2, etc.
  • the decoding means 50 also has a means 67 for selectively activating the decoder logic network 52 to decode the outputs of counter means 44 for the purpose of producing current build-up or current decay.
  • Means 67 has an input control line 68 that receives a high signal or logic 1 for current build ⁇ up and a low signal or logic 0 for current decay.
  • a NAND gate 70 has one input connected to line 68, another input connected to the count 0 of counter 46 over a line 72, and yet another input connected to +V.
  • a NAND gate 74 has one input connected to line 72 and another input connected to +V. Yet another input to NAND gate 74 is the output of a Schmitt trigger 76 over a line 78, whose input is the high or low signal on line 68.
  • the signal on line 68 sometimes will be logic 0; therefore the output of gate 70 on a line 80 will be logic 1.
  • the output of gate 70 on line 80 will be logic 0 as soon as counter 46 is reset to 0 to produce a logic 1 on line 72.
  • the output of gate 74 on a line 82 goes to logic 0 when the signal on line 68 is logic 0 and counter 46 is reset to 0.
  • the output on line 80 and the output on line 82 are both high until counter 46 is reset to 0, at which time these outputs are opposite from each other, depending on the high/low level of the signal on line 68.
  • An R-S flip-flop 84 of means 67 has a reset input R coupled to line 82 and a set input S " coupled to line 80.
  • the output Q of flip-flop 84 is connected to a "down” line 86 to activate decoder logic network 52 for producing current decay, whereas the output Q of flip-flop 84 is connected to an "up” line 88 to activate network 52 for producing current build-up.
  • "down" line 86 is connected to gate 54-3, gate 56-3, gate 58-3, etc.
  • "up” line 88 is connected to gate 54-1 and gate 54-2, gate 56-1 and gate 56-2, etc.
  • the means 67 for selectively activating decoder logic network 52 for current build-up or current decay (1) latches the logic 1 or logic 0 signal on line 68 via flip-flop 84 until the logic 0 or logic 1 occurs, respectively, (2) ensures that the output Q on line 86 and output Q on line 88 have at least
  • J ⁇ RE a minimum pulse width equal to the time needed to reset counter 46 to 0, and (3) ensures that all transitions between conditions of current build-up and current decay begin at a count whose least sig- nificant digit is zero which is the start of reference phase voltage AB or at 60° intervals -thereafter.
  • decoding means 50 In the overall operation of decoding means 50, assume that a logic 1 appears on line 68 and that counter 46 is reset to 0. Therefore, flip- flop 84 will be set to produce a high on line 88 and a low on line 86. Consequently, two of each of the NAND gates in each set 54-64 will have an active high from the signal on line 88. For example, gate 54-1 and gate 54-2 will have an active high from line 88 and gate 54-3 " will be deactivated by the low on line 86, gate 56-1 and gate 56-2 will have an active high from line 88 and gate 56-3 will be deactivated by the low on. line 86, etc.
  • gate 56-1 has a high at all three of its inputs to produce a low pulse which drives gate 56-4 to produce a high pulse on an output line 56-5.
  • gate 56-2 has a high at all three of its inputs to produce a low pulse which drives gate 56-4 again to produce a high pulse on line 56-5 atthis time.
  • a similar sequence occurs as the counter means 44 is clocked to count from 0 through to 60 before it is reset to 0.
  • Each gate 58-4, 60-4, 62-4 and 64-4 also will be driven twice during this counting sequence at the times or count ⁇ er states indicated by the line connections shown for decoding means 50.
  • gate 60-3 will have a high at all three inputs to produce a low pulse which drives gate 60-4 to produce a high pulse on line 60-5 at this time.
  • gate 56-3 will have a high at all three inputs to produce a low pulse which drives gate 56-4 to produce a high pulse on line 56-5 at this time.
  • a similar action occurs with gate 54-3 and gate 54-4, gate 58-3 and gate
  • An opto-isolator 54-6 responds to the high pulses on line 54-5 to gate "on" a field effect transistor or FET 54-7 having a resistor R.
  • Five additional opto-isolators 56-6 to 64-6, FETs 56-7 to 64-7 and resistors R are coupled to respective lines 56-5 through 64-5, as shown in Fig. 15.
  • opto-isolator 54-6 gates on FET 54-7. Consequently, SCR gate current will flow from +V into the gate of SCR 1, out the cathode of SCR 1, -through resistor R and FET 54-7 to -V.
  • SCR 1 will be triggered or gated “on” to conduct current of the 3-phase AC source, as will be further described.
  • SCRs 2-6 are triggered “on” at the time a high pulse appears on lines 56-5 to 64-5, respectively.
  • Fig. 16A again shows the waveform of the
  • Fig. 16B shows the phase angles of the reference phase voltage AB.
  • Fig. 16C illustrates the count in counter means 44 at the various phase angles shown in Fig. 16B. For example, count 10 corresponds to 60°, count 20 to 120°, etc.
  • Fig. 16D is a chart showing the count of the counter means 44 at which the SCRs 1-6 should be triggered "on" to maximize the rate of build-up of current through the load 12 or the rate of decay of current through the load 12.
  • the load 12 can be an inductive load such as an eddy current dynamometer which is used to control the speed of an engine by loading.
  • power supply circuit 20 can rapidly build-up current through load 12 to load the engine.
  • power supply circuit 20 can rapidly decay current through load 12 to unload the engine.
  • the NAND gates of the six sets 54-64 are connected to the tens counter 48, as shown in Fig. 15.
  • the line Q is selectively coupled to the count 1 of counter 46 while line P is selectively coupled to the count 9 of counter 46.
  • gate 54-4 and gate 60-4 will . be driven to produce a trigger or gate pulse on line 54-5 and line 60-5, which results in SCR 1 and SCR 4 being triggered "on" at a phase angle of about 66° relative to the reference phase voltage AB.
  • a cur ⁇ rent path is now completed from line A, through SCR
  • This time interval corresponds to the example of a current-up to current-down transition shown in Fig. 13A.
  • the example here, in which gating pulses cause no current- path changes, is unique to the up-to-down mode changes. That is, it does not happen in steady-state conditions or during the down-to-up mode conditions, each of which is discussed elsewhere.
  • the first current-path-changing trigger occurs at count 29 and is applied to SCR 4 with results indicated in Fig. 10A and Fig. 10B.
  • gate 62-3 is enabled to drive gate 62-4 to produce a gate pulse on line 62-5.
  • SCR 5 is triggered “on” at this time corresponding to a relative phase angle of about 294°, as shown in Fig. 12A and Fig. 16A, to produce a current path from line A, through SCR 1, load 12, SCR 5 and back to line C, as indicated in Fig. 12B.
  • a resistor 90 is connected across load 12 because of the combination of SCR characteristics and large inductance of load 12. Due to the magnitude of the voltage of the 3-phase AC source, current may not build up to the SCR holding current during one SCR gate pulse; therefore, the SCRs may not latch under this condition. By using resistor 90, the current through the SCRs is the sum of the current through load 12 and resistor 90, which produces sufficient SCR holding current.
  • the constraints of magnitude of the 3-phase AC source voltage and inductance of the load 12, which limit the rate of change of current through load 12, are alleviated by the power supply circuit 20.
  • the phase angles relative to the reference phase voltage AB at which the SCRs 1-6 are triggered "on” a maximum or any desired rate of current build-up and/or decay -through load 12 can be achieved.
  • the power supply circuit 20 is of the full- on, full-off form. It applies the peak value of the 3-phase AC line voltage to its load 12, one polarity of the voltage for the full-on mode and the opposite polarity for the full-off mode. This is shown graphically in Fig. 14A. In the full-off mode the peak line voltage is applied to the load 12 until the load current decreases to zero. Then the applied vol ⁇ tage goes to zero.
  • the power supply circuit 20 is able to cause quick current build-up or quick current decay by applying a voltage high enough to get a desired rate- of-change of current through the inductive load 12. For a given load time-constant, the absolute maximum rates of current rise and decay are determined by the magnitude of the 3-phase source voltage. In a number of instances, this applied voltage may be too high to keep applied indefinitely. Therefore, power supply circuit 20 might be used with appropriate other cir ⁇ cuitry (not shown) to prevent current or power levels from becoming too large. Very high reliability is obtained with this power supply circuit 20 because the only components which handle load current and/or voltage are SCRs. In the current-up mode, in which line 68 is high, the circuit approximates a simple full-wave 3-phase

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

Circuit d'alimentation de courant (20) possedant une charge inductive (12), trois lignes de puissance (A, B, C) pour amener le courant d'une source de courant alternatif triphase, un reseau de SCR (24) compose de six SCR (1-6) servant a coupler le courant de la source entre les lignes de puissance (A, B, C) et la charge (12), un detecteur de phase (30) produisant un signal de reference en reponse a une tension de phase de reference (AB) de la source, et un circuit de declenchement (35) servant a declencher les SCR (1-6) a des angles de phase predetermines par rapport a la tension (AB). Le circuit d'alimentation de courant (20) permet d'eliminer les contraintes telles que l'inductance de charge qui limite la vitesse d'accroissement ou de diminution du courant au travers de la charge (12) en declenchant les SCR (1-6) aux angles de phase predetermines afin de porter au maximum l'accroissement ou la diminution du courant.
PCT/US1981/000578 1981-04-30 1981-04-30 Circuit d'alimentation de courant Ceased WO1982003954A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US1981/000578 WO1982003954A1 (fr) 1981-04-30 1981-04-30 Circuit d'alimentation de courant

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
PCT/US1981/000578 WO1982003954A1 (fr) 1981-04-30 1981-04-30 Circuit d'alimentation de courant
WOUS81/00578810430 1981-04-30

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WO1982003954A1 true WO1982003954A1 (fr) 1982-11-11

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4016468A (en) * 1975-03-18 1977-04-05 General Electric Company Controlled rectifier motor drive system including d.c. fault detection and commutation means
US4017744A (en) * 1975-12-22 1977-04-12 Westinghouse Electric Corporation Digital firing pulse generator for thyristor power converters
US4063146A (en) * 1975-05-22 1977-12-13 Reliance Electric Company Digital firing control for a converter

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4016468A (en) * 1975-03-18 1977-04-05 General Electric Company Controlled rectifier motor drive system including d.c. fault detection and commutation means
US4063146A (en) * 1975-05-22 1977-12-13 Reliance Electric Company Digital firing control for a converter
US4017744A (en) * 1975-12-22 1977-04-12 Westinghouse Electric Corporation Digital firing pulse generator for thyristor power converters

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