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US8161276B2 - Demodulator device and method of operating the same - Google Patents

Demodulator device and method of operating the same Download PDF

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Publication number
US8161276B2
US8161276B2 US12/373,894 US37389407A US8161276B2 US 8161276 B2 US8161276 B2 US 8161276B2 US 37389407 A US37389407 A US 37389407A US 8161276 B2 US8161276 B2 US 8161276B2
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Prior art keywords
demodulator device
demodulator
operating system
abort
command
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US20090327676A1 (en
Inventor
Olivier ELSHOCHT
John Hornsby
Joel Grad
Panagiotis Arkoudopoulos
Philip Marivoet
Tom Appermont
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Sony Europe BV United Kingdom Branch
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Sony Service Center Europe NV
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Priority claimed from GB0614547A external-priority patent/GB0614547D0/en
Priority claimed from GB0614548A external-priority patent/GB0614548D0/en
Application filed by Sony Service Center Europe NV filed Critical Sony Service Center Europe NV
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G06F9/4887—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues involving deadlines, e.g. rate based, periodic
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3228—Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

Definitions

  • the present invention relates to a demodulator device and a method of operating the same.
  • a demodulator device In digital television receivers, such as those conforming to the digital video broadcast-hand-held (DVB-H) standards, it is known to provide a demodulator device, perhaps in the form of an interchangeable module.
  • a reset signal is sent by a host application in the receiver to the demodulator device and the demodulator device is configured to load various information, such as an operating system and parameters, from the host receiver.
  • the demodulator device then initializes the operating system and any appropriate hardware devices within the demodulator device.
  • the present application is based on a recognition that, on occasions during use of the receiver, it is desirable to reinitialize the various hardware devices. For instance, after loss of a received signal, the host application of the receiver could decide to move to a different carrier frequency.
  • a method of operating a demodulator device having a loaded operating system and a communication protocol enabling a host application to control the demodulator device including:
  • the present application also provides a demodulator device configured to run a loaded operating system and operate a communication protocol enabling a host application to control the demodulator device, wherein the demodulator device is configured to respond to receipt of an abort command of the communication protocol by carrying out an abort process which stops current operations and reinitializes the loaded operating system.
  • the demodulator device is configured to respond to the abort command to re-boot or reinitialize the loaded operating system, and reinitialize individual parts of the demodulator device, such as its various hardware devices.
  • the demodulator device includes a plurality of hardware devices and is configured to reinitialize the plurality of hardware devices upon receipt of the abort command and as part of the abort process.
  • the hardware devices can include at least one of a timer, a UART, an SPI, an SDIO, a tuner, a demodulator, a filter and an MPE-FEC.
  • the timer provides an indication of the system time and allows configuring alarms to go off after a pre-determined amount of time.
  • the UART Universal Asynchronous Receiver/Transmitter
  • the SPI Serial Peripheral Interface
  • the SPI is a standard synchronous communication data link, used to inter-connect devices such as integrated circuits, used in the DVB-H receiver to communication with and be controlled by a host application processor (i.e. receiver commands and send responses including command results).
  • the SDIO Secure Digital Input/Output
  • the tuner is an analog integrated circuit used to extract and isolate a specific radio frequency channel in the frequency spectrum and convert it down to base band (i.e. bring the carrier frequency to 0 Hz).
  • the demodulator is a digital integrated circuit used to demodulate a DVB-H signal.
  • the filter is a digital integrated circuit used to extract specific packets of data, identified among other things by their packet ID (PID) and table id, as a subset of and from an MPEG-2 transport stream.
  • the MPE-FEC Multi-Protocol Encapsulation-Forward Error Correction
  • MPE-FEC Multi-Protocol Encapsulation-Forward Error Correction
  • IP packets in the case of DVB-H
  • FEC is a method that includes encapsulating extra codes in the MPEG-2 transport stream, at the transmitter side, and using these codes at the receiver side to detect and correct transmission errors in the MPE data.
  • the demodulator device is to be controlled by an external processor, such as a host application of a receiver, it preferably includes an interface, such as a serial peripheral interface (SPI) to enable this communication.
  • the demodulator device is preferably configured not to stop operation of the interface upon receipt of the abort command. This enables continued communication with the external processor.
  • the demodulator device is configured to send an abort response upon completion of the abort process by the demodulator device.
  • the demodulator device is configured to respond to receipt of a reset command of the communication protocol to conduct a reset process which includes downloading an operating system from an external memory and initializing the downloaded operating system.
  • the reset command could be used to achieve reinitialization of various parts of the demodulator device, such as its hardware devices.
  • the full reset process involves downloading the operating system from an external memory, downloading configuration parameters and re-mapping parts of the memory of the demodulator device. This is unnecessary and time consuming.
  • Provision of the abort command according to the present invention allows reinitialization of the already loaded operating system without having to download that operating system.
  • the demodulator device of the present invention can be provided as an interchangeable module, for instance as an integrated circuit. It is preferably configured to demodulate digital television signals, for instance conforming to the DVB-H standards, and a digital television receiver may be provided including the demodulator device.
  • a computer program or firmware may be provided for operating the communication protocol and abort command as described.
  • FIG. 1 illustrates an example of a device in which the present invention may be embodied
  • FIG. 2 illustrates schematically a system embodying the present invention
  • FIG. 3 provides an alternative schematic illustration of an embodiment of the present application
  • FIG. 4 illustrates a reset process for the arrangement of FIG. 3 ;
  • FIG. 5 illustrates an abort process for the arrangement of FIG. 3 ;
  • FIG. 6 illustrates schematically an example of tasks, services and device drivers operated in the arrangement of FIG. 3 ;
  • FIG. 7 illustrates schematically a device driver
  • FIG. 8 illustrates schematically power control of hardware devices
  • FIG. 9 illustrates various power up and down states
  • FIG. 10 illustrates the arrangement of FIG. 6 with additional time slicer tasks
  • FIG. 11 illustrates relative priority of various tasks.
  • the present invention is intended for use in a mobile television receiver ( 2 ), for instance a mobile telephone device ( 2 ) as illustrated in FIG. 1 .
  • a mobile television receiver may function according to the DVB-H (Digital Video Broadcast-Handheld) standards used in Europe.
  • DVB-H Digital Video Broadcast-Handheld
  • the illustrated receiver ( 2 ) includes a display ( 4 ) for displaying received television program images and a user interface ( 6 ), for instance including a plurality of keys ( 8 ), allowing a user to operate or control the receiver ( 2 ). Audio reproduction of the audio part of a received television program may be provided to the user for instance by means of a pair of headphones ( 10 ).
  • FIG. 2 illustrates schematically parts of the receiver ( 2 ) used in receiving digital television signals.
  • the receiver ( 2 ) includes its own application processor or host ( 12 ) which can be used to operate television functions of the receiver ( 2 ) as well as other functions, such as telephone operations where the receiver ( 2 ) is operable also as a telephone.
  • the application processor ( 12 ) can include a variety of middleware ( 14 ) and associated memories for storing such middleware.
  • the receiver ( 2 ) includes a module ( 16 ) specifically configured to handle the television functions.
  • the module ( 16 ) could be made and sold separately and provided for use in a number of different receivers.
  • the module ( 16 ) is configured to output video data for display on the display ( 4 ) and audio data for reproduction by the headphones ( 10 ).
  • Control of the module ( 16 ), for instance changing television channels, can be achieved by means of the application processor ( 12 ) under the control of the user interface ( 6 ).
  • An aerial ( 18 ) is provided for receiving a number of television signals modulated on a variety of radio frequency carriers.
  • a tuner ( 20 ) is configured to tune to a particular carrier frequency and provide the received modulated signal to a demodulator ( 22 ).
  • the demodulator ( 22 ) includes a number of hardware units ( 24 ) (in addition to the tuner ( 20 )) such as demodulator and filter blocks. These are operated under the control of firmware ( 26 ) previously downloaded from the application processor ( 12 ) so as to provide full operation of the module ( 16 ) and output of audio/video signals as required.
  • FIG. 3 provides an alternative schematic illustration of the structure of the module ( 16 ).
  • a bus ( 28 ) allows communication between the various components of the module ( 16 ).
  • the tuner ( 20 ) and other hardware blocks ( 24 ) are connected for communication with a processor ( 30 ).
  • a serial peripheral interface ( 32 ) is provided for communication with the application processor ( 12 ) of the receiver ( 2 ).
  • a ROM ( 34 ) and RAM ( 36 ) are provided.
  • FIG. 4 is a flow diagram illustrating schematically what happens in the arrangement for FIG. 3 during start-up of the module ( 16 ).
  • a reset signal is provided to the module ( 16 ) and to the processor ( 30 ). This causes the processor ( 30 ) to start executing instructions located at address 0x0000 which physically maps to the ROM ( 34 ) which itself contains a boot loader for downloading code from the application processor ( 12 ) of the receiver ( 2 ).
  • the boot loader uses the serial peripheral interface ( 32 ), the boot loader receives from the application processor ( 12 ) and stores in RAM ( 36 ) the boot configuration parameters. For example, these parameters could include the bandwidth of the device (for example 5, 6, 7 or 8 MHz) and the frequency of the receiver source clock.
  • step S 14 the boot loader then downloads, from the application processor ( 12 ), the firmware ( 26 ) and stores this in RAM ( 36 ).
  • the downloaded image as stored in RAM ( 36 ) will include the operating system for the module ( 16 ). For reasons to be discussed, significantly, this process takes an appreciable amount of time, for instance approximately 200 ms.
  • step S 16 the ROM boot loader remaps the memory such that address 0x0000 now physically points to the RAM ( 36 ) instead of the ROM ( 34 ).
  • step S 18 the processor ( 30 ) is made to start executing instructions at address 0x000 again, which now (as a consequence of step S 16 ) physically maps to the RAM ( 36 ), which itself contains the firmware ( 26 ).
  • step S 20 the firmware stored in the RAM ( 36 ) causes the processor ( 30 ) to start the operating system as also stored in RAM ( 36 ).
  • step S 22 the firmware ( 26 ) retrieves the configuration parameter values as stored in step S 12 . These are preferably stored at a predetermined or fixed place in RAM ( 36 ). The values are then put in memory according to requirements such that, in step S 24 , the hardware blocks, including the tuner and filters etc. can be initialized. In particular, the firmware uses the configuration parameters in initializing the hardware.
  • step S 26 appropriate threads (to be discussed further below) for carrying out various tasks are created.
  • module ( 16 ) still awaits commands from the application processor ( 12 ) with regard to tuning or creating filters for appropriate television programmes etc.
  • the present application contemplates for the first time the use of an abort command which, rather than operate the entire reset process of FIG. 4 causes the module ( 16 ) to stop any and all current operations and release all resources without requiring the processor ( 30 ) to stop individually every single operation.
  • the firmware ( 26 ) controlling the processor ( 30 ) does not individually stop operations and release resources, but merely re-initializes the operating system kernel.
  • FIG. 5 is a flow diagram illustrating schematically what happens upon receiving the abort command.
  • step S 30 the abort command is sent from the application processor ( 12 ) to the module ( 16 ).
  • step (S 32 ) the firmware kills all threads, timers and events, as well as mutexes by which simultaneous operation by two threads is prevented. In this way, all processes being carried out by the module ( 16 ) stop what they are doing and all operating system memory structures are cleared.
  • a section of memory includes data of the operating system for active threads such that the operating system is aware of those active threads.
  • the firmware kills all threads it is not necessary to delete all stored threads, but only to clear the memory block used by the operating system to store the list of active threads. As a result, the operating system does not see any of the threads which were in existence. Significantly, this process is almost instantaneous.
  • step S 34 the firmware starts the operating system again. In other words, it re-initializes the bootstrap function and carries out a process similar to S 20 of FIG. 4 .
  • step S 22 it is not then necessary to conduct the step S 22 , because it is not necessary to re-store the configuration parameters; these will already be correctly stored in memory. At this point it is worth noting that, if it is required to use different configuration parameters, for instance to use a different bandwidth, then a full reset process would be required.
  • step S 36 of the abort process is more simple.
  • hardware relating to communication in particular the serial peripheral interface ( 32 ) is not re-initialized.
  • the serial peripheral interface ( 32 ) since the serial peripheral interface ( 32 ) handles communication with the application processor ( 12 ) regarding the abort process, the serial peripheral interface ( 32 ) is not re-initialized.
  • the processing state is kept in memory and restored to the serial peripheral interface ( 32 ) after initialization, then it would be possible to carry out a full hardware re-initialization similar to step S 24 of the reset process.
  • step S 38 the appropriate threads are created in the same manner as in step S 26 of the reset process.
  • step S 40 the firmware sends an abort response to the application processor ( 12 ) by means of the serial peripheral interface ( 32 ) so as to confirm to the application processor ( 12 ) that the abort process has completed.
  • the module configuration (as done in step S 22 ), the VIC (Vectored Interrupt Controller).
  • Some other blocks are only partially re-initialized: the demodulator, the SPI and SDIO controller (used for host protocol communication), and the DMA (Direct Memory Access) controller.
  • the module ( 16 ) may be provided as a demodulator chip, such as a DVB-H demodulator chip. Embedded firmware may be provided for the DVB-H demodulator chip.
  • the general approach applies to any software system, embedded or not, that performs a single basic operation, in particular where the system state after aborting or stopping the current operation is equivalent to the initial state after power-up.
  • the receiver ( 16 ) implements a communication protocol that enables a host application processor ( 12 ) to control it.
  • This protocol consists of commands to configure and initiate the main functions of the receiver ( 16 ), for instance scan the frequency spectrum to find DVB-H signals, tune on a specific frequency and set up SI and MPE filters and receive payload data.
  • the protocol also contains commands to stop operations such as stop an ongoing frequency spectrum scan and stop and release (clear) SI and MPE filters.
  • the receiver ( 2 ) however implements a communication protocol which is novel by 1) defining an additional #ABORT command that causes the receiver to stop any and all current operations and release all resources without requiring the host application processor to individually stop every single operation and 2) providing the embedded firmware implementation of the #ABORT command itself which does not individually stop operations and release resources, but, instead, re-initializes the operating system kernel.
  • the #ABORT command provides a quick and simple way for the host application processor ( 12 ) to return the receiver ( 16 ) to a clean state, e.g. in preparation for tuning to a different frequency or creating a different set of SI and MPE filters. Also, not having to iterate through all operations to stop, and all resources to release, reduces the amount of code and makes the embedded firmware smaller, therefore saving on embedded memory.
  • the receiver software (previously described as firmware) implementation operates on the embedded real-time kernel operating system ThreadX from Express Logic, Inc. In the initialization process of a ThreadX system one can distinguish a number of steps:
  • the system is in a known state X where it can start receiving commands from the host.
  • step 3.c. the implementation of software modules should take into account that global and static variables are initialized only in step 2 of the initialization process. If any global or static variable is expected to be re-initialized on #ABORT, it should be done explicitly in the initialization method of the particular module.
  • FIG. 6 illustrates schematically an example of the software side of digital television reception such as operated in a module such as module ( 16 ) discussed above.
  • each service can make use of one or more device drivers ( 44 ) corresponding to respective devices or hardware blocks ( 20 , 24 ).
  • the present application considers for the first time issues of power consumption of the various devices or hardware blocks ( 20 , 24 ). These devices or hardware blocks ( 20 , 24 ) consume power when turned on and the present application recognises the advantages, particularly for battery powered devices, to turn off the devices or hardware blocks ( 20 , 24 ) when they are not being used.
  • a digital television receiver it is quite usual for a digital television receiver to receive and process blocks of data in bursts. Hence, at different times during reception and processing of those burst, various hardware blocks or devices will or will not be in use.
  • the present application proposes the use of a power management application programming interface (API) ( 46 ) for each driver ( 44 ). This is illustrated schematically in FIG. 7 .
  • API application programming interface
  • the power management API includes a counter which is incremented each time a service ( 42 ) requests use of the corresponding device or hardware block ( 20 , 24 ) and is decremented each time use of that device or hardware block ( 20 , 24 ) is released.
  • the power management API ( 46 ) provides a power signal ( 48 ) for the respective device or hardware block ( 20 , 24 ). Responsive to this power signal ( 48 ), the respective device or hardware block ( 20 , 24 ) can be powered up or down.
  • the power signal ( 48 ) could be used in a number of different ways to control the power of respective devices or hardware blocks ( 20 , 24 ).
  • FIG. 8 illustrates schematically an arrangement where the power signal ( 48 ) is used in conjunction with the main clock signal ( 50 ) and a clock block ( 52 ).
  • the clock signal ( 50 ) is provided to the hardware blocks ( 20 , 24 ) by means of a clock block ( 52 ).
  • This may be embodied as a hardware block including a plurality of gates ( 54 ) corresponding respectively to hardware blocks ( 20 , 24 ). Each gate is enabled or not according to the respective power signal ( 48 ). In this way the power management API ( 46 ) of a driver ( 44 ) controls whether or not the clock signal ( 50 ) is supplied to the respective hardware block ( 20 , 24 ).
  • Either “or” or “and” gates can be used. With an “and” gate, setting the power signal ( 48 ) to “one” powers up the hardware; setting it to “zero” powers it down. With an “or” gate, setting the power signal ( 48 ) to “one” maintains the block clock at “one” thus freezing the clock and therefore powering down the block; setting the power signal ( 48 ) to “zero” makes the block clock equivalent to the system clock, thus powering up the block.
  • the hardware uses “or” gates and thus the power signal must be inverted (one means off, zero means on).
  • this arrangement can be used in any circuit where there are a plurality of the individual hardware blocks which can be selectively powered up or down. It is particularly useful in a digital television receiver, such as a DVB-H receiver or module, such as module ( 16 ) for use in such a receiver. However, it will have other applications, for instance in a mobile telephone or personal computer.
  • a system and a method of operating a system in particular using reference counting to save power by disabling the clocks of individual hardware blocks that are not needed.
  • the approach applies to any system in which the power state of hardware blocks can be controlled independently, and the hardware blocks are used by multiple software tasks or threads asynchronously.
  • the receiver hardware ( 20 , 24 . 52 ) will allow the power of each block ( 20 , 24 ) to be controlled independently, to save even more power. For example, once a burst has been received and stored in the MPE-FEC memory ( 24 ), the tuner ( 20 ), demodulator ( 24 ) and filter blocks ( 24 ) can be turned off while the burst is being error-corrected and transferred to the host or application processor ( 12 ). Only after this will the MPE-FEC block be turned off. As discussed above, difficulties in the embedded firmware implementation come from the fact that the power state of a single hardware block ( 20 , 24 ) may depend on the activities of multiple tasks ( 40 ).
  • the tuner may be used by the interface handler (or interface handler task ( 40 )) to perform a SCAN command or by the time slicer (or time slicer task ( 40 )) to receive a burst.
  • the MPE-FEC may have to process parallel IP services.
  • each device driver ( 44 ) can independently manage the power state of the hardware block it controls.
  • an example of a synchronous power management API is as follows:
  • a client or service ( 42 ) will call the PowerUp( ) function to indicate that it requires the power state of the device to be held on POWERED_ON.
  • the driver ( 44 ) will immediately turn on the device ( 20 , 24 ) if it is not already on.
  • the client or service ( 42 ) then calls PowerDown( ) when the hold can be released.
  • the device power state will actually switch to POWERED_OFF only if no other client or service ( 42 ) is holding the power on. This is implemented by the driver ( 44 ) maintaining a power state counter.
  • the state is initialized to 0, incremented every time PowerUp( ) is called and decremented every time PowerDown( ) is called.
  • the device ( 20 , 24 ) is turned off when the counter value is 0.
  • Some services ( 42 ) (Tuning, SI extraction and IP extraction) will implement the same APIs.
  • Each device driver implements the power management API, by the use of which services or tasks can control the power state of the corresponding hardware block.
  • the tuning service knows that the tuner and demodulator blocks must be powered on to perform a tune operation. However, it does not know when these blocks can be powered down, which would be at the end of the reception of the current burst (i.e. time-slice), which only the IP reception tasks knows about.
  • tasks do not access device drivers and their APIs directly, but only through the intermediate services blocks in the service layer.
  • the services can forward power management requests from the tasks to the device drivers. This is achieved by having services implement the same power management API as device drivers.
  • the power management APIs are implemented in a way similar to how it is in the device drivers, i.e. with reference counting. The only difference is that instead of controlling a power signal, services call the PowerUp( ) and PowerDown( ) functions of the underlying device drivers, when the reference count is non-zero or zero respectively.
  • time slicer task illustrated in FIG. 6 can easily be implemented as shown in the following pseudo-code:
  • the present application proposes a new system where the power state of individual hardware blocks ( 20 , 24 ) that are used in combination by multiple software tasks can be controlled independently by disabling their individual clock signal.
  • Reference counting in the lowest software layer (device drivers) ( 44 ) may be used to determine when a hardware block can be powered on or off when 1) there are multiple software tasks sharing the same hardware resources; and 2) the multiple software tasks use the hardware resources (and need them to be powered up) asynchronously.
  • a standard power control reference counting API that can be implemented not only in the driver layer, but also in all the software layers above it, to shield the top layers from having to know which hardware blocks are indirectly used through function call to intermediate layers.
  • system architecture and implementation can be simplified as some global state is not required to be queried or modified by all software components using a specific power controlled hardware block.
  • IP extraction mainly requires the use of three main hardware components, namely, the Tuner/Demodulator block, Transport Filter block and FEC Frame Controller block.
  • the software architecture is composed of tasks on top of services which are on top of drivers.
  • every hardware block ( 20 , 24 ) is controller by a driver ( 44 ).
  • Hardware blocks ( 20 , 24 ) implementing power management functionalities have their PowerUp( ) and PowerDown( ) couple of functions.
  • Each PowerUp( ) function counts the number of times it is called, the first time it is called the hardware block is powered-on and the counter usage is incremented. All subsequent calls to this PowerUp( ) will only increment the usage counter.
  • the PowerDown( ) works the same way except that it decrements its usage counter until it reaches 0, at this point the hardware ( 20 , 24 ) will be really powered-off.
  • the hardware blocks and their power control functions are as follows.
  • the Tuner block is required to be powered-on prior to any other blocks.
  • the Demodulator block is also required to be active before data can be extracted.
  • Tuner and Demodulator blocks are coupled together.
  • the Tuner and Demodulator blocks can have their own PowerUp( ) and PowerDown( ) functions to save power.
  • the Transport Filter clock can be activated or deactivate to save power using the DrvDemux_PowerUp( ) and DrvDemux_PowerDown( ) functions.
  • the FEC Frame Controller clock can be activated or deactivate to save power using the DrvFec_PowerUp( ) and DrvFec_PowerDown( ) functions.
  • the FEC block requires the Transport Filter block to be active to actually receive data, therefore the DrvFec_PowerUp( ) resp. DrvFec_PowerDown( ) functions also internally invoke the DrvDemux_PowerUp( ) resp. DrvDemux_PowerDown( ) functions.
  • the services ( 42 ) can also have the PowerUp( ) and PowerDown( ) functions which are called by the tasks using those services. Generally they are also implemented using a usage counter and a call to a driver power control function.
  • each IP filter extraction running from a task powers up specific resources whenever it needs them and powers them off when they are not needed anymore, the key architecture point here is the fact that each IP or SI filter is treated independently and uses the power control functions of each shared resource.
  • FIG. 9 represents the power counter usage value of the three main drivers and the following shows Pseudo-code for 2 independent services running concurrently with values between parenthesis represents the power usage counter of every driver.
  • the number of tasks are required to be carried out simultaneously or at least in an overlapping manner.
  • Each time slicer task could have in use its own respective set of services (for instance tuning, S/PSI:extraction and IP:extraction services) or more preferably, and as illustrated, share the same set of services.
  • a first co-routine could be constructed with yield points after step A 1 and after step A 2 and, similarly, a co-routine could be constructed with yield points after step B 1 , after step B 2 and after step B 3 .
  • the overall process would proceed in a known manner by, for instance, starting with step A 1 and, at the yield point at the end of step A 1 , checking to see whether the system is ready to carry out step B 1 . If the system is ready, the process moves to step B 1 , otherwise, the process moves on to A 2 .
  • This arrangement provides some degree of flexibility without the memory demands of stacks for each process.
  • the present application proposes for the first time an arrangement in which co-routines are embedded within an individual thread.
  • processes alsowise described here as tasks
  • processes which have the same or similar priority can be arranged as co-routines within a single thread, allowing processes with quite different priorities to have their own individual threads.
  • only a single memory stack is needed for the multiple time slicer tasks.
  • the interface handler or signal locker needs to interrupt the time slicer tasks, this can be done, because they operate with separate threads having respective memory stacks.
  • the tasks to be performed by the software of the preferred embodiment are 1) configuring and controlling the tuner and the demodulator, scheduling time slices and extracting SI/PSI tables and IP services, and communicating with the host application processor ( 12 ).
  • the goal of the architecture is to make it possible to perform all the software tasks while optimizing timing, power consumption and memory usage.
  • tasks such as extracting SI/PSI tables, performing software AGC, or sending debug messages to the UART, are less time-critical than processing MPE-FEC frames and extracting IP services. They could have to be made pre-emptible by the IP service task
  • memory is a critically sparse resource in many devices, such as a DVB-H receiver.
  • no more than 64 kiB of RAM might be available. Therefore, the architecture should aim at minimizing: code size; data size; and stack space.
  • RTOS Real-Time Operating System
  • each RTOS thread requires a separate execution stack, which increases the total memory requirement of the system.
  • a DVB-H receiver ( 2 ) which assigns the software tasks to a combination of 1) RTOS pre-emptible threads, to achieve real-time constraints for tasks ( 40 ) that have them and 2) classical co-operative co-routines for tasks ( 40 ) that do not have relative real-time priorities.
  • Groups of co-routines are run within a single RTOS pre-emptible thread, and therefore share the same execution stack.
  • Multi-tasking is achieved by co-operative scheduling, which means each task (i.e. co-routine) co-operative yields control from time to time to allow other tasks (i.e. co-routine) to execute.
  • co-operative scheduling which means each task (i.e. co-routine) co-operative yields control from time to time to allow other tasks (i.e. co-routine) to execute.
  • the top layer blocks ( 40 ) are called tasks, but can be considered to be threads.
  • the time slicer thread runs several co-routines, each co-routine executing one respective IP reception task.
  • the number of RTOS threads in the system should be kept to a strict minimum.
  • some tasks should run asynchronously and within low timing constraints.
  • FIG. 11 An example of real time task scheduling is shown in FIG. 11 . Although the tasks involved have been mentioned above, a brief summary of each is given below.
  • the time slicer task is a low-priority task which controls the system heartbeat. For every (for example DVB-H) time slice, it 1) requests the Tuning service to wake up the hardware and reacquire the signal lock, 2) waits for SI/PSI or IP events and processes them, 3) requests the Tuning service to shut off the hardware, and 4) sleeps until the next time slice.
  • this thread actually runs several co-routines. Each co-routine performs the task of receiving a single IP service as listed above, allowing other IP services to be processed by using co-operative scheduling.
  • the interface handler is a medium-priority task which handles the host processor commands, which by nature are asynchronous to the stream handling. It manages the receiver state and uses the Tuning service to implement the SCAN and TUNE commands. Because the SPI host interface is a performance bottleneck, this task must have a higher priority than the time slicer task.
  • the signal locker is a high-priority task which responds to the signal lock lost event or any other events that require quick handling. In case of signal lock lost, it initiates the recovery procedure.
  • the idle task is the lowest priority task in the system. It is scheduled only when all the other tasks are sleeping and or pending on an event. Its only function is to set the processor ( 30 ) in a low-power state.
  • FIG. 11 illustrates typical scheduling scenarios and demonstrates how an RTOS helps construct a simple design that meets the low-latency timing and power constraints.
  • Section (a) shows the idle task being scheduled between time slices. The only thing this task does is to put the processor ( 30 ) into a low-power state. The processor ( 30 ) will wake up at the next time slice (timer set up by the time slicer task) or whenever a host command is received (SPI/SDIO interrupt) and to be processed by the interface handler.
  • Section (b) illustrates how the real-time scheduling properties enable serving host commands quickly, even if the time slicer is running. For example, if the host sends a SEND_STAT_DATA command while the time slicer is processing SI tables, basically the only delay before the request is served will be a context switch.
  • Section (c) illustrates multiple levels of pre-emption. It shows how an RTOS helps handling signal lock lost interrupts with virtually no delays.
  • the receiver will support the reception of up to four IP services simultaneously, each IP service having its own value for delta-t and its own power-up periods that may overlap with that of other IP services.
  • co-operative multi-tasking is used. This is could be implemented with state machines, but preferred embodiments use the more elegant, easier to read and easier to maintain co-routines.
  • co-routines allow multiple exit points in a function, while maintaining the execution state, which makes the control flow more explicit than in a switch-based state machine. Indeed a co-routine allow a co-operative task to be implemented in a way that is independent from other tasks.

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US20090293072A1 (en) 2009-11-26
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US20090327676A1 (en) 2009-12-31
WO2008009366A1 (fr) 2008-01-24
WO2008009367A1 (fr) 2008-01-24

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