US20220020316A1

US20220020316A1 - Display Device With Two-Dimensional Shared Lines For Controlling Distributed Driver Circuits

Info

Publication number: US20220020316A1
Application number: US17/149,402
Authority: US
Inventors: Richard Landry Gray; Chih-Chang WEI; Junjie Zheng; Li-Lun Chi
Original assignee: Huayuan Semiconductor Shenzhen Ltd Co
Current assignee: Huayuan Semiconductor Shenzhen Ltd Co
Priority date: 2020-07-16
Filing date: 2021-01-14
Publication date: 2022-01-20
Also published as: CN113948036A; CN114023248B; KR20220009902A; KR102667720B1; CN114023248A; CN113948036B; US11436970B2; US20220020310A1; KR102646130B1; KR20220009903A

Abstract

A display device comprises an array of driver circuits and LED zones distributed in a display area. A set of shared lines couple includes column lines coupling driver circuits in respective columns and row lines coupling driver circuits in respective rows. During an addressing mode, a control circuit assigns addresses to the driver circuits using a combination of the row lines and the column lines. During an operational mode, the control circuit sends driver control commands to the driver circuits utilizing the assigned addresses to control brightness of the LED zones. The control circuit may also send readback commands to the driver circuits to obtain readback data relating to sensed conditions. The control circuit may adjust the driver control commands based on the sensed conditions.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No. 63,052,844 filed on Jul. 16, 2020, which is incorporated by reference herein.

BACKGROUND

This disclosure relates generally to light emitting diodes (LEDs) and LED driver circuitry for a display, and more specifically to a display architecture with distributed driver circuits.
LEDs are used in many electronic display devices, such as televisions, computer monitors, laptop computers, tablets, smartphones, projection systems, and head-mounted devices. Modern displays may include well over ten million individual LEDs that may be arranged in rows and columns in a display area. In order to drive each LED, current methods employ driver circuitry that require significant amounts of external chip area that impacts the size of the display device.

SUMMARY

A display device comprises an array of light emitting diode zones, an array of driver circuits, a set of shared lines, and a control circuit. The array of light emitting diode zones each comprise one or more light emitting diodes that generate light in response to respective driver currents. The driver circuits are distributed in the display area of the display device. The driver circuits drive respective light emitting diode zones with the respective driver currents based on driver control commands and generate readback data comprising sensed conditions in response to readback commands. The set of shared lines communicate the driver control commands, the readback commands and the readback data. The set of shared lines include row lines coupling driver circuits in respective rows of the array of driver circuits and column lines coupling driver circuits in respective columns of the array of driver circuits. The control circuit operates in an addressing mode to assign addresses to the array of driver circuits based on addressing signals sent on the row lines and the column lines. The control circuit also operates in an operational mode to generate the readback commands, to obtain the readback data in response to the readback commands, and to generate the driver control commands based at least in part on the readback data. The driver control commands include an address associated with a targeted driver circuit.
In an embodiment, the set of shared lines include a set of power lines coupling the driver circuits in the respective rows. The set of power lines provide respective supply voltages to driver circuits in the respective rows. A set of data input lines couple the driver circuits in the respective columns for providing the driver control commands and the readback commands to driver circuits in the respective columns. A set of data output lines couple the driver circuits in the respective columns for communicating the readback data to the control circuit in response to the readback commands.
In another embodiment, the set of shared lines include a set of power lines coupling the driver circuits for providing the respective supply voltages to those driver circuits in the respective rows. A set of data input lines couple the driver circuits in the respective columns for communicating addressing signals during the addressing mode to assign respective addresses to the driver circuits in the respective columns such that all driver circuits within a column have a same address and all driver circuits in a row have different addresses. A set of data output lines that couple the driver circuits in the respective rows communicate the readback data to the control circuit in response to the readback commands.
In another embodiment, the set of shared lines include a set of power communication lines coupling the driver circuits in the respective rows. The set of power communication lines provide respective supply voltages to driver circuits in the respective rows, and provide the driver control commands and the readback commands as digital data modulated on the supply voltages during an operational mode. A set of bidirectional data lines couple the driver circuits in the respective columns. The set of bidirectional data lines communicate the addressing signals from the control circuit during the addressing mode to assign respective addresses to the driver circuits in the respective columns such that all driver circuits within a column have a same address and all driver circuits in a row have different addresses. The set of bidirectional data lines communicate the readback data to the control circuit in response to the readback commands during the operational mode.
In yet another embodiment, the set of shared lines include a set of data input lines coupling the driver circuits in the respective rows to sequentially send row select signals from the control circuit during the addressing mode to select respective rows of the array of driver circuits for address assignment during sequential row select periods. A set of bidirectional data lines couple the driver circuits in the respective columns. In an embodiment, the set of bidirectional data lines sequentially send column select signals from the control circuit during each of the sequential row select periods of the addressing mode to select respective columns of the array of driver circuits for address assignment during sequential row-column select periods. The set of bidirectional data lines also communicate the readback data to the control circuit in response to the readback commands during an operational mode. A set of power communication lines couple the driver circuits in the respective rows. The set of power lines provide respective supply voltages to driver circuits in the respective rows. The set of power communication lines also send address assignments to respective selected driver circuits during each of the row-column select periods of the addressing mode.
In another embodiment, the set of shared lines include a set of data input lines coupling the driver circuits in the respective rows. The set of data input lines sequentially send row select signals from the control circuit during an addressing mode to select respective rows of the array of driver circuits for address assignment during sequential row select periods. A set of bidirectional data lines couple the driver circuits in the respective columns. The set of bidirectional data lines sequentially send column addressing signals from the control circuit during each of the sequential row select periods of the addressing mode to assign addresses to respective driver circuits. The set of bidirectional data lines also communicate the readback data to the control circuit in response to the readback commands during an operational mode. A set of power lines couple the driver circuits in the respective rows for providing respective supply voltages to driver circuits in the respective rows.

BRIEF DESCRIPTION OF THE DRAWINGS

The teachings of the embodiments of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings.

FIG. 1 is a circuit diagram of a first embodiment of a display device, according to one embodiment.

FIG. 2 is a waveform diagram illustrating first example waveforms of an addressing process for a display device, according to one embodiment.

FIG. 3 is a circuit diagram of a second embodiment of a display device, according to one embodiment.

FIG. 4 is a waveform diagram illustrating second example waveforms of an addressing process for a display device, according to one embodiment.

FIG. 5 is a circuit diagram of a third embodiment of a display device, according to one embodiment.

FIG. 6 is a waveform diagram illustrating third example waveforms of an addressing process for a display device, according to one embodiment.

FIG. 7 is a circuit diagram of a driver circuit, according to one embodiment.

FIG. 8A is a cross sectional view of a first embodiment of an LED and driver circuit that may be utilized in a display device.

FIG. 8B is a cross sectional view of a second embodiment of an LED and driver circuit that may be utilized in a display device.

FIG. 8C is a cross sectional view of a third embodiment of an LED and driver circuit that may be utilized in a display device.

FIG. 9 is a top down view of a display device using an LED and driver circuit, according to one embodiment.

FIG. 10 illustrates a schematic view of several layers of an LED and driver circuit for a display device, according to one embodiment.

The features and advantages described in the specification are not all inclusive and many additional features and advantages will be apparent to one of ordinary skill in the art in view of the drawings, specification, and claims.

DETAILED DESCRIPTION

A display device comprises an array of driver circuits and LED zones distributed in a display area. A set of shared lines includes column lines coupling driver circuits in respective columns and row lines coupling driver circuits in respective rows. During an addressing mode, a control circuit assigns addresses to the driver circuits using a combination of the row lines and the column lines. During an operational mode, the control circuit sends driver control commands to the driver circuits utilizing the assigned addresses to control brightness of the LED zones. The control circuit may also send readback commands to the driver circuits to obtain readback data relating to sensed conditions. The control circuit may adjust the driver control commands based on the sensed conditions.
(FIG.) 1 is a circuit diagram of a display device 100 for displaying images or video, according to one embodiment. In various embodiments, the display device 100 may be implemented in any suitable form-factor, including a display screen for a computer display panel, a television, a mobile device, a billboard, etc. The display device 100 may comprise a liquid crystal display (LCD) device or an LED display device. In an LCD display device, LEDs provide white light backlighting that passes through liquid crystal color filters that control the color of individual pixels of the display. In an LED display device, LEDs are directly controlled to emit colored light corresponding to each pixel of the display.
The display device 100 includes a device array 105 of distributed zone integrated circuits (ICs) 150. Each zone IC 150 includes a driver circuit 120 and one or more LEDs of an LED zone 130. The LED zones 130 each correspond to pixels of a digital image that have color and intensity based on data received from the control circuit 110. The device array 105 may be arranged in rows and columns. Each row may share a common power line (Pwr1, PwrM) 160 controlled by a row controller 112. Each column may share a common data input line (Di1, . . . DiN) 170 and data output line (Do1, . . . DoN) 180 controlled by a column controller 114. Zone ICs 150 in a row or column of the device array 105 may also share other lines (not shown) such as voltage supply lines (VLED) for the LED zones 130 and ground lines (GND). In another embodiment, a shared power line provides power to both the driver circuits 120 and the LED zones 130 in a group (e.g., a row or column). As used herein, a row or column may refer to a partial row or column and not necessarily to the entire row or column of the display device 100.
As will be described in further detail below, the device array 105 may be physically structured such that the LED zones 130 are stacked over the driver circuits 120. In other words, an array of LED zones 130 are arranged in a first x-y plane and an array of driver circuits 120 are arranged in a second x-y plane parallel to the first x-y plane. In one configuration, each LED zone 130 is stacked over (i.e., in the z direction) the corresponding driver circuit 120 that drives it. Furthermore, the components of the device array 105 (e.g., the LED zones 130 and the driver circuits 120) may be integrated on the same substrate and in a same package as further described in FIGS. 8-10. This structure enables a display device 100 in which the driver circuits 120 are distributed in a display area and therefore enables a more compact display device 100 than in devices where the driver circuits 120 are external to the display area.
The LED zones 130 each comprise one or more LEDs that each generate light that has a brightness dependent on respective driver currents provided by the corresponding drivers 120. In an LCD display, an LED zone 130 may comprise one or more LEDs that provides backlighting for a backlighting zone, which may include a one-dimensional or two-dimensional array of pixels. In an LED display, the LED zone 130 may comprise one or more LEDs corresponding to a single pixel of the display device 100 or may comprise a one-dimensional array or two-dimensional array of LEDs corresponding to an array of pixels (e.g., one or more columns or rows). For example, in one embodiment, the LED zone 130 may comprise one or more groups of red, green, and blue LEDs that each correspond to a sub-pixel of a pixel. In another embodiment, the LED zone 130 may comprise one or more groups of red, green, and blue LED strings that correspond to a column or partial column of sub-pixels or a row or partial row of sub-pixels. For example, an LED zone 130 may comprise a set of red sub-pixels, a set of green sub-pixels, or a set of blue sub-pixels.
The LEDs may be organic light emitting diodes (OLEDs), inorganic light emitting diodes (ILEDs), mini light emitting diodes (mini-LEDs) (e.g., having a size range between 100 to 300 micrometers), micro light emitting diodes (micro-LEDs) (e.g., having a size of less than 100 micrometers), white light emitting diodes (WLEDs), active-matrix OLEDs (AMOLEDs), transparent OLEDs (TOLEDs), or some other type of LEDs.
The driver circuits 120 drive the LED zones 130 by controlling the respective driver currents to the LED zones 130 in response to driver control signals. In an embodiment, a driver circuit 120 controls a driver current supplied by a power supply (not shown) to control brightness of one LED zone 130 based on the driver control signals. For example, brightness of the LED zone 130 generally increases with increasing driver current.
In an embodiment, the driver circuits 120 each drive multiple channels of a corresponding LED zone 130 that may each have separately controllable driver currents. For example, the driver circuit 120 may independently control LED currents corresponding to red, green, and blue channels of the LED zones 130 via separate output pins.
A set of shared lines couple different groups of driver circuits 120 with the control circuit 110. The shared lines may include column lines that each couple a column of driver circuits 120 to a column controller 114 and row lines that each couple a row of driver circuits 120 to a row controller 112. For example, in the embodiment of FIG. 1, the power lines 160 correspond to row lines and the data input lines 170 and data output lines 180 each correspond to column lines. In alternative embodiments, different arrangements may be used.
The driver circuits 120 may operate in various modes including at least an addressing mode, a configuration mode, and an operational mode. During the addressing mode, the control circuit 110 initiates an addressing procedure to cause assignment of addresses to each of the driver circuits 120. In an embodiment, different addresses are assigned to driver circuits 120 that are in different rows, but all of the driver circuits 120 in a particular row are assigned the same address. For example, all driver circuits 120 in the first row receive an address ID_1, all driver circuits 120 in a second row receive an address ID_2, and so on. Examples of waveforms associated with an addressing process are described below with reference to FIG. 2.
During the configuration and operational modes, the control circuit 110 transmits commands and data that may be targeted to specific driver circuits 120 based on their addresses. For example, in the configuration mode, the control circuit 110 configures the driver circuits 120 with one or more operating parameters (e.g., overcurrent thresholds, overvoltage thresholds, clock division ratios, and/or slew rate control). During the operational mode, the control circuit 110 provides control data to the driver circuits 120 that causes the driver circuits 120 to control the respective driver currents to the LED zones 130, thereby controlling brightness. For example, in each of a sequence of image frames, the control circuit 110 provides driver control signals to the driver circuits 120 that control a driving current of the LED zones 130 (e.g., by controlling a duty cycle and/or current level through one or more LED strings). For example in FIG. 1, the column controller 114 provides the control commands through the proper data input line 170 together with the address (ID_x) of the targeted driver circuit 120. Each driver circuit 120 determines if the address associated with a received command matches its stored address and only executes the command if the target address matches. Otherwise, the command may be ignored. For instance, to send brightness information to the driver circuit 120 in the 3^rdrow and 2^ndcolumn, the column controller 114 sends the command via the data input line 170 Di2 accompanied by the ID-3 address associated with the third row.
The row controller 112 may also issue commands via the data input lines 170 to request readback data from driver circuits 120. In response to the readback commands, the driver circuits output the readback to the column controller 114 via the data output lines 180. The readback data can comprise various sensed conditions such as the channel voltages at the output to the LED channels, the temperature of each driver circuits 120, status information such as overvoltage/undervoltage flags for the driver circuits 120, or other fault information. The readback command may target an individual driver circuit 120 by specifying a target address, or may comprise a group command requesting readback data from all driver circuits 120 coupled to the data input line 170 (e.g., a column of driver circuits 120). The control circuit 110 may adjust driver control signals, supply voltage levels, sensor parameters, or other display parameters dependent on the received feedback data from the driver circuits 120. For example, the control circuit 110 may calibrate the driver circuits 120 based on the sensed data so that LED zones 130 each output the same brightness in response to the same brightness control signal, despite process variations or other sensed conditions that may otherwise cause variations. The calibration process may be performed by measuring light output, channel voltages, temperature, or other data that may affect performances of the LEDs. The calibration process may be repeated over time (e.g., as the display device 100 heats up during operation). In an embodiment, each driver circuit 120 may place its respective data output pin coupled to the data output line 180 in a high impedance state when the driver circuit 120 is not outputting so that it does not interfere with signals outputted by other driver circuits 120 coupled to the same data output line 180.
FIG. 2 illustrates example waveforms associated with an addressing process for the display device 100 of FIG. 1. Here, the row contoller 112 turns on the power lines (Pwr) 160 during sequential time slots. The column controller 114 outputs an address on the data input pins 170 and updates the address each time slot. In an embodmient, the column controller 114 outputs the same address on all data input pins 170 in a given time slot so that all driver circuits 120 in a row are assigned the same address. The power line 160 of each row may stay on after it initally turns on as long as the driver circuits 120 in each row are configured to ignore further addressing commands once they have been assigned an address. Thus, for example, during the first time slot of the addressing procedure, the power line 160 (Pwr1) associated with the top row of driver circuits 120 is turned on and the top row of driver circuits 120 are all assigned an address ID_1 via the data input line 170 Di1. Then, in the second time slot of the addressing procedure, the second power line 160 (Pwr2) associated with the second row of driver circuits 120 is turned on and the second row of driver circuits 120 are all assigned an address ID_2 via the data input line 170 Di2. During the second time slot, the driver circuits 120 in the top row may still be powered on but they will ignore the addressing command ID_2. This process continues until all rows of driver circuits 120 have received addresses.
FIG. 3 illustrates an alternative embodiment of a display device 300 that includes a device array 305 of distributed zone ICs 350, each including a driver circuit 320 and LED zone 330. The display device 300 furthermore includes a control circuit 310 comprising a column controller 314 and a row controller 312. The column controller 314 controls data input lines (Di) 370 that couple the column controller 314 with respective columns of driver circuits 320. The row controller 312 controls data output lines (Do) 380 that couple the row controller 312 with respective rows of driver circuits 320. The row controller 312 furthermore controls power line communication (PLC) lines 360 that each couple the row controller 312 to the respective rows of driver circuits 320. The PLC lines 360 provide both power to the driver circuits 320 and provide commands as digital data modulated on the supply voltage.
The zone ICs 350 may be physically structured similarly to the zone ICs 150 described above, but have a modified pin configuration and interact differently with the control circuit 310 as described below. Particularly, in the addressing mode, the column controller 314 outputs respective addresses on each data input line 370 such that all the driver circuits 320 in each column are given the same address. For example, the driver circuits 320 in the first column addresses each receive an address ID_1, the driver circuits 320 in the second column each receive addresses ID_2, and so on. Waveforms associated with the addressing phase are illustrated in FIG. 4, discussed in further detail below.
In the operational mode, the row controller 312 communicates driver control commands with brightness settings to the LED drivers via the PLC lines 360. Here, the commands on a PLC line 360 are sent together with an address that specifies which driver circuit 120 is being targeted by the command. Other driver circuits 320 that do not have the matching address may ignore the command. The row controller 312 may similarly send readback commands to the driver circuits 320 via the PLC lines 360 to request readback data such as temperature, channel voltage, or other sensed conditions. The targeted driver circuit 320 sends the readback data on the data output lines 380. The readback data can be sent via the data output lines 380 concurrently with the driver control commands being sent on the PLC lines 360. The readback commands may further optionally be sent as group commands targeted to all driver circuits 320 coupled to the same PLC line 360 instead of to a specific targeted driver circuit 320. In this case, the readback data can be sent back sequentially by the driver circuits 320 (e.g., in order of increasing address, decreasing address, or another pattern). In another embodiment, a specific driver circuit 320 can be targeted by a readback command by asserting a signal on the data input line 370 coupled to the targeted driver circuit 320.
In an alternative embodiment, the data output lines 380 may be omitted and the data input lines 370 may be bidirectional lines. Here, the same bidirectional data lines 370 may be used to both provide addressing inputs during the addressing mode and to provide readback data during the operational mode.
In another embodiment, the display device 300 does not have power communication lines 360 and instead includes separate dedicated power lines and driver control signal lines that provide the brightness information.
FIG. 4 illustrates example waveforms associated with an addressing process for the display device 300 of FIG. 3. Here, the column contoller 314 concurrently outputs different addresses on each of the data input lines 370 (ID_1, ID_2, . . . , ID_M) to assign different addresses to each column of the display device 300. This enables the display device 300 to assign addresses very quickly upon startup.
FIG. 5 illustrates an alternative embodiment of a display device 500 that includes a device array 505 of distributed zone ICs 550, each including a driver circuit 520 and LED zone 530. The display device 500 furthermore includes a control circuit 510. A set of bidirectional data lines 580 couple respective columns of driver circuits 520 to the control circuit 510. A set of data input lines 570 couple respective rows of driver circuits 520 along to the control circuit 510. Furthermore, a set of PLC lines 560 couple the respective rows of driver circuits 520 to the control circuit 510.
The zone ICs 550 may be physically structured similarly to the zone ICs 150 described above, but have a modified pin configuration and interact differently with the control circuit 510 as described below. Particularly, in the addressing mode, the control circuit 510 assigns addresses using both the data input lines 570 and data output lines 580, and optionally the PLC lines 560. For example, the control circuit 510 may assert an active signal on one of the data input lines 570 to identify an active row. Addresses may then be assigned to the driver circuits 520 in the active row via the PLC line 560 or via the bidirectional data lines 580. Here, unique addresses may be assigned to each driver circuit 520. Waveforms associated with the addressing phase are illustrated in FIG. 6, discussed in further detail below.
During the operational mode, the control circuit 510 broadcasts driver control signals including brightness information and/or readback commands to the driver circuits 510 in a row via the data input lines 570. Alternatively, the driver control signals and readback commands can be sent via the PLC lines 560. In response to a readback command, the driver circuits 520 output readback data via the bidirectional data lines 580. When sending commands, the targeted driver circuit 520 may be uniquely identified based on its address assigned during the addressing mode.
In another embodiment, the display device 500 does not have power communication lines 560 and instead includes separate dedicated power lines. In this embodiment, the driver and readback commands may be sent via the data input lines 570 or via a separate dedicated line.
FIG. 6 illustrates example waveforms associated with an addressing process for the display device 500 of FIG. 5. Here, the control circuit 510 initially asserts data input line 570 Di1 to select the first row of driver circuits 520. While the data input line 570 Di1 is asserted, the control circuit 510 sequentially asserts the data output lines 580 to sequentially select different driver circuits 520 in the first row. Concurrently, the control circuits 510 outputs address assignments via the PLC line 560. This process then repeats for the next data input line 570 until addresses are assigned to all driver circuits 520. In an alternative embodiment, addresses can instead be outputted sequentially or concurrently via the data otuput lines 580 while a data input line 570 is asserted to select a row. Thus, in this embodmient, digital data on the power communication line 560 is not necessarily utilized during addressing.
FIG. 7 is an example circuit diagram of a driver circuit 720, according to one embodiment. The driver circuit 720 may include a power/PLC control circuit 702, control logic 704, a pulse width modulation (PWM) dimming circuit 706, a transistor 708, and a brightness control circuit 710. The example driver circuit 720 furthermore includes a data input pin 712, a data output pin 714, one or more LED driving output pins 716, a power/PLC pin 718, and a ground pin 726 that provide external connections.
The power/PLC control circuit 702 is coupled to receive a supply voltage from the power/PLC pin 718 and provides power regulation to generate an output voltage for powering the control logic 704 or other components of the driver circuit 720. In some embodiments where power line communication is used, the power/PLC control circuit 702 furthermore may demodulate the supply voltage to extract the digitally encoded signal and provide it to the control logic 704. The control logic 704 receives data signals from the data input pin 712 and optionally from the power/PLC control circuit 702 if power line communication is used. In some embodiments, where the data output pin 714 provides bidirectional communication, data signals may also be received via the data output pin 714. Here, the received data signal may include addressing signals for assigning addresses, driver control signals for controlling the driver current to the LED zone 730, readback commands, or other signals. The control logic 704 may also output readback data to the data output pin 714 in response to readback commands.
The control logic 704 generates a PWM signal 722 for controlling the PWM dimming circuit 706 and a max current signal 724 for controlling the brightness control circuit 710. The PWM signal 722 specifies a duty cycle for controlling PWM dimming by the PWM dimming circuit 706. Based on the selected duty cycle, the PWM dimming circuit 706 controls timing of an on-state and an off-state of the transistor 708. During the on-state of the transistor 708, a current path is established from the LED driving output pin 716 (coupled to the LED zones 730) to the ground pin 726 through the transistor 708 and the brightness control circuit 710 to sink the driver current through the LEDs of the LED zones 730. During an off-state of the transistor 708, the current path is interrupted to block current from flowing through the LED zones 730. The brightness control circuit 710 receives the max current signal 724 from the control logic 704 and controls the current level that flows through the LEDs (from the LED driving output pin 716 to the ground pin 726) when the transistor 708 is in the on-state. The control logic 704 controls the duty cycle of the PWM dimming circuit 706 and the max current signal 724 of the brightness control circuit 710 to set the desired brightness of the LED zone 730 coupled to the output pin 716. Although the driver circuit 720 of FIG. 7 illustrates a single transistor 708 and LED driving output pin 716, the driver circuit 720 may include multiple instances of the transistor 708 and LED driving output pin 716 to control multiple LED channels of the LED zone 730 (e.g., different color channels) or of different LED zones.
FIG. 8A is a cross sectional view of a first embodiment of a display device 800 including an integrated LED and driver circuit 805. In the example shown in FIG. 8A, the display device 800 includes a printed circuit board (PCB) 810, a PCB interconnect layer 820, and the integrated LED and driver circuit 805 which comprises a substrate 830, a driver circuit layer 840, an interconnect layer 850, a conductive redistribution layer 860, and an LED layer 870. Bonded wires 855 may be included for connections between the PCB interconnect layer 820 and the integrated LED and driver circuit 805. The PCB 810 comprises a support board for mounting the integrated LED and driver circuit 805, the control circuit and various other supporting electronics. The PCB 810 may include internal electrical traces and/or vias that provide electrical connections between the electronics. A PCB interconnect layer 820 may be formed on a surface of the PCB 810. The PCB interconnect layer 820 includes pads for mounting the various electronics and traces for connecting between them.
The integrated LED and driver circuit 805 includes the substrate 830 that is mountable on a surface of the PCB interconnect layer 820. The substrate 830 may be, e.g., a silicon (Si) substrate. In other embodiments, the substrate 830 may include various materials, such as gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), aluminum nitride (AlN), sapphire, silicon carbide (SiC), or the like.
The driver circuit layer 840 may be fabricated on a surface of the substrate 830 using silicon transistor processes (e.g., BCD processing). The driver circuit layer 840 may include one or more driver circuits 120 (e.g., a single driver circuit or a group of driver circuits arranged in an array). The interconnect layer 850 may be formed on a surface of the driver circuit layer 840. The interconnect layer 850 may include one or more metal or metal alloy materials, such as Al, Ag, Au, Pt, Ti, Cu, or any combination thereof. The interconnect layer 850 may include electrical traces to electrically connect the driver circuits 120 in the driver circuit layer 840 to wire bonds 855, which are in turn connected to the control circuit 110 on the PCB 810. In an embodiment, each wire bond 855 provides an electrical connection between the driver circuit or LED zone and the control circuit or other electronic components (e.g., power and ground lines). Additionally, the interconnect layer 850 may provide electrical connections for supplying the driver current between the driver circuit layer 840 and the conductive redistribution layer 860.
In an embodiment, the interconnect layer 850 is not necessarily distinct from the driver circuit layer 840 and these layers 840, 850 may be formed in a single process in which the interconnect layer 850 represents a top surface of the driver circuit layer 840.
The conductive redistribution layer 860 may be formed on a surface of the interconnect layer 850. The conductive redistribution layer 860 may include a metallic grid made of a conductive material, such as Cu, Ag, Au, Al, or the like. The LED layer 870 includes LEDs that are on a surface of the conductive redistribution layer 860. The LED layer 870 may include arrays of LEDs arranged into LED zones as described above. The conductive redistribution layer 860 provides an electrical connection between the LEDs in the LED layer 870 and the one or more driver circuits in the driver circuit layer 840 for supplying the driver current and provides a mechanical connection securing the LEDs over the substrate 830 such that the LED layer 870 and the conductive redistribution layer 860 are vertically stacked over the driver circuit layer 840.
Thus, in the illustrated circuit 805, the one or more driver circuits and the LED zones including the LEDs are integrated in a single package including a substrate 830 with the LEDs in an LED layer 870 stacked over the driver circuits in the driver circuit layer 840. By stacking the LED layer 870 over the driver circuit layer 840 in this manner, the driver circuits can be distributed in the display area of a display device.
FIG. 8B is a cross sectional view of a second embodiment of a display device 880 including an integrated LED and driver circuit 885, according to one embodiment. The device 880 is substantially similar to the device 800 described in FIG. 8A but utilizes vias 832 and corresponding connected solder balls 834 to make electrical connections between the driver circuit layer 840 and the PCB 810 instead of the wires 855. Here, the vias 832 are plated vertical electrical connections that pass completely through the substrate layer 830. In one embodiment, the substrate layer 830 is a Si substrate and the through-chip vias 832 are Through Silicon Vias (TSVs). The through-chip vias 832 are etched into and through the substrate layer 830 during fabrication and may be filled with a metal, such as tungsten (W), copper (C), or other conductive material. The solder balls 834 comprise a conductive material that provide an electrical and mechanical connection to the plating of the vias 832 and electrical traces on the PCB interconnect layer 820. In one embodiment, each via 832 provides an electrical connection for providing signals and supply lines to and from the driver circuits 120 and LED zones 130.
FIG. 8C is a cross sectional view of a third embodiment of a display device 890 including an integrated LED and driver circuit 895. The device 890 is substantially similar to the device 880 described in FIG. 8B but includes the driver circuit layer 840 and interconnect layer 850 on the opposite side of the substrate 830 from the conductive redistribution layer 860 and the LED layer 870. In this embodiment, the interconnect layer 850 and the driver circuit layer 840 are electrically connected to the PCB 810 via a lower conductive redistribution layer 865 and solder balls 834. The lower conductive redistribution layer 865 and solder balls 834 provide mechanical and electrical connections (e.g., for the driver control signals) between the driver circuit layer 840 and the PCB interconnect layer 820. The driver circuit layer 840 and interconnect layer 850 are electrically connected to the conductive redistribution layer 860 and the LEDs of the LED layer 870 via one or more plated vias 832 through the substrate 830. The one or more vias 832 seen in FIG. 8C may be utilized to provide the signals and supply lines as described above.
In alternative embodiments, the integrated driver and LED circuits 805, 885, 895 may be mounted to a different base such as a glass base instead of the PCB 810.
FIG. 9 is a top down view 900 of a display device using an integrated LED and driver circuit, according to one embodiment. The view 900 can correspond to any of the integrated LED and driver circuits 805, 885, 895 depicted in FIGS. 8A-C. A plurality of LEDs in an LED layer 870 is arranged in rows and columns (e.g., C1, C2, C3, . . . Cn−1, Cn) in FIG. 9. For passive matrix architectures, each row of LEDs of the LED layer 870 is connected by a conductive redistribution layer 860 to a demultiplexer which outputs a plurality of VLED signals (i.e., VLED_1 . . . VLED_M). The VLED signals provide power (i.e., a supply voltage) to a corresponding row of LEDs in the LED layer 870 via the conductive redistribution layer 860.
FIG. 10 illustrates a schematic view of several layers of a display device 1000 with an integrated LED and driver circuit, according to one embodiment. The schematic view includes the PCB 810, the driver circuit layer 840, the conductive redistribution layer 860, and the LED layer 870 as described in FIGS. 8A-C. The schematic of FIG. 10 shows circuit connections for the circuits 805, 885, 895 of FIGS. 8A-C but does not reflect the physical layout. As described above, in the physical layout, the LED layer 870 is positioned on top of (i.e., vertically stacked over) the conductive redistribution layer 860. The conductive redistribution layer 860 is positioned on top of the driver circuit layer 840 and the driver circuit layer 840 is positioned on top of the PCB 810.
The PCB 810 includes a connection to a power source supplying power (e.g., VLED) to the LEDs, a control circuit for generating a control signal, generic I/O connections, and a ground (GND) connection. The driver circuit layer 840 includes a plurality of driver circuits (e.g., DC1, DC2, DCn) and a demultiplexer DeMux. The conductive redistribution layer 860 provides electrical connections between the driver circuits and the demultiplexer DeMux in the driver circuit layer 840 to the plurality of LEDs in the LED layer 870. The LED layer 870 includes a plurality of LEDs arranged in rows and columns. In this example implementation, each column of LEDs is electrically connected via the conductive redistribution layer 860 to one driver circuit in the driver circuit layer 840. The electrical connection established between each driver circuit and its respective column of LEDs controls the supply of driver current from the driver circuit to the column. In this embodiment, each diode shown in the LED layer corresponds to an LED zone. Each row of LEDs is electrically connected via the conductive redistribution layer 860 to one output (e.g., VLED_1, VLED_2, . . . VLED_M) of the demultiplexer DeMux in the driver circuit layer 840. The demultiplexer DeMux in the driver circuit layer 840 is connected to a power supply (VLED) and a control signal from the PCB 810. The control signal instructs the demultiplexer DeMux which row or rows of LEDs are to be enabled and supplied with power using the VLED lines. Thus, a particular LED in the LED layer 870 is activated when power (VLED) is supplied on its associated row and the driver current is supplied to its associated column.
Upon reading this disclosure, those of skill in the art will appreciate still additional alternative embodiments through the disclosed principles herein. Thus, while particular embodiments and applications have been illustrated and described, it is to be understood that the disclosed embodiments are not limited to the precise construction and components disclosed herein. Various modifications, changes and variations, which will be apparent to those skilled in the art, may be made in the arrangement, operation and details of the method and apparatus disclosed herein without departing from the spirit and scope described herein.

Claims

1. A display device comprising:

an array of light emitting diode zones each comprising one or more light emitting diodes that generate light in response to respective driver currents;

an array of driver circuits distributed in the display area of the display device, the array of driver circuits to drive respective light emitting diode zones with the respective driver currents based on driver control commands and to generate readback data comprising sensed conditions in response to readback commands;

a set of shared lines to communicate the driver control commands, the readback commands and the readback data, the set of shared lines including row lines coupling driver circuits in respective rows of the array of driver circuits and column lines coupling driver circuits in respective columns of the array of driver circuits; and

a control circuit to operate in an addressing mode to assign addresses to the array of driver circuits based on addressing signals sent on the row lines and the column lines, and to operate in an operational mode to generate the readback commands, to obtain the readback data in response to the readback commands, and to generate the driver control commands based at least in part on the readback data, each driver control command including an address associated with a targeted driver circuit.

2. The display device of claim 1, wherein the set of shared lines comprises:

a set of power lines coupling the driver circuits in the respective rows, the set of power lines to provide respective supply voltages to driver circuits in the respective rows;

a set of data input lines coupling the driver circuits in the respective columns, the set of data input lines to provide the driver control commands and the readback commands to driver circuits in the respective columns; and

a set of data output lines coupling the driver circuits in the respective columns, the set of data output lines to communicate the readback data to the control circuit in response to the readback commands.

3. The display device of claim 2, wherein during the addressing mode, the control circuit sequentially turns on the respective supply voltages of the set of power lines during sequential time periods, and wherein the control circuit provides a different address on the set of data input lines during each of the sequential time periods.

4. The display device of claim 3, wherein during the addressing mode, the control circuit assigns a same address to every driver circuit in a same row, and assigns different addresses to each driver circuit in a same column.

5. The display device of claim 1, wherein the set of shared lines comprises:

a set of data input lines coupling the driver circuits in the respective columns, wherein the control circuit sends addressing signals on the set of data input lines during the addressing mode to assign respective addresses to the driver circuits in the respective columns such that all driver circuits within a column have a same address and all driver circuits in a row have different addresses;

a set of data output lines coupling the driver circuits in the respective rows, the set of data output lines to communicate the readback data to the control circuit in response to the readback commands.

6. The display device of claim 5, wherein the set of power lines comprises a set of power communication lines, wherein the set of power communication lines provide at least one of the driver control commands and the readback commands as digital data modulated on the supply voltages during the operational mode.

7. The display device of claim 5, wherein the set of data output lines comprise bidirectional lines, the bidirectional lines to provide at least one of the driver control commands and the readback commands.

8. The display device of claim 1, wherein the set of shared lines comprises:

a set of power communication lines coupling the driver circuits in the respective rows, the set of power communication lines to provide respective supply voltages to driver circuits in the respective rows, and to provide the driver control commands and the readback commands as digital data modulated on the supply voltages during an operational mode;

a set of bidirectional data lines coupling the driver circuits in the respective columns, wherein the set of bidirectional data lines communicate the addressing signals from the control circuit during the addressing mode to assign respective addresses to the driver circuits in the respective columns such that all driver circuits within a column have a same address and all driver circuits in a row have different addresses, and wherein the set of bidirectional data lines communicates the readback data to the control circuit in response to the readback commands during the operational mode.

9. The display device of claim 1, wherein the set of shared lines comprises:

a set of data input lines coupling the driver circuits in the respective rows, wherein the set of data input lines sequentially send row select signals from the control circuit during the addressing mode to select respective rows of the array of driver circuits for address assignment during sequential row select periods;

a set of bidirectional data lines coupling the driver circuits in the respective columns, the set of bidirectional data lines to sequentially send column select signals from the control circuit during each of the sequential row select periods of the addressing mode to select respective columns of the array of driver circuits for address assignment during sequential row-column select periods, and the set of bidirectional data lines to communicate the readback data to the control circuit in response to the readback commands during an operational mode;

a set of power communication lines coupling the driver circuits in the respective rows, the set of power lines to provide respective supply voltages to driver circuits in the respective rows, and the set of power communication lines to send address assignments to respective selected driver circuits during each of the row-column select periods of the addressing mode.

10. The display device of claim 9, wherein during the addressing mode, each of the driver circuits in the array of driver circuits is assigned a unique address.

11. The display device of claim 9, wherein the set of power communication lines provides at least one of the driver control commands and the readback commands as digital data modulated on the supply voltages during the operational mode.

12. The display device of claim 9, wherein the set of data input lines provide at least one of the driver control commands and the readback commands during the operational mode.

13. The display device of claim 1, wherein the set of shared lines comprises:

a set of data input lines coupling the driver circuits in the respective rows, wherein the set of data input lines sequentially send row select signals from the control circuit during an addressing mode to select respective rows of the array of driver circuits for address assignment during sequential row select periods;

a set of bidirectional data lines coupling the driver circuits in the respective columns, the set of bidirectional data lines to sequentially send column addressing signals from the control circuit during each of the sequential row select periods of the addressing mode to assign addresses to respective driver circuits, and the set of bidirectional data lines to communicate the readback data to the control circuit in response to the readback commands during an operational mode;

a set of power lines coupling the driver circuits in the respective rows, the set of power lines to provide respective supply voltages to driver circuits in the respective rows.

14. The display device of claim 13, wherein during the addressing mode, each of the driver circuits in the array of driver circuits is assigned a unique address.

15. The display device of claim 13, wherein the set of power lines comprises power communication lines to provide at least one of the driver control commands and the readback commands as digital data modulated on the supply voltages during the operational mode.

16. The display device of claim 13, wherein the set of data input lines provide at least one of the driver control commands and the readback commands during the operational mode.

17. The display device of claim 1, wherein each driver circuit and corresponding light emitting diode zone are stacked over a common substrate and integrated in a same package.

18. A method for operating a display device comprising:

in an addressing mode, assigning addresses to driver circuits in an array of driver circuits based on addressing signals sent by a control circuit on a set of shared lines, the set of shared lines including row lines coupling driver circuits in respective rows of the array of driver circuits and column lines coupling driver circuits in respective columns of the array of driver circuits;

in an operational mode, communicating, from the control circuit to the array of driver circuits distributed in a display area of the display device, driver control commands and readback commands on the set of shared lines, the driver control commands including an address of a targeted driver circuit;

controlling, by the targeted driver circuit in response to the driver control commands, driver currents through one or more light emitting diodes in a light emitting diode zone;

obtaining, from the control circuit, via the set of shared lines, readback data from the driver circuits in response to the readback commands; and

adjusting, by the control circuit, the driver control commands in response to the readback data.

19. The method of claim 18, wherein each driver circuit and corresponding light emitting diode zone are stacked over a common substrate and integrated in a same package.

20. A display device comprising:

light emitting means for generating light in response to respective driver currents;

driving means distributed in a display area of the display device, the driving means for

driving respective light emitting means with the respective driver circuits based on driver control commands and to generate readback data comprising sensed conditions in response to readback commands;

control means for generating the readback commands, obtaining the readback data in response to the readback commands, and generating the driver control signals based at least in part on the readback data; and

shared communication means for communicating the driver control commands and the readback commands from the control means to the driving means and to communicate the readback data from the driving means to the control means, the shared communication means including at least a first subset of shared communication means coupling driving means in respective rows and a second subset of the shared communication means coupling driving means in respective columns.