[go: up one dir, main page]

US20210202470A1 - Mosfet with integrated esd protection diode having anode electrode connection to trenched gates for increasing switch speed - Google Patents

Mosfet with integrated esd protection diode having anode electrode connection to trenched gates for increasing switch speed Download PDF

Info

Publication number
US20210202470A1
US20210202470A1 US16/731,114 US201916731114A US2021202470A1 US 20210202470 A1 US20210202470 A1 US 20210202470A1 US 201916731114 A US201916731114 A US 201916731114A US 2021202470 A1 US2021202470 A1 US 2021202470A1
Authority
US
United States
Prior art keywords
gate
source
type
metal
trenched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US16/731,114
Inventor
Fu-Yuan Hsieh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nami Mos Co Ltd
Original Assignee
Nami Mos Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nami Mos Co Ltd filed Critical Nami Mos Co Ltd
Priority to US16/731,114 priority Critical patent/US20210202470A1/en
Assigned to Nami MOS CO., LTD. reassignment Nami MOS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HSIEH, FU-YUAN
Priority to CN202010913672.7A priority patent/CN112038407A/en
Publication of US20210202470A1 publication Critical patent/US20210202470A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H01L27/0255—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L29/0696—
    • H01L29/41741—
    • H01L29/4236—
    • H01L29/7811—
    • H01L29/7813—
    • H01L29/866—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/112—Field plates comprising multiple field plate segments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/20—Breakdown diodes, e.g. avalanche diodes
    • H10D8/25—Zener diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/141—VDMOS having built-in components
    • H10D84/148—VDMOS having built-in components the built-in components being breakdown diodes, e.g. Zener diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/611—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes

Definitions

  • This invention relates generally to the cell structure, device configuration and layout of semiconductor power devices. More particularly, this invention relates to an improved cell structure and device configuration to manufacture a trench semiconductor power device with integrated ESD protection diode having anode electrode connection to trenched gates for increasing switch speed.
  • FIG. 1C is a top view of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device 100 which includes a gate metal pad 110 connected to a gate metal runner 125 disposed on the peripheral edges of the device 100 and a source metal pad 120 . There is a metal gap 115 opened between the source metal pad 110 and the gate metal pad 110 ′ and the gate metal runner 125 . Gate-Source ESD clamp diodes 130 are connected between the gate metal runner 125 and the source metal pad 120 .
  • FIG. 1C is a top view of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device 100 which includes a gate metal pad 110 connected to a gate metal runner 125 disposed on the peripheral edges of the device 100 and a source metal pad 120 . There is a metal gap 115 opened between the source metal pad 110 and the gate metal pad 110 ′ and the gate metal runner 125 . Gate-Source ESD clamp diodes 130 are connected between the gate metal runner 125
  • FIG. 1D is a top view of another MOSFET device 200 that includes a gate metal pad 212 connected to gate metal runners 213 and a source metal pad 211 with a metal gap 214 disposed between them.
  • the MOSFET 200 in FIG. 1D further comprises poly-silicon resistors 215 together with Gate-Source ESD clamp diodes 216 which are connected between the gate metal runner 213 and the source metal pad 211 .
  • there is another kind of Gate-Source ESD clamp diode 217 which is connected between the gate metal pad 212 and the source metal pad 211 . All the Gate-Source ESD clamp diodes in FIG. 1C and FIG.
  • Gate-Source ESD clamp diodes comprise multiple back to back Zener diodes with alternating n+ doped regions next to p+ doped regions, wherein the alternating n+ doped regions and p+ doped regions have a stripe structure which would have a leakage path along an edge of the Gate-Source ESD clamp diodes because the dry poly-silicon etch step in the manufacturing process would damage the edge of the Gate-Source ESD clamp diodes. Therefore, there are only two types of Gate-Source ESD clamp diodes in the prior art: a first type is formed between the gate metal pad and the source metal pad, and a second type is formed between the source metal pad and the gate metal runner. Especially for small-size devices, there is not much space budget for the Gate-Source ESD clamp diodes due to the size limitation of dies, which requires increasing the total perimeter of the Gate-Source ESD clamp diodes for ESD capability enhancement.
  • Gate-Source ESD clamp diodes for providing an ESD protection between a source electrode and a gate electrode of the trench semiconductor power device 300 : a first type Gate-Source ESD clamp diode (ESD 1 , as illustrated) connected between the gate metal pad 301 and the source metal pad 303 ; a second type Gate-Source ESD clamp diode (ESD 2 , as illustrated) connected between the gate metal pad 301 and the source metal runner 304 ; a third type Gate-Source ESD clamp diode (ESD 3 , as illustrated) connected between the gate metal runner 302 and the source metal pad 303 ; and a fourth type Gate-Source ESD clamp diode (ESD 4 , as illustrated) connected between the gate metal runner 302 and the source metal runner 304 .
  • ESD 1 Gate-Source ESD clamp diode
  • ESD 2 Gate-Source ESD clamp diode
  • ESD 3 Gate-Source ESD clamp diode
  • ESD 4 Gate-Source ESD clamp diode
  • the improved layout and device structure according to the present invention comprises two more types of Gate-Source ESD clamp diodes comparing to the prior arts as shown in FIGS. 1A-1D that have only two types of Gate-Source ESD clamp diodes, which increases the total perimeter of the Gate-Source ESD clamp diodes to enhance ESD capability especially for small devices.
  • gate metal runner surrounding active area as anode of ESD diode does not connecting to trench gate resulting in slow switching speed due to high gate resistance Rg, especially for P channel trench MOSFET.
  • a semiconductor power device integrated with Gate-Source ESD clamp diodes formed on a semiconductor silicon layer comprising a substrate of a first conductivity type: an epitaxial layer of the first conductivity type grown on the substrate, wherein the epitaxial layer having a lower doping concentration than the substrate; a plurality of transistor cells in an active area, and multiple back to back Zener diodes with alternating doped regions of a first conductivity type next to a second conductivity type in the Gate-Source ESD clamp diodes.
  • the trench semiconductor power device further comprises: a plurality of first type trenched gates surrounded by source regions of the first conductivity type encompassed in body regions of the second conductivity type; a plurality of trenched source-body contacts opened through the source regions and extending into the body regions, filled with a contact metal plug therein and connected to a front metal serving as a source metal pad.
  • the Gate-Source ESD clamp diodes further comprises: a gate metal pad connected to a first type gate metal runner having poly-silicon layer underneath as anode electrode of the gate-source ESD clamp diodes surrounding a peripheral region of the semiconductor power device; a first type Gate-Source ESD clamp diode connected between the gate metal pad and the source metal pad; a second type Gate-Source ESD clamp diode connected between the first type gate metal runner and the source metal pad;
  • the first type gate metal runner is extended into the active area and connected to the first type trench gates for gate resistance reduction.
  • the first type gate metal runner extended into active area connecting to the first type trench gate from the first type gate metal runner surrounding the peripheral region of power device.
  • the first type gate metal runner extended to active area and connected to the first type trench gates through at least one second type gate metal runner without having the undoped poly-silicon layer underneath.
  • each of the alternating doped regions of the Gate-Source ESD clamp diodes has a closed ring structure; the body regions are formed underneath the Gate-Source ESD clamp diodes, and are further extended between every two adjacent of second type trenched gates functioning as etch-buffer trenched gates, and the etch-buffer trenched gates are penetrating through the body regions and disposed right below trenched ESD contacts in the Gate-Source ESD clamp diodes, wherein the etch-buffer trenched gates have trench width greater than the trenched ESD contacts for prevention of gate-body shortage; there is no front metal covering a top surface of the contact metal plug in the trenched drain contact; multiple third type trenched gates having floating voltage in a termination area are comprised; the contact metal plug is a tungsten layer padded with a barrier metal layer of Ti/TiN or Co/TiN; the front metal is Al alloys overlying a resistance-reduction layer of Ti or Ti/TiN; the first type trench
  • FIG. 1A is a top view of a prior art for a MOSFET device.
  • FIG. 1B is a top view of a prior art for another MOSFET device.
  • FIG. 1C is a top view of a prior art for another MOSFET device.
  • FIG. 1D is a top view of a prior art for another MOSFET device.
  • FIG. 1E is a top view of a prior art for another MOSFET device.
  • FIG. 2A is a top view of a preferred embodiment for a trench semiconductor power device according to the present invention.
  • FIG. 2B is a top view of another preferred embodiment for showing the doped regions of ESD diodes on gate metal pad and peripheral poly silicon areas according to the present invention.
  • FIG. 2C is a top view of another preferred embodiment according to the present invention.
  • FIG. 2D is a top view of another preferred embodiment according to the present invention.
  • FIG. 3 is a top view of another preferred embodiment according to the present invention.
  • FIG. 4 is a top view of another preferred embodiment according to the present invention.
  • FIG. 5 is a top view of another preferred embodiment according to the present invention.
  • FIG. 6A is a cross-section view showing a preferred E to G cross section of FIG. 3 .
  • FIG. 6B is a cross-section view showing another preferred E to G cross section of FIG. 3 .
  • FIG. 7 is a cross-section view showing another preferred E to G cross section of FIG. 3 .
  • FIG. 8A is a cross-section view showing another preferred E to G cross section of FIG. 3 .
  • FIG. 8B is a cross-section view showing another preferred E to G cross section of FIG. 3 .
  • FIG. 9 is a cross-section view showing another preferred E to G cross section of FIG. 3
  • FIG. 2A Please refer to FIG. 2A for a preferred embodiment of this invention, wherein a trench semiconductor power device is shown integrated with Gate-Source ESD clamp diodes.
  • the trench semiconductor power device includes a gate metal pad 401 for gate wire bonding with a first type gate metal runner 402 having a poly-silicon layer underneath as anode electrode of ESD diode surrounding a peripheral region of the trench semiconductor power device, and a second type gate metal runner 403 without having the poly-silicon layer underneath connecting to trenched gates 407 , wherein the trenched gated 407 are for gate contacts, and the second type gate metal runner 403 is between two active areas from one side of anode electrode of ESD diode to opposite side of the anode electrode connecting to trench gates.
  • the trench semiconductor power device also includes a top source metal pad 404 on top active area and a bottom source metal pad 405 on bottom active area for source wire bonding with a source metal runner 406 surrounding a peripheral region of the gate metal pad 401 , wherein the bottom source metal pad 405 with the source metal runner 406 , the gate metal pad 401 with the first type gate metal runner 402 , the second type gate metal runner 403 with the trenched gates, and the top source metal pad 404 are composed of Al alloys as a front metal overlying a resistance-reduction layer of Ti or Ti/TiN.
  • the source metal pad is connected to a plurality of source regions and body regions surrounding a plurality of first type trenched gates underneath an active area while the source metal runner does not have the first type trenched gates underneath.
  • the gate metal pad 401 having a square or circular shape is for gate wire bonding, and the source metal pad is for source wire bonding.
  • Gate-Source ESD clamp diodes for providing an ESD protection between a source electrode and a gate electrode of the trench semiconductor power device: a first type Gate-Source ESD clamp diode connected between the gate metal pad and the bottom source metal pad; a second type Gate-Source ESD clamp diode connected between the source metal pad and the gate metal runner; a third type Gate-Source ESD clamp diode connected between the gate metal pad and the source metal runner; and a fourth type Gate-Source ESD clamp diode connected between the gate metal runner and the source metal runner. Therefore, the improved layout and device structure according to the present invention comprises anode electrode of the ESD clamp diodes connects with trench gates in active area, which results in gate resistance reduction.
  • FIG. 2B is a top view of device configuration of doped regions of ESD diodes on gate metal pad and peripheral poly silicon areas.
  • the Gate-Source ESD clamp diodes comprise multiple back to back Zener diodes with alternating n+ doped regions next to p+ doped regions formed under the gate metal pad 401 and the first type gate metal runner 402 of the trench semiconductor power device as shown in FIG. 2A , wherein the multiple doped regions have multiple n+ and p+ closed rings on a poly-silicon layer, that would not touch edges of the Gate-Source ESD clamp diodes, therefore, the improved layout and device structure according to the present invention would not have the leakage path that exists in the prior art.
  • the Gate-Source ESD clamp diodes further comprise trenched ESD contacts filled with a contact metal plug and extending into the n+ doped regions on two sides of each of the Gate-Source ESD clamp diodes for an N-channel trench semiconductor power device.
  • FIG. 2C Please refer to FIG. 2C for another preferred embodiment of this invention, which is similar to that shown in FIG. 2A , except that second type gate metal runner disclosed in this invention extended from one side of the anode electrode into active area connecting to trenched gates.
  • FIG. 2D for another preferred embodiment of this invention, which is similar to that shown in FIG. 2A , except that the second type gate metal runner disclosed in this invention extended from two sides of the anode electrode of ESD diode into active area connecting to trenched gates.
  • FIG. 3 is a top view of another preferred embodiment for a trench semiconductor power device according to the present invention.
  • the gate metal pad connects to trenched gates
  • the first type gate metal runner as the anode electrode of ESD diode surrounding active area also connects to trenched gates on device corners and/or between device corners.
  • FIG. 4 is a top view of another preferred embodiment according to the present invention, which is similar as the structure disclosed in FIG. 2A , except that the structure in this invention has no source metal runners near gate metal pad.
  • FIG. 5 is a top view of another preferred embodiment according to the present invention, which is similar as the structure disclosed in FIG. 2C , except that the structure in this invention has no source metal runners nearby gate metal pad. All of the above inventions significantly reduce Rg.
  • FIG. 6A is an E-F-G cross-section view of FIG. 3 , which is comprises of single trench gate MOSFET (N channel) with trenched termination.
  • the structure is formed in a semiconductor silicon layer which can be implemented by comprising an N epitaxial layer 611 above a heavily doped N+ substrate 612 .
  • a plurality of trenched gates 614 , 642 and 671 are formed spaced apart by P body regions 615 and extending into the N epitaxial layer 611 .
  • a gate-source ESD clamp diode for providing an ESD protection comprises multiple back to back Zener diodes with alternating n+ doped regions 646 next to p+ doped regions 647 , and further comprises trenched ESD contacts 648 - 1 filled with the contact metal plugs 648 - 2 , for example, a tungsten layer padded by a barrier metal layer of Ti/TiN or Co/TiN or Ta/TIN, is implemented through a contact interlayer 621 , extending into the n+ regions 646 of the Gate-Source ESD clamp diode.
  • the trenched ESD contact 648 - 1 of the Gate-Source ESD clamp diode is connected to the first type gate metal runner 622 .
  • etch-buffer trenched gate 642 which serves as the buffer layer for prevention of gate-body shortage.
  • a trenched body contact 639 filled with the contact metal plug 640 which are the same as the contact metal plug 648 - 2 is implemented through the contact interlayer 621 and extending into the etch-buffer trenched gate 614 to connect the trenched gate 614 to the first type gate metal runner 622 onto the contact interlayer 621 .
  • a termination area comprises a plurality of multiple third type trenched gates 671 being spaced apart by the P body regions 615 , wherein the multiple third type trenched gates 671 having a same structure as the first type trenched gates 642 have floating voltage to function as trenched floating rings for the termination area.
  • FIG. 6B another E-F-G cross-section view of FIG. 3 , which is comprised of single trench gate MOSFET with multiple P body floating rings.
  • the invention disclosed in FIG. 6B is same as that in FIG. 6A , except for the termination area: P body-dopant regions 654 in the N epitaxial layer 611 and a trenched drain contact 655 filled with the contact metal plug 656 penetrating through the contact interlayer 621 , an n+ source-dopant region 657 and extending into the N epitaxial layer 611 with the p+ ohmic contact doped region 623 surrounding at least its bottom, wherein the n+ source-dopant region 657 can reduce the contact resistance between the N epitaxial layer 611 and the contact metal plug 656 filled in the trenched drain contact 655 , wherein the trenched drain contact 655 is finally connected to a drain region in the N epitaxial layer 611 .
  • FIG. 7 for another E-F-G cross-section view of FIG. 3 , which is comprises of shielded gate trench MOSFET with trench filed plate as termination.
  • the structure is quite similar to that disclosed in FIG. 6A , except for dual electrodes comprising a gate electrode 761 and a shielded gate electrode 762 in trenches 714 and the trench field plates 771 in termination.
  • the first type gate metal runner is extended into active area and connected to the gate electrode 761 of the first type trenched gates.
  • FIG. 8A for another E-F-G cross-section view of FIG. 3 , which is comprised of single trench gate MOSFET (P channel) with trenched termination.
  • the structure is same to that illustrated in FIG. 6A , except that the doping type in substrate 812 , epitaxy layer 811 , regions 815 , 846 and 847 is opposite to that disclosed in FIG. 6A .
  • FIG. 8B for another E-F-G cross-section view of FIG. 3 , which comprises a single trench gate MOSFET (P channel) with multiple P body floating rings.
  • the structure is same to that illustrated in FIG. 6B , except that the doping type in substrate 812 , epitaxy layer 811 , regions 815 , 823 , 846 , 847 , 854 and 857 is just opposite to that disclosed in FIG. 6B .
  • FIG. 9 for another E-F-G cross-section view of FIG. 3 , which comprises a shielded gate trench MOSFET (P channel) with trench filed plate as termination.
  • the structure is same to that illustrated in FIG. 7 , except that the doping type in substrate 912 , epitaxy layer 911 , regions 915 , 946 and 947 is just opposite to that disclosed in FIG. 7 .
  • the semiconductor power device can also be formed as a trench IGBT.
  • the heavily doped N+ substrate should be replaced by an N+ buffer layer extending over a heavily doped P+ substrate.
  • the terminology, such as “source”, “body”, “drain” should be accordingly replaced by “emitter”, “base”, “collector”.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A trench semiconductor power device integrated with ESD clamp diodes for optimization of total perimeter of the ESD clamp diodes, wherein the ESD clamp diodes comprise multiple back to back Zener diodes with alternating doped regions of a first conductivity type next to a second conductivity type, wherein anode electrode of the ESD clamp diodes connects with trenched gates in active area for gate resistance reduction.

Description

    FIELD OF THE INVENTION
  • This invention relates generally to the cell structure, device configuration and layout of semiconductor power devices. More particularly, this invention relates to an improved cell structure and device configuration to manufacture a trench semiconductor power device with integrated ESD protection diode having anode electrode connection to trenched gates for increasing switch speed.
    • BACKGROUND OF THE INVENTION
  • Conventional layouts and device structures for manufacturing a trench semiconductor power device integrated with Gate-Source ESD clamp diodes for providing an ESD protection still have a limitation. Prior arts disclosed in U.S. Pat. No. 8,053,808 (as shown in FIG. 1A and FIG. 1B) only has one kind ESD diode region between gate metal pad and source metal pad. For small devices with high ESD rating, there is no much space budget, requiring increasing total peripheral length of the ESD diodes on gate metal pad for ESD capability enhancement.
  • To improve the space limitation, another two prior arts also disclosed in above U.S. Pat No. as shown in FIGS. 1C and 1D. FIG. 1C is a top view of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device 100 which includes a gate metal pad 110 connected to a gate metal runner 125 disposed on the peripheral edges of the device 100 and a source metal pad 120. There is a metal gap 115 opened between the source metal pad 110 and the gate metal pad 110′ and the gate metal runner 125. Gate-Source ESD clamp diodes 130 are connected between the gate metal runner 125 and the source metal pad 120. FIG. 1D is a top view of another MOSFET device 200 that includes a gate metal pad 212 connected to gate metal runners 213 and a source metal pad 211 with a metal gap 214 disposed between them. Unlike the MOSFET device 100 in FIG. 1C, the MOSFET 200 in FIG. 1D further comprises poly-silicon resistors 215 together with Gate-Source ESD clamp diodes 216 which are connected between the gate metal runner 213 and the source metal pad 211. And furthermore, in FIG. 1D, there is another kind of Gate-Source ESD clamp diode 217 which is connected between the gate metal pad 212 and the source metal pad 211. All the Gate-Source ESD clamp diodes in FIG. 1C and FIG. 1D comprise multiple back to back Zener diodes with alternating n+ doped regions next to p+ doped regions, wherein the alternating n+ doped regions and p+ doped regions have a stripe structure which would have a leakage path along an edge of the Gate-Source ESD clamp diodes because the dry poly-silicon etch step in the manufacturing process would damage the edge of the Gate-Source ESD clamp diodes. Therefore, there are only two types of Gate-Source ESD clamp diodes in the prior art: a first type is formed between the gate metal pad and the source metal pad, and a second type is formed between the source metal pad and the gate metal runner. Especially for small-size devices, there is not much space budget for the Gate-Source ESD clamp diodes due to the size limitation of dies, which requires increasing the total perimeter of the Gate-Source ESD clamp diodes for ESD capability enhancement.
  • Please refer to FIG. 1E for an improved layout disclosed in U.S. Pat. No. 8,466,514. There are four types of Gate-Source ESD clamp diodes for providing an ESD protection between a source electrode and a gate electrode of the trench semiconductor power device 300: a first type Gate-Source ESD clamp diode (ESD1, as illustrated) connected between the gate metal pad 301 and the source metal pad 303; a second type Gate-Source ESD clamp diode (ESD2, as illustrated) connected between the gate metal pad 301 and the source metal runner 304; a third type Gate-Source ESD clamp diode (ESD3, as illustrated) connected between the gate metal runner 302 and the source metal pad 303; and a fourth type Gate-Source ESD clamp diode (ESD4, as illustrated) connected between the gate metal runner 302 and the source metal runner 304. Therefore, the improved layout and device structure according to the present invention comprises two more types of Gate-Source ESD clamp diodes comparing to the prior arts as shown in FIGS. 1A-1D that have only two types of Gate-Source ESD clamp diodes, which increases the total perimeter of the Gate-Source ESD clamp diodes to enhance ESD capability especially for small devices. However, gate metal runner surrounding active area as anode of ESD diode does not connecting to trench gate resulting in slow switching speed due to high gate resistance Rg, especially for P channel trench MOSFET.
  • Therefore, there is still a need in the art of the semiconductor power device integrated with Gate-Source ESD clamp diodes, to provide a novel cell structure, device configuration and layout that would further optimize total perimeter of the Gate-Source ESD clamp diodes for ESD capability enhancement, reduce the gate resistance Rg and increase the switching speed without sacrificing other performances and improve other characteristics of the semiconductor power device.
    • SUMMARY OF THE INVENTION
  • It is therefore an aspect of the present invention to provide a semiconductor power device so that the total perimeter of the Gate-Source ESD clamp diodes is increased for ESD capability enhancement without sacrificing other performances of the semiconductor power device. According to the present invention, there is provided a semiconductor power device integrated with Gate-Source ESD clamp diodes formed on a semiconductor silicon layer, comprising a substrate of a first conductivity type: an epitaxial layer of the first conductivity type grown on the substrate, wherein the epitaxial layer having a lower doping concentration than the substrate; a plurality of transistor cells in an active area, and multiple back to back Zener diodes with alternating doped regions of a first conductivity type next to a second conductivity type in the Gate-Source ESD clamp diodes. The trench semiconductor power device further comprises: a plurality of first type trenched gates surrounded by source regions of the first conductivity type encompassed in body regions of the second conductivity type; a plurality of trenched source-body contacts opened through the source regions and extending into the body regions, filled with a contact metal plug therein and connected to a front metal serving as a source metal pad. The Gate-Source ESD clamp diodes further comprises: a gate metal pad connected to a first type gate metal runner having poly-silicon layer underneath as anode electrode of the gate-source ESD clamp diodes surrounding a peripheral region of the semiconductor power device; a first type Gate-Source ESD clamp diode connected between the gate metal pad and the source metal pad; a second type Gate-Source ESD clamp diode connected between the first type gate metal runner and the source metal pad; The first type gate metal runner is extended into the active area and connected to the first type trench gates for gate resistance reduction. The first type gate metal runner extended into active area connecting to the first type trench gate from the first type gate metal runner surrounding the peripheral region of power device. The first type gate metal runner extended to active area and connected to the first type trench gates through at least one second type gate metal runner without having the undoped poly-silicon layer underneath.
  • According to another aspect, the invention also features a semiconductor power device comprises: source metal pad connected to at least one source metal runner disposed between the gate metal pad and the gate metal runner, and separated from the gate metal pad and the gate metal runner by a metal gap, wherein the source metal runner does not have the first type trenched gates underneath; a third type Gate-Source ESD clamp diode connected between the gate metal pad and the source metal runner; and a fourth type Gate-Source ESD clamp diode connected between the source metal runner and the gate metal runner.
  • According to another aspect, the invention also features a semiconductor power device comprises: at least one body-dopant region of the second conductivity type with floating voltage in a termination area, wherein the body-dopant region is formed simultaneously as the body regions; a source-dopant region of the first conductivity type formed near an edge of the semiconductor power device, wherein the source-dopant region is formed simultaneously as the source regions; a trenched drain contact filled with the contact metal plug and penetrating through the source-dopant region, and further extended into the semiconductor silicon layer; an ohmic contact doped region of the second conductivity type surrounding at least bottom of the trenched drain contact underneath the source-dopant region; and the ohmic contact doped region has a higher doping concentration than the body regions.
  • Some preferred embodiments include one or more detail features as followed: each of the alternating doped regions of the Gate-Source ESD clamp diodes has a closed ring structure; the body regions are formed underneath the Gate-Source ESD clamp diodes, and are further extended between every two adjacent of second type trenched gates functioning as etch-buffer trenched gates, and the etch-buffer trenched gates are penetrating through the body regions and disposed right below trenched ESD contacts in the Gate-Source ESD clamp diodes, wherein the etch-buffer trenched gates have trench width greater than the trenched ESD contacts for prevention of gate-body shortage; there is no front metal covering a top surface of the contact metal plug in the trenched drain contact; multiple third type trenched gates having floating voltage in a termination area are comprised; the contact metal plug is a tungsten layer padded with a barrier metal layer of Ti/TiN or Co/TiN; the front metal is Al alloys overlying a resistance-reduction layer of Ti or Ti/TiN; the first type trench gates are single trench gate; the first type trench gates are shielded trenched gate having dual gate electrodes comprising a gate electrode disposed in the upper portion and a shielded electrode disposed in the lower potion, wherein the gate electrode and the shielded electrode insulated from each other by an inter-electrode insulation layer; the first conductivity type is N type and second conductivity type is P type; the first conductivity type is P type and second conductivity is N type.
  • These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment, which is illustrated in the various drawing figures.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:
  • FIG. 1A is a top view of a prior art for a MOSFET device.
  • FIG. 1B is a top view of a prior art for another MOSFET device.
  • FIG. 1C is a top view of a prior art for another MOSFET device.
  • FIG. 1D is a top view of a prior art for another MOSFET device.
  • FIG. 1E is a top view of a prior art for another MOSFET device.
  • FIG. 2A is a top view of a preferred embodiment for a trench semiconductor power device according to the present invention.
  • FIG. 2B is a top view of another preferred embodiment for showing the doped regions of ESD diodes on gate metal pad and peripheral poly silicon areas according to the present invention.
  • FIG. 2C is a top view of another preferred embodiment according to the present invention.
  • FIG. 2D is a top view of another preferred embodiment according to the present invention.
  • FIG. 3 is a top view of another preferred embodiment according to the present invention.
  • FIG. 4 is a top view of another preferred embodiment according to the present invention.
  • FIG. 5 is a top view of another preferred embodiment according to the present invention
  • FIG. 6A is a cross-section view showing a preferred E to G cross section of FIG. 3.
  • FIG. 6B is a cross-section view showing another preferred E to G cross section of FIG. 3.
  • FIG. 7 is a cross-section view showing another preferred E to G cross section of FIG. 3.
  • FIG. 8A is a cross-section view showing another preferred E to G cross section of FIG. 3.
  • FIG. 8B is a cross-section view showing another preferred E to G cross section of FIG. 3.
  • FIG. 9 is a cross-section view showing another preferred E to G cross section of FIG. 3
    • DETAILED DESCRIPTION OF THE EMBODIMENTS
  • In the following Detailed Description, reference is made to the accompanying drawings, which forms a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top”, “bottom”, “front”, “back”, etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be make without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise.
  • Please refer to FIG. 2A for a preferred embodiment of this invention, wherein a trench semiconductor power device is shown integrated with Gate-Source ESD clamp diodes. The trench semiconductor power device includes a gate metal pad 401 for gate wire bonding with a first type gate metal runner 402 having a poly-silicon layer underneath as anode electrode of ESD diode surrounding a peripheral region of the trench semiconductor power device, and a second type gate metal runner 403 without having the poly-silicon layer underneath connecting to trenched gates 407, wherein the trenched gated 407 are for gate contacts, and the second type gate metal runner 403 is between two active areas from one side of anode electrode of ESD diode to opposite side of the anode electrode connecting to trench gates. The trench semiconductor power device also includes a top source metal pad 404 on top active area and a bottom source metal pad 405 on bottom active area for source wire bonding with a source metal runner 406 surrounding a peripheral region of the gate metal pad 401, wherein the bottom source metal pad 405 with the source metal runner 406, the gate metal pad 401 with the first type gate metal runner 402, the second type gate metal runner 403 with the trenched gates, and the top source metal pad 404 are composed of Al alloys as a front metal overlying a resistance-reduction layer of Ti or Ti/TiN. The source metal pad is connected to a plurality of source regions and body regions surrounding a plurality of first type trenched gates underneath an active area while the source metal runner does not have the first type trenched gates underneath. The gate metal pad 401 having a square or circular shape is for gate wire bonding, and the source metal pad is for source wire bonding. There are four types of Gate-Source ESD clamp diodes for providing an ESD protection between a source electrode and a gate electrode of the trench semiconductor power device: a first type Gate-Source ESD clamp diode connected between the gate metal pad and the bottom source metal pad; a second type Gate-Source ESD clamp diode connected between the source metal pad and the gate metal runner; a third type Gate-Source ESD clamp diode connected between the gate metal pad and the source metal runner; and a fourth type Gate-Source ESD clamp diode connected between the gate metal runner and the source metal runner. Therefore, the improved layout and device structure according to the present invention comprises anode electrode of the ESD clamp diodes connects with trench gates in active area, which results in gate resistance reduction.
  • FIG. 2B is a top view of device configuration of doped regions of ESD diodes on gate metal pad and peripheral poly silicon areas. The Gate-Source ESD clamp diodes comprise multiple back to back Zener diodes with alternating n+ doped regions next to p+ doped regions formed under the gate metal pad 401 and the first type gate metal runner 402 of the trench semiconductor power device as shown in FIG. 2A, wherein the multiple doped regions have multiple n+ and p+ closed rings on a poly-silicon layer, that would not touch edges of the Gate-Source ESD clamp diodes, therefore, the improved layout and device structure according to the present invention would not have the leakage path that exists in the prior art. The Gate-Source ESD clamp diodes further comprise trenched ESD contacts filled with a contact metal plug and extending into the n+ doped regions on two sides of each of the Gate-Source ESD clamp diodes for an N-channel trench semiconductor power device.
  • Please refer to FIG. 2C for another preferred embodiment of this invention, which is similar to that shown in FIG. 2A, except that second type gate metal runner disclosed in this invention extended from one side of the anode electrode into active area connecting to trenched gates.
  • Please refer to FIG. 2D for another preferred embodiment of this invention, which is similar to that shown in FIG. 2A, except that the second type gate metal runner disclosed in this invention extended from two sides of the anode electrode of ESD diode into active area connecting to trenched gates.
  • FIG. 3 is a top view of another preferred embodiment for a trench semiconductor power device according to the present invention. Besides the gate metal pad connects to trenched gates, the first type gate metal runner as the anode electrode of ESD diode surrounding active area also connects to trenched gates on device corners and/or between device corners.
  • FIG. 4 is a top view of another preferred embodiment according to the present invention, which is similar as the structure disclosed in FIG. 2A, except that the structure in this invention has no source metal runners near gate metal pad.
  • FIG. 5 is a top view of another preferred embodiment according to the present invention, which is similar as the structure disclosed in FIG. 2C, except that the structure in this invention has no source metal runners nearby gate metal pad. All of the above inventions significantly reduce Rg.
  • Please refer to FIG. 6A for an E-F-G cross-section view of FIG. 3, which is comprises of single trench gate MOSFET (N channel) with trenched termination. The structure is formed in a semiconductor silicon layer which can be implemented by comprising an N epitaxial layer 611 above a heavily doped N+ substrate 612. A plurality of trenched gates 614, 642 and 671 are formed spaced apart by P body regions 615 and extending into the N epitaxial layer 611. A gate-source ESD clamp diode for providing an ESD protection comprises multiple back to back Zener diodes with alternating n+ doped regions 646 next to p+ doped regions 647, and further comprises trenched ESD contacts 648-1 filled with the contact metal plugs 648-2, for example, a tungsten layer padded by a barrier metal layer of Ti/TiN or Co/TiN or Ta/TIN, is implemented through a contact interlayer 621, extending into the n+ regions 646 of the Gate-Source ESD clamp diode. The trenched ESD contact 648-1 of the Gate-Source ESD clamp diode is connected to the first type gate metal runner 622. Right below the trenched ESD contacts 648-1, there is the etch-buffer trenched gate 642 which serves as the buffer layer for prevention of gate-body shortage. A trenched body contact 639 filled with the contact metal plug 640, which are the same as the contact metal plug 648-2 is implemented through the contact interlayer 621 and extending into the etch-buffer trenched gate 614 to connect the trenched gate 614 to the first type gate metal runner 622 onto the contact interlayer 621. A termination area comprises a plurality of multiple third type trenched gates 671 being spaced apart by the P body regions 615, wherein the multiple third type trenched gates 671 having a same structure as the first type trenched gates 642 have floating voltage to function as trenched floating rings for the termination area.
  • Please refer to FIG. 6B for another E-F-G cross-section view of FIG. 3, which is comprised of single trench gate MOSFET with multiple P body floating rings. The invention disclosed in FIG. 6B is same as that in FIG. 6A, except for the termination area: P body-dopant regions 654 in the N epitaxial layer 611 and a trenched drain contact 655 filled with the contact metal plug 656 penetrating through the contact interlayer 621, an n+ source-dopant region 657 and extending into the N epitaxial layer 611 with the p+ ohmic contact doped region 623 surrounding at least its bottom, wherein the n+ source-dopant region 657 can reduce the contact resistance between the N epitaxial layer 611 and the contact metal plug 656 filled in the trenched drain contact 655, wherein the trenched drain contact 655 is finally connected to a drain region in the N epitaxial layer 611. There is no front metal covering on top surface of the contact metal plug 656 in the trenched drain contact 655.
  • Please refer to FIG. 7 for another E-F-G cross-section view of FIG. 3, which is comprises of shielded gate trench MOSFET with trench filed plate as termination. The structure is quite similar to that disclosed in FIG. 6A, except for dual electrodes comprising a gate electrode 761 and a shielded gate electrode 762 in trenches 714 and the trench field plates 771 in termination. The first type gate metal runner is extended into active area and connected to the gate electrode 761 of the first type trenched gates.
  • Please refer to FIG. 8A for another E-F-G cross-section view of FIG. 3, which is comprised of single trench gate MOSFET (P channel) with trenched termination. The structure is same to that illustrated in FIG. 6A, except that the doping type in substrate 812, epitaxy layer 811, regions 815, 846 and 847 is opposite to that disclosed in FIG. 6A.
  • Please refer to FIG. 8B for another E-F-G cross-section view of FIG. 3, which comprises a single trench gate MOSFET (P channel) with multiple P body floating rings. The structure is same to that illustrated in FIG. 6B, except that the doping type in substrate 812, epitaxy layer 811, regions 815, 823, 846, 847, 854 and 857 is just opposite to that disclosed in FIG. 6B.
  • Please refer to FIG. 9 for another E-F-G cross-section view of FIG. 3, which comprises a shielded gate trench MOSFET (P channel) with trench filed plate as termination. The structure is same to that illustrated in FIG. 7, except that the doping type in substrate 912, epitaxy layer 911, regions 915, 946 and 947 is just opposite to that disclosed in FIG. 7.
  • As an alternative to the exemplary embodiment illustrated and described above, the semiconductor power device can also be formed as a trench IGBT. In the case of a trench IGBT, the heavily doped N+ substrate should be replaced by an N+ buffer layer extending over a heavily doped P+ substrate. In this regards, the terminology, such as “source”, “body”, “drain” should be accordingly replaced by “emitter”, “base”, “collector”.
  • Although the present invention has been described in terms of the presently preferred embodiments, it is to be understood that such disclosure is not to be interpreted as limiting. Various alternations and modifications will no doubt become apparent to those skilled in the art after reading the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alternations and modifications as fall within the true spirit and scope of the invention.

Claims (15)

What is claimed is:
1. A semiconductor power device integrated with Gate-Source ESD clamp diodes comprising a substrate of a first conductivity type;
an epitaxial layer of said first conductivity type grown on said substrate, wherein said epitaxial layer having a lower doping concentration than said substrate;
a plurality of transistor cells in an active area, and multiple back to back Zener diodes with alternating doped regions of a first conductivity type next to a second conductivity type in said Gate-Source ESD clamp diodes formed on a poly-silicon layer, wherein:
said trench semiconductor power device further comprises:
a plurality of first type trenched gates surrounded by source regions of said first conductivity type encompassed in body regions of said second conductivity type;
a plurality of trenched source-body contacts opened through said source regions and extending into said body regions, filled with a contact metal plug therein and connected to a front metal serving as a source metal pad;
said Gate-Source ESD clamp diodes further comprises:
a gate metal pad connected to first type gate metal runner with said poly-silicon layer underneath as anode electrode of said gate-source ESD clamp diodes surrounding a peripheral region of said semiconductor power device;
a first type Gate-Source ESD clamp diode connected between said gate metal pad and said source metal pad;
a second type Gate-Source ESD clamp diode connected between said source metal pad and said first type gate metal runner; and
said first type gate metal runner is extended into said active area and connected to said first type trench gates for gate resistance reduction.
2. The semiconductor power devices of claim 1, wherein said first type gate metal runner extended into active area connecting to said first type trenched gates from any portions of said first type gate metal runner surrounding said peripheral region of power device.
3. The semiconductor power devices of claim 1, wherein said first type gate runner extended to active area and connected to said first type trenched gates through at least one second type gate metal runner without having said poly-silicon layer underneath.
4. The semiconductor power device of claim 1 further comprising:
said source metal pad connected to at least one source metal runner disposed between said gate metal pad and said gate metal runner, and separated from said gate metal pad and said gate metal runner by a metal gap, wherein said source metal runner does not have said first type trenched gates underneath;
a third type Gate-Source ESD clamp diode connected between said gate metal pad and said source metal runner; and
a fourth type Gate-Source ESD clamp diode connected between said source metal runner and said gate metal runner.
5. The semiconductor power device of claim 1, wherein each of said alternating doped regions of said Gate-Source ESD clamp diodes has a closed ring structure.
6. The semiconductor power device of claim 1, wherein said body regions are formed underneath said Gate-Source ESD clamp diodes, and are further extended between every two adjacent of second type trenched gates functioning as etch-buffer trenched gates, and said etch-buffer trenched gates are penetrating through said body regions and disposed right below trenched ESD contacts in said Gate-Source ESD clamp diodes, wherein said etch-buffer trenched gates have trench width greater than said trenched ESD contacts for prevention of gate-body shortage.
7. The semiconductor power device of claim 1 further comprising:
at least one body-dopant region of said second conductivity type with floating voltage in a termination area, wherein said body-dopant region is formed simultaneously as said body regions;
a source-dopant region of said first conductivity type formed near an edge of said semiconductor power device, wherein said source-dopant region is formed simultaneously as said source regions;
a trenched drain contact filled with said contact metal plug and penetrating through said source-dopant region, and further extended into said semiconductor silicon layer;
an ohmic contact doped region of said second conductivity type surrounding at least bottom of said trenched drain contact underneath said source-dopant region; and
said ohmic contact doped region has a higher doping concentration than said body regions.
8. The semiconductor power device of claim 8, wherein there is no front metal covering a top surface of said contact metal plug in said trenched drain contact.
9. The semiconductor power device of claim 1 further comprising multiple third type trenched gates having floating voltage in a termination area.
10. The trench semiconductor power device of claim 1, wherein said contact metal plug is a tungsten layer padded with a barrier metal layer of Ti/TiN or Co/TiN.
11. The trench semiconductor power device of claim 1, wherein said front metal is Al alloys overlying a resistance-reduction layer of Ti or Ti/TN.
13. The power semiconductor device of claim 1, wherein said first type trench gates are single trench gate.
14. The power semiconductor device of claim 1, wherein said first type trench gates are shielded trenched gate having dual gate electrodes comprising a gate electrode disposed in the upper portion and a shielded gate electrode disposed in the lower potion, wherein said gate electrode and said shielded gate electrode insulated from each other by an inter-electrode insulation layer; and said first type gate metal runner is extended into said active area and connected to said gate electrode of said first type trenched gates.
15. The power semiconductor device of claim 1, wherein said first conductivity type is N type and second conductivity type is P type.
16. The power semiconductor device of claim 1, wherein said first conductivity type is P type and second conductivity is N type.
US16/731,114 2019-12-31 2019-12-31 Mosfet with integrated esd protection diode having anode electrode connection to trenched gates for increasing switch speed Abandoned US20210202470A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US16/731,114 US20210202470A1 (en) 2019-12-31 2019-12-31 Mosfet with integrated esd protection diode having anode electrode connection to trenched gates for increasing switch speed
CN202010913672.7A CN112038407A (en) 2019-12-31 2020-09-03 A semiconductor power device with integrated electrostatic discharge protection diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US16/731,114 US20210202470A1 (en) 2019-12-31 2019-12-31 Mosfet with integrated esd protection diode having anode electrode connection to trenched gates for increasing switch speed

Publications (1)

Publication Number Publication Date
US20210202470A1 true US20210202470A1 (en) 2021-07-01

Family

ID=73591370

Family Applications (1)

Application Number Title Priority Date Filing Date
US16/731,114 Abandoned US20210202470A1 (en) 2019-12-31 2019-12-31 Mosfet with integrated esd protection diode having anode electrode connection to trenched gates for increasing switch speed

Country Status (2)

Country Link
US (1) US20210202470A1 (en)
CN (1) CN112038407A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11410990B1 (en) * 2020-08-25 2022-08-09 Semiq Incorporated Silicon carbide MOSFET with optional asymmetric gate clamp
WO2023002767A1 (en) * 2021-07-21 2023-01-26 ローム株式会社 Semiconductor device
US20240234590A1 (en) * 2022-03-31 2024-07-11 Leap Semiconductor Corp. METHOD OF MANUFACTURING MERGED PiN SCHOTTKY (MPS) DIODE
JP7599061B1 (en) * 2023-08-25 2024-12-12 ヌヴォトンテクノロジージャパン株式会社 Semiconductor Device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7183610B2 (en) * 2004-04-30 2007-02-27 Siliconix Incorporated Super trench MOSFET including buried source electrode and method of fabricating the same
JP2009141007A (en) * 2007-12-04 2009-06-25 Toyota Industries Corp Semiconductor device
CN102244095B (en) * 2010-05-11 2013-05-22 力士科技股份有限公司 A power semiconductor device
US8779510B2 (en) * 2010-06-01 2014-07-15 Alpha And Omega Semiconductor Incorporated Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts
US8466514B2 (en) * 2011-10-17 2013-06-18 Force Mos Technology Co., Ltd. Semiconductor power device integrated with improved gate source ESD clamp diodes
US10361276B1 (en) * 2018-03-17 2019-07-23 Littelfuse, Inc. Embedded field plate field effect transistor
US10930774B2 (en) * 2019-07-16 2021-02-23 Nami MOS CO., LTD. Shielded gate trench MOSFETs with floating trenched gates and channel stop trenched gates in termination

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11410990B1 (en) * 2020-08-25 2022-08-09 Semiq Incorporated Silicon carbide MOSFET with optional asymmetric gate clamp
US20220336444A1 (en) * 2020-08-25 2022-10-20 Semiq Incorporated Silicon Carbide MOSFET With Optional Asymmetric Gate Clamp
US11756954B2 (en) * 2020-08-25 2023-09-12 Semiq Incorporated Silicon carbide MOSFET with optional asymmetric gate clamp
WO2023002767A1 (en) * 2021-07-21 2023-01-26 ローム株式会社 Semiconductor device
US20240234590A1 (en) * 2022-03-31 2024-07-11 Leap Semiconductor Corp. METHOD OF MANUFACTURING MERGED PiN SCHOTTKY (MPS) DIODE
US12191403B2 (en) * 2022-03-31 2025-01-07 Leap Semiconductor Corp. Method of manufacturing merged PiN Schottky (MPS) diode
JP7599061B1 (en) * 2023-08-25 2024-12-12 ヌヴォトンテクノロジージャパン株式会社 Semiconductor Device

Also Published As

Publication number Publication date
CN112038407A (en) 2020-12-04

Similar Documents

Publication Publication Date Title
US8466514B2 (en) Semiconductor power device integrated with improved gate source ESD clamp diodes
US10930774B2 (en) Shielded gate trench MOSFETs with floating trenched gates and channel stop trenched gates in termination
US11114558B2 (en) Shielded gate trench MOSFET integrated with super barrier rectifier
US8164162B2 (en) Power semiconductor devices integrated with clamp diodes sharing same gate metal pad
US8072000B2 (en) Avalanche capability improvement in power semiconductor devices having dummy cells around edge of active area
US6600182B2 (en) High current field-effect transistor
US8519477B2 (en) Trench MOSFET with trenched floating gates and trenched channel stop gates in termination
US8564053B2 (en) Trench MOSFET with trenched floating gates in termination
US20120037954A1 (en) Equal Potential Ring Structures of Power Semiconductor with Trenched Contact
US20120175700A1 (en) Trench mos rectifier
US11004969B2 (en) Trench MOSFETs having dummy cells for avalanche capability improvement
US11600725B2 (en) Trench MOSFETs integrated with clamped diodes having trench field plate termination to avoid breakdown voltage degradation
US8816348B2 (en) Shielded gate MOSFET-Schottky rectifier-diode integrated circuits with trenched contact structures
US20210202470A1 (en) Mosfet with integrated esd protection diode having anode electrode connection to trenched gates for increasing switch speed
US20100006927A1 (en) Charge Balance Techniques for Power Devices
US8564052B2 (en) Trench MOSFET with trenched floating gates in termination
US20230010328A1 (en) Shielded gate trench mosfet with multiple stepped epitaxial structures
US11444164B2 (en) Shielded gate trench MOSFET having improved specific on-resistance structures
US20140103426A1 (en) Trench metal oxide semiconductor field effect transistor with multiple trenched source-body contacts for reducing gate charge
US6548860B1 (en) DMOS transistor structure having improved performance
US12176397B2 (en) Super barrier rectifier with shielded gate electrode and multiple stepped epitaxial structure
JP2010232335A (en) Insulated gate bipolar transistor
US8487372B1 (en) Trench MOSFET layout with trenched floating gates and trenched channel stop gates in termination
US20240363698A1 (en) Sic shielded gate trench mosfet with improved performance
US20240186265A1 (en) Shielded gate trench mosfets with hexagonal deep trench layouts and multiple epitaxial layers

Legal Events

Date Code Title Description
AS Assignment

Owner name: NAMI MOS CO., LTD., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HSIEH, FU-YUAN;REEL/FRAME:051390/0712

Effective date: 20191230

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION