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US20190157213A1 - Semiconductor structure with substantially straight contact profile - Google Patents

Semiconductor structure with substantially straight contact profile Download PDF

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Publication number
US20190157213A1
US20190157213A1 US15/817,801 US201715817801A US2019157213A1 US 20190157213 A1 US20190157213 A1 US 20190157213A1 US 201715817801 A US201715817801 A US 201715817801A US 2019157213 A1 US2019157213 A1 US 2019157213A1
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Prior art keywords
oxidized
layer
block
substantially straight
interlevel dielectric
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US15/817,801
Inventor
Ronald Naumann
Matthias Zinke
Robert Seidel
Tobais BARCHEWITZ
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GlobalFoundries Inc
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GlobalFoundries Inc
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Priority to US15/817,801 priority Critical patent/US20190157213A1/en
Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NAUMANN, RONALD, BARCHEWITZ, TOBAIS, SEIDEL, ROBERT, ZINKE, MATTHIAS
Priority to TW107102215A priority patent/TW201924011A/en
Priority to DE102018202132.5A priority patent/DE102018202132B4/en
Priority to CN201810185273.6A priority patent/CN109817566A/en
Priority to US16/374,969 priority patent/US11127683B2/en
Publication of US20190157213A1 publication Critical patent/US20190157213A1/en
Assigned to GLOBALFOUNDRIES U.S. INC. reassignment GLOBALFOUNDRIES U.S. INC. RELEASE OF SECURITY INTEREST Assignors: WILMINGTON TRUST, NATIONAL ASSOCIATION
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Definitions

  • the present disclosure relates to semiconductor structures and, more particularly, to a semiconductor structure with a substantially straight contact profile and methods of manufacture.
  • Semiconductor devices include many different wiring layers. These wiring layers are formed in interlevel dielectric material and may include wiring structures, interconnect contacts, passive devices and active devices. The interconnect contacts are provided in different wiring layers of the die to connect to the different structures, e.g., different wiring structures, etc.
  • an adhesion layer is typically formed at a bottom surface of the interlevel dielectric material, e.g., bulk SiCOH materials, above a wiring structure.
  • the adhesion layer has a different etch rate than the interlevel dielectric material, resulting in a tapered via profile.
  • the etch rate is different for the interlevel dielectric material and the adhesion layer, these materials will etch at a different rate resulting in a tapered profile within the adhesion layer.
  • the tapered via profile leads to interconnect contacts with tapered profiles. This tapered profile of the interconnect contacts leads to electrical performance issues including void formation in the metal material, e.g., copper, as well as and time-dependent gate oxide breakdown (TDDB).
  • TDDB time-dependent gate oxide breakdown
  • etching of these different materials is also known to be difficult to control as it is not possible to measure the thickness of the adhesion layer, in line. And, different thicknesses of the adhesion layer will generate different tapered via profiles.
  • a structure comprises: a block material comprising an upper oxidized layer at an interface with an insulating material; and an interconnect contact structure with a substantially straight profile through the oxidized layer of the block material.
  • a structure comprises: a wiring layer formed in an insulator material; a block material comprising an upper surface composed of oxidized material; an interlevel dielectric material directly on the upper surface; and a contact extending to the wiring layer, through the block material, oxidized material and the interlevel dielectric material, the contact having a substantially straight profile within the oxidized material.
  • a method comprises: forming a blocking material over a wiring structure; oxidizing the blocking material to form an upper oxidized layer; forming an interlevel dielectric material over the oxidized layer; etching a via into the interlevel dielectric material, the oxidized layer and the blocking material to expose the wiring structure, the via having a substantially straight via profile through the oxidized layer; and forming a contact within the via, the contact having a substantially straight profile through the oxidized layer.
  • FIG. 1 shows a structure and respective fabrication processes in accordance with aspects of the present disclosure.
  • FIG. 2 shows a via with a substantially straight profile, amongst other features, and respective fabrication processes in accordance with aspects of the present disclosure.
  • FIG. 3 shows an interconnect contact with a substantially straight profile, amongst other features, and respective fabrication processes in accordance with aspects of the present disclosure.
  • the present disclosure relates to semiconductor structures and, more particularly, to a semiconductor structure with a substantially straight contact profile and methods of manufacture. More specifically, the present disclosure provides a substantially straight or vertical interconnect contact profile within an oxidized film in a blocking layer, below an interlevel dielectric material. Advantageously, by using the oxidized film, the present disclosure provides a more controllable via etching process, resulting in improved electrical parametric values of the interconnect contact, e.g., reduction in voids and time-dependent gate oxide breakdown (TDDB).
  • TDDB time-dependent gate oxide breakdown
  • an oxygen treatment is provided to an upper surface of a BLoK layer, e.g., low-k dielectric insulator material.
  • This oxygen treatment will improve taper control, e.g., etching, at the interface between an interlevel dielectric material and the BLoK layer. That is, by providing the oxygen treatment an oxidized layer of the BLoK layer will have a similar etch rate as the interlevel dielectric layer.
  • the resulting via profile will, in turn, have a straight or substantially straight profile at the interface between the two materials, e.g., substantially 90 degrees as measured relative to the horizontal dielectric surface, as the oxidized layer and the interlevel dielectric layer will have a similar etch rate.
  • the structure of the present disclosure can be manufactured in a number of ways using a number of different tools.
  • the methodologies and tools are used to form structures with dimensions in the micrometer and nanometer scale.
  • the methodologies, i.e., technologies, employed to manufacture the structure of the present disclosure have been adopted from integrated circuit (IC) technology.
  • the structure can be built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer.
  • the fabrication of the structure uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask.
  • FIG. 1 shows a structure and respective fabrication processes in accordance with aspects of the present disclosure.
  • the structure 10 includes a wiring structure 12 formed in an insulator material 14 .
  • the insulator material 14 can be an oxide based material.
  • the metal wiring structure 12 can be formed of a copper material, for example, using conventional lithography, etching and deposition processes.
  • a resist formed over the insulator material 14 is exposed to energy (light) to form a pattern (opening).
  • An etching process with a selective chemistry e.g., reactive ion etching (RIE)
  • RIE reactive ion etching
  • the resist can then be removed by a conventional oxygen ashing process or other known stripants.
  • the conductive material can be deposited by any conventional deposition processes, e.g., electroplating processes. Any residual material on the surface of the insulator material 14 can be removed by conventional chemical mechanical polishing (CMP) processes.
  • CMP chemical mechanical polishing
  • a block material 16 is formed over the insulator material 14 and the wiring structure 12 .
  • the block material 16 is a low-k dielectric layer e, g., nitride material.
  • the block material 16 can be an NBLoK (NBLoK is a trademark of Applied Materials, Inc.), which is a nitrogen-doped silicon carbide material.
  • the block material 16 can be deposited by any conventional deposition process, e.g., chemical vapor deposition (CVD) processes, to a particular thickness depending on the technology node.
  • CVD chemical vapor deposition
  • the thickness of the block layer and the thickness of the oxidized layer should be balanced such that the remaining block thickness is still sufficient to act as diffusion barrier.
  • the block material 16 undergoes an oxygen treatment to form an oxidized layer 18 .
  • the oxidized layer 18 can be at an upper surface of the block material and, more specifically, can extend about 5 nm to about 25 nm, depending on the technology node; although other thicknesses are also provided herein. In more specific examples, the oxidized layer 18 can be about 20% to about 30% of the thickness of the block material 16 . In one specific embodiment, the oxidized layer 18 can be about 5 nm for a 35 nm thick block material 16 .
  • the oxygen treatment can be provided in an oxygen atmosphere.
  • the oxygen atmosphere can be, e.g., O 2 , NO 2 or CO 2 , in a carrier gas in a CVD chamber.
  • the oxygen treatment can be provided after the start of the deposition process using the same CVD chamber as the deposition process.
  • the oxidation treatment can be provided after the start of or at the end of the deposition process of the block material 16 . In this way, the oxidation can be provided in situ.
  • the oxygen treatment can be provided prior to the deposition interlevel dielectric material, e.g., oxygen pre-treatment before SiCOH deposition, in either an external tool or within the deposition chamber.
  • the oxygen treatment can be provided using a remote plasma tool, after the deposition process.
  • the oxygen treatment should not affect the underlying metal features, e.g., wiring structure 12 .
  • an interlevel dielectric material 20 is deposited over the block material 16 and, in more specific embodiments, the interlevel dielectric material 20 can be bulk SiCOH deposited directly on the oxidized layer 18 using a conventional blanket deposition process, e.g., CVD. Accordingly, in this latter implementation, the oxygen treatment process would occur prior to the deposition of the interlevel dielectric material 20 .
  • the etch rate of the interlevel dielectric material 20 and the oxidized layer 18 is similar, as should be understood by those of skill in the art.
  • a stack of hardmasks 22 , 24 is deposited on the interlevel dielectric material 20 .
  • the hardmask 22 is an ILD hardmask 22 and the hardmask 24 is a TiN hardmask, as examples.
  • FIG. 2 shows a via 26 formed within the structure of FIG. 1 .
  • the via 26 can be formed by a conventional dual or single damascene process, as should be understood by those of skill in the art such that no further explanation is required herein.
  • the etching rate of the interlevel dielectric material 20 and the oxidized layer 18 have a substantially same etch rate, the portion of the via formed within the oxidized layer 18 will have a substantially straight profile 28 (regardless of the thickness of the oxidized layer).
  • the substantially straight profile 28 is it means substantially 90 degrees as measured relative to the horizontal surface of the dielectric material or underlying wiring structure 12 .
  • the etching process can be performed using conventional etching cycles, e.g., RIE processes, with the interlevel dielectric material 20 and the oxidized layer 18 , amongst the other layers, being etched together, to expose the underlying wiring structure 12 .
  • conventional etching cycles e.g., RIE processes
  • FIG. 3 shows an interconnect contact 30 with a substantially straight profile, amongst other features, formed in the via 26 .
  • the hardmasks can be removed by known stripping processes.
  • the interconnect contact 30 will be formed within the via by conventional deposition processes, followed by a chemical mechanical polishing (CMP), as an example.
  • CMP chemical mechanical polishing
  • the deposition of tungsten can be a CVD process
  • the deposition of aluminum can be a plasma vapor deposition (PVD) process
  • PVD plasma vapor deposition
  • other metal or metal alloy materials can be deposited by an electroplating process.
  • the straight profile is due to the fact that the interconnect material is deposited within the via with the straight profile 28 .
  • the method(s) as described above is used in the fabrication of integrated circuit chips.
  • the resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form.
  • the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections).
  • the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product.
  • the end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

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Abstract

The present disclosure relates to semiconductor structures and, more particularly, to a semiconductor structure with a substantially straight contact profile and methods of manufacture. The structure includes a block material comprising an upper oxidized layer at an interface with an insulating material; and an interconnect contact structure with a substantially straight profile through the oxidized layer of the block material.

Description

    FIELD OF THE INVENTION
  • The present disclosure relates to semiconductor structures and, more particularly, to a semiconductor structure with a substantially straight contact profile and methods of manufacture.
    • BACKGROUND
  • Semiconductor devices include many different wiring layers. These wiring layers are formed in interlevel dielectric material and may include wiring structures, interconnect contacts, passive devices and active devices. The interconnect contacts are provided in different wiring layers of the die to connect to the different structures, e.g., different wiring structures, etc.
  • In manufacturing the semiconductor devices, an adhesion layer is typically formed at a bottom surface of the interlevel dielectric material, e.g., bulk SiCOH materials, above a wiring structure. The adhesion layer, though, has a different etch rate than the interlevel dielectric material, resulting in a tapered via profile. In other words, as the etch rate is different for the interlevel dielectric material and the adhesion layer, these materials will etch at a different rate resulting in a tapered profile within the adhesion layer. The tapered via profile, in turn, leads to interconnect contacts with tapered profiles. This tapered profile of the interconnect contacts leads to electrical performance issues including void formation in the metal material, e.g., copper, as well as and time-dependent gate oxide breakdown (TDDB).
  • The etching of these different materials is also known to be difficult to control as it is not possible to measure the thickness of the adhesion layer, in line. And, different thicknesses of the adhesion layer will generate different tapered via profiles.
    • SUMMARY
  • In an aspect of the disclosure, a structure comprises: a block material comprising an upper oxidized layer at an interface with an insulating material; and an interconnect contact structure with a substantially straight profile through the oxidized layer of the block material.
  • In an aspect of the disclosure, a structure comprises: a wiring layer formed in an insulator material; a block material comprising an upper surface composed of oxidized material; an interlevel dielectric material directly on the upper surface; and a contact extending to the wiring layer, through the block material, oxidized material and the interlevel dielectric material, the contact having a substantially straight profile within the oxidized material.
  • In an aspect of the disclosure, a method comprises: forming a blocking material over a wiring structure; oxidizing the blocking material to form an upper oxidized layer; forming an interlevel dielectric material over the oxidized layer; etching a via into the interlevel dielectric material, the oxidized layer and the blocking material to expose the wiring structure, the via having a substantially straight via profile through the oxidized layer; and forming a contact within the via, the contact having a substantially straight profile through the oxidized layer.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present disclosure is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure.
  • FIG. 1 shows a structure and respective fabrication processes in accordance with aspects of the present disclosure.
  • FIG. 2 shows a via with a substantially straight profile, amongst other features, and respective fabrication processes in accordance with aspects of the present disclosure.
  • FIG. 3 shows an interconnect contact with a substantially straight profile, amongst other features, and respective fabrication processes in accordance with aspects of the present disclosure.
    •  DETAILED DESCRIPTION
  • The present disclosure relates to semiconductor structures and, more particularly, to a semiconductor structure with a substantially straight contact profile and methods of manufacture. More specifically, the present disclosure provides a substantially straight or vertical interconnect contact profile within an oxidized film in a blocking layer, below an interlevel dielectric material. Advantageously, by using the oxidized film, the present disclosure provides a more controllable via etching process, resulting in improved electrical parametric values of the interconnect contact, e.g., reduction in voids and time-dependent gate oxide breakdown (TDDB).
  • In embodiments, an oxygen treatment is provided to an upper surface of a BLoK layer, e.g., low-k dielectric insulator material. This oxygen treatment will improve taper control, e.g., etching, at the interface between an interlevel dielectric material and the BLoK layer. That is, by providing the oxygen treatment an oxidized layer of the BLoK layer will have a similar etch rate as the interlevel dielectric layer. The resulting via profile will, in turn, have a straight or substantially straight profile at the interface between the two materials, e.g., substantially 90 degrees as measured relative to the horizontal dielectric surface, as the oxidized layer and the interlevel dielectric layer will have a similar etch rate. In addition, by implementing the processes described herein, it is possible to eliminate the adhesion layer formed at the bottom of the interlevel dielectric layer that typically causes a tapered via profile during the etching process.
  • The structure of the present disclosure can be manufactured in a number of ways using a number of different tools. In general, though, the methodologies and tools are used to form structures with dimensions in the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to manufacture the structure of the present disclosure have been adopted from integrated circuit (IC) technology. For example, the structure can be built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer. In particular, the fabrication of the structure uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask.
  • FIG. 1 shows a structure and respective fabrication processes in accordance with aspects of the present disclosure. Specifically, the structure 10 includes a wiring structure 12 formed in an insulator material 14. In embodiments, the insulator material 14 can be an oxide based material. The metal wiring structure 12 can be formed of a copper material, for example, using conventional lithography, etching and deposition processes.
  • For example, to form the wiring structure 12, a resist formed over the insulator material 14 is exposed to energy (light) to form a pattern (opening). An etching process with a selective chemistry, e.g., reactive ion etching (RIE), will be used to form one or more trenches in the insulator material 14 through the openings of the resist. The resist can then be removed by a conventional oxygen ashing process or other known stripants. Following the resist removal, the conductive material can be deposited by any conventional deposition processes, e.g., electroplating processes. Any residual material on the surface of the insulator material 14 can be removed by conventional chemical mechanical polishing (CMP) processes.
  • Still referring to FIG. 1, a block material 16 is formed over the insulator material 14 and the wiring structure 12. In embodiments, the block material 16 is a low-k dielectric layer e, g., nitride material. In more specific embodiments, the block material 16 can be an NBLoK (NBLoK is a trademark of Applied Materials, Inc.), which is a nitrogen-doped silicon carbide material. In embodiments, the block material 16 can be deposited by any conventional deposition process, e.g., chemical vapor deposition (CVD) processes, to a particular thickness depending on the technology node. By way non-limiting example, the thickness of the block layer and the thickness of the oxidized layer should be balanced such that the remaining block thickness is still sufficient to act as diffusion barrier.
  • In embodiments, the block material 16 undergoes an oxygen treatment to form an oxidized layer 18. In embodiments, the oxidized layer 18 can be at an upper surface of the block material and, more specifically, can extend about 5 nm to about 25 nm, depending on the technology node; although other thicknesses are also provided herein. In more specific examples, the oxidized layer 18 can be about 20% to about 30% of the thickness of the block material 16. In one specific embodiment, the oxidized layer 18 can be about 5 nm for a 35 nm thick block material 16.
  • The oxygen treatment can be provided in an oxygen atmosphere. The oxygen atmosphere can be, e.g., O2, NO2 or CO2, in a carrier gas in a CVD chamber. For example, the oxygen treatment can be provided after the start of the deposition process using the same CVD chamber as the deposition process. For example, the oxidation treatment can be provided after the start of or at the end of the deposition process of the block material 16. In this way, the oxidation can be provided in situ. Alternatively, the oxygen treatment can be provided prior to the deposition interlevel dielectric material, e.g., oxygen pre-treatment before SiCOH deposition, in either an external tool or within the deposition chamber. As an example, the oxygen treatment can be provided using a remote plasma tool, after the deposition process. In embodiments, the oxygen treatment should not affect the underlying metal features, e.g., wiring structure 12.
  • Still referring to FIG. 1, an interlevel dielectric material 20 is deposited over the block material 16 and, in more specific embodiments, the interlevel dielectric material 20 can be bulk SiCOH deposited directly on the oxidized layer 18 using a conventional blanket deposition process, e.g., CVD. Accordingly, in this latter implementation, the oxygen treatment process would occur prior to the deposition of the interlevel dielectric material 20. In embodiments, the etch rate of the interlevel dielectric material 20 and the oxidized layer 18 is similar, as should be understood by those of skill in the art. A stack of hardmasks 22, 24 is deposited on the interlevel dielectric material 20. In embodiments, the hardmask 22 is an ILD hardmask 22 and the hardmask 24 is a TiN hardmask, as examples.
  • FIG. 2 shows a via 26 formed within the structure of FIG. 1. In embodiments, the via 26 can be formed by a conventional dual or single damascene process, as should be understood by those of skill in the art such that no further explanation is required herein. As the etching rate of the interlevel dielectric material 20 and the oxidized layer 18 have a substantially same etch rate, the portion of the via formed within the oxidized layer 18 will have a substantially straight profile 28 (regardless of the thickness of the oxidized layer). In embodiments, the substantially straight profile 28 is it means substantially 90 degrees as measured relative to the horizontal surface of the dielectric material or underlying wiring structure 12. The etching process can be performed using conventional etching cycles, e.g., RIE processes, with the interlevel dielectric material 20 and the oxidized layer 18, amongst the other layers, being etched together, to expose the underlying wiring structure 12.
  • FIG. 3 shows an interconnect contact 30 with a substantially straight profile, amongst other features, formed in the via 26. Prior to the deposition of the interconnect material, the hardmasks can be removed by known stripping processes. The interconnect contact 30 will be formed within the via by conventional deposition processes, followed by a chemical mechanical polishing (CMP), as an example. In embodiments, the deposition of tungsten can be a CVD process, the deposition of aluminum can be a plasma vapor deposition (PVD) process and other metal or metal alloy materials can be deposited by an electroplating process. The straight profile is due to the fact that the interconnect material is deposited within the via with the straight profile 28.
  • The method(s) as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
  • The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (20)

1. A structure, comprising:
a block material comprising an upper oxidized layer at an interface with an insulating material, the insulating material and the oxidized layer having substantially a same etching rate regardless of a thickness of the oxidized layer; and
an interconnect contact structure with a substantially straight profile through the oxidized layer of the block material, the interconnect contact structure extending through the insulating material and contacting an underlying wiring structure,
wherein the substantially straight profile is substantially 90 degrees as measured relative to a horizontal surface of the underlying wiring structure.
2. (canceled)
3. The structure of claim 1, wherein the insulating material is a dielectric material composed of SiCOH.
4. The structure of claim 1, wherein the oxidized layer is about 20% to 30% of a thickness of the block material.
5. (canceled)
6. (canceled)
7. The structure of claim 1, wherein the block material is composed of nitride material.
8. The structure of claim 1, wherein the block material is composed of nitrogen-doped silicon carbide.
9. The structure of claim 8, wherein the insulating layer is bulk SiCOH.
10. A structure comprising:
a wiring layer formed in an insulator material;
a low-k dielectric block material comprising an upper surface composed of oxidized material;
an interlevel dielectric material directly on the upper surface, the interlevel dielectric material and the oxidized material of the low-k dielectric block material having substantially a same etching rate regardless of a thickness of the oxidized material; and
a contact extending to the wiring layer, through the block material, oxidized material and the interlevel dielectric material, the contact having a substantially straight profile within the oxidized material, the contact structure extending through the interlevel dielectric material and contacting the wiring layer,
wherein the substantially straight profile is substantially 90 degrees as measured relative to a horizontal surface of the wiring layer.
11. The structure of claim 10, wherein the interlevel dielectric material is composed of bulk SiCOH.
12. The structure of claim 10, wherein the oxidized material is about 20% to 30% of a thickness of the block material.
13. The structure of claim 10, wherein the interlevel dielectric material and the oxidized material have substantially a same etching rate.
14. The structure of claim 13, wherein the low-k dielectric block material is composed of nitride material.
15. The structure of claim 14, wherein the low-k dielectric block material is composed of nitrogen-doped silicon carbide.
16. The structure of claim 14, wherein the oxidized material has a thickness of about 12 nm to 25 nm.
17.-20. (canceled)
21. The structure of claim 1, wherein the block material is a low-k dielectric material that covers insulating material and partially covers an upper surface of the underlying wiring structure.
22. The structure of claim 21, wherein the interconnect contact is tungsten and the insulating material is an oxide material.
23. The structure of claim 22, wherein the underlying wiring structure is a copper material.
US15/817,801 2017-11-20 2017-11-20 Semiconductor structure with substantially straight contact profile Abandoned US20190157213A1 (en)

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US20190229063A1 (en) 2019-07-25
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