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US20160141242A1 - Method and apparatus for a high yield contact integration scheme - Google Patents

Method and apparatus for a high yield contact integration scheme Download PDF

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Publication number
US20160141242A1
US20160141242A1 US15/001,390 US201615001390A US2016141242A1 US 20160141242 A1 US20160141242 A1 US 20160141242A1 US 201615001390 A US201615001390 A US 201615001390A US 2016141242 A1 US2016141242 A1 US 2016141242A1
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Prior art keywords
trenches
tip
wafer
block mask
contact
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US15/001,390
Inventor
Ryan Kim
Jason R. Cantone
Wenhui Wang
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Alsephina Innovations Inc
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GlobalFoundries Inc
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Priority to US15/001,390 priority Critical patent/US20160141242A1/en
Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KIM, RYAN, WANG, WENHUI, CANTONE, JASON R.
Publication of US20160141242A1 publication Critical patent/US20160141242A1/en
Assigned to ALSEPHINA INNOVATIONS INC. reassignment ALSEPHINA INNOVATIONS INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GLOBALFOUNDRIES INC.
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H01L27/1104—
    • H01L27/1116—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/18—Peripheral circuit regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present disclosure relates to a semiconductor contact integration scheme.
  • the present disclosure is particularly applicable to static random access memory (SRAM) design for 20 nanometer (nm) and beyond technology nodes.
  • SRAM static random access memory
  • 193 nm immersion lithography Due to the high resource requirements of extreme ultraviolet (EUV) lithography, 193 nm immersion lithography remains an attractive alternative for the fabrication of 20 nm and beyond technology nodes.
  • 193 nm immersion lithography techniques suffer from reliability and yield issues caused by time dependent dielectric breakdown (TDDB), especially for tight contact tip-to-tip spacing.
  • TDDB time dependent dielectric breakdown
  • the problems caused by tight tip-to-tip contact spacing are particularly severe in highly integrated circuits with the greatest demands for feature size reduction and scaling (e.g., 10 nm SRAM design).
  • FIG. 1 illustrates a top view 100 of contact trenches 101 and gates 103 .
  • a triple patterning process e.g., with 193 nm immersion lithography
  • CGP tight contact to gate pitch
  • a triple patterning process is used to pattern the contact trenches 101 alongside the gates 103 .
  • shorts may still occur in tight tip-to-tip contact spacings.
  • the tip-to-tip spacing near gate contacts 109 may be particularly small.
  • process optimization for triple patterning is particularly expensive and resource-intensive because of the unknown variation of the tools at these feature sizes.
  • product overlay does not scale at the same rate as the rate at which chip features are down-scaled.
  • the integration margin for 20 nm nodes is, therefore, not as great as it is for less advanced technology nodes.
  • mask error remains a problem and further complicates the contact integration process. For example, the risk of contact-to-contact shorts is greater for end-of-line process stages because of the greater mask error enhancement factor (MEEF).
  • MEEF mask error enhancement factor
  • MOL middle-of-line
  • An aspect of the present disclosure is a method of patterning contacts for a MOL integration stack that results in greatly reduced risk of contact-to-contact shorts and TDDB.
  • Another aspect of the present disclosure is a contact area of a semiconductor device exhibiting greatly reduced risk of contact-to-contact shorts and TDDB.
  • some technical effects may be achieved in part by a method including: forming one or more trench patterning layers on a planarized surface of a wafer, forming one or more trenches in the one or more trench patterning layers, forming a block mask at one or more points along the one or more trenches, extending the one or more trenches down to a substrate level of the wafer, and removing the block mask from the one or more points.
  • aspects of the present disclosure include forming the one or more trenches according to a double patterning process. Additional aspects include the one or more points are associated with a tight tip-to-tip contact spacing parameter. Further aspects include determining the one or more points along the trench associated with a tight tip-to-tip contact spacing parameter. Additional aspects include extending the one or more trenches down to one or more contact areas of one or more semiconductor devices formed on the wafer. Further aspects include forming a first dielectric material between one or more semiconductor devices on the wafer, planarizing the wafer down to the one or more semiconductor devices, forming a first trench patterning layer on the planarized wafer surface, and forming a second trench patterning layer on the first trench patterning layer.
  • Additional aspects include forming the first trench patterning layer of a dielectric material to a thickness greater than 10 nm and forming the second trench patterning layer of silicon nitride (SiN), silicon dioxide (SiO 2 ), titanium (Ti) or silicon carbide (SiC) to a thickness greater than 10 nm.
  • Further aspects include a critical dimension of the block mask corresponds to a tip-to-tip contact spacing. Additional aspects include a critical dimension of the block mask is 10 nm to 150 nm. Further aspects include the block mask includes photoresist, SiN, or titanium nitride (TiN). Further aspects include defining one or more large contact-to-contact spacings when forming the one or more first and second trenches.
  • a device including: a wafer, one or more semiconductor devices including source/drain regions on the wafer, a dielectric material between the one or more semiconductor devices, and one or more contact areas, through the dielectric material, having a tight tip-to-tip contact spacing, wherein the contact areas are formed by forming one or more trench patterning layers on a planarized surface of the wafer, forming one or more trenches in the one or more trench patterning layers, forming a block mask at one or more points along the one or more trenches, extending the one or more trenches down to the source/drain regions, removing the block mask from the one or more points, wherein the tip-to-tip contact spacing corresponds to a critical dimension of the block mask. Additional aspects include the critical dimension of the block mask is 10 nm to 150 nm. Further aspects include the block mask comprises photoresist, SiN, or TiN.
  • aspects include a method including: forming one or more trench patterning layers on a planarized surface of a wafer, forming one or more first trenches in the one or more trench patterning layers, forming one or more second trenches in the one or more trench patterning layers, determining one or more points along the one or more first and second trenches associated with a tight tip-to-tip contact spacing parameter, forming a block mask at the one or more points, extending the one or more first and second trenches down to a substrate level of the wafer, and removing the block mask from the one or more points.
  • aspects include forming the one or more first and second trenches in the one or more trench patterning layers according to a self-aligned double patterning process. Additional aspects include extending the one or more first and second trenches down to one or more contact areas of one or more semiconductive devices on the wafer. Further aspects include a critical dimension of the block mask corresponds to a tip-to-tip contact spacing. Additional aspects include a critical dimension of the block mask is 10 nm to 150 nm. Further aspects include defining one or more large contact-to-contact spacings when forming the one or more first and second trenches.
  • FIG. 1 schematically illustrates a top view of a semiconductor wafer patterned according to a conventional contact integration scheme
  • FIGS. 2A-1 through 2E-1 schematically illustrate top views of a contact integration scheme, in accordance with an exemplary embodiment
  • FIGS. 2A-2 through 2E-2 schematically illustrate cross section views of a contact integration scheme, in accordance with an exemplary embodiment.
  • a block mask is used to define the tip-to-tip spacing.
  • Methodology in accordance with embodiments of the present disclosure includes forming one or more trench patterning layers on a planarized surface of a wafer, forming one or more trenches in the one or more trench patterning layers, forming a block mask at one or more points along the one or more trenches, extending the one or more trenches down to a substrate level of the wafer, and removing the block mask from the one or more points.
  • FIGS. 2A through 2E schematically illustrate a contact integration scheme, in accordance with an exemplary embodiment of the present disclosure.
  • FIGS. 2A-1 and 2A-2 illustrate respective top ( 201 ) and cross-sectional ( 203 ) views of a MOL integration stack 205 .
  • the areas 207 in the top view 201 correspond to gates 207 of the semiconductor devices 209 in the cross section view 203 .
  • the semiconductor devices 209 are beneath a first trench patterning layer 211 and a second trench patterning layer 213 .
  • the first trench patterning layer 211 may also be referred to as an inter-layer dielectric (ILD) layer and may have a thickness greater than 10 nm.
  • ILD inter-layer dielectric
  • the second trench patterning layer 213 may, for example, be formed from SiN, SiO 2 , Ti, or silicon carbide (SiC) and has a thickness greater than 10 nm.
  • the semiconductor devices 209 may have shared source/drain regions (e.g., shared source/drain 215 ).
  • the material 217 deposited between the semiconductor devices 209 and above the substrate may be any dielectric material or another ILD material.
  • shallow trench isolation (STI) regions may be present for device isolation.
  • FIGS. 2B-1 and 2B-2 illustrate respective top ( 201 ) and cross-sectional ( 203 ) views of the MOL integration stack 205 following a first patterning step.
  • a photoresist layer 219 was formed on the second trench patterning layer 213 and was etched down to the first trench patterning layer 211 to form contact trenches 221 a - 221 c (collectively referred to as contact trenches 221 ).
  • the contact trenches 221 are formed alongside the gates 207 .
  • FIGS. 2C-1 and 2C-2 illustrate respective top ( 201 ) and cross-sectional ( 203 ) views of the MOL integration stack 205 following a second patterning step.
  • a second photoresist layer 223 was formed on the etched second trench patterning layer 213 and was patterned to further etch the second trench patterning layer 213 at contact trenches 225 a - 225 c (collectively referred as contact trenches 225 ).
  • the contact trenches 225 are formed alongside the gates 207 .
  • the second patterning step does not etch at points 227 that have a large contact-to-contact spacing.
  • the first and second patterning steps may be performed according to a lithography-etch-lithography-etch (LELE) double patterning process.
  • LELE lithography-etch-lithography-etch
  • the contact trenches 221 formed in the first patterning step and the contact trenches 225 formed in the second patterning step may correspond to two successive lithography-etch cycles in a LELE double patterning process.
  • FIGS. 2D-1 and 2D-2 illustrate respective top ( 201 ) and cross-sectional ( 203 ) views of the MOL integration stack 205 after removal of the second photoresist layer 223 and formation of block masks 229 a - 229 d (collectively referred to as block masks 229 ) at tight contact-to-contact spacing points.
  • block masks 229 may be used to refer to any tip-to-tip spacing that is greater than or equal to 10 nm and less than or equal to 150 nm.
  • the critical dimension of the block masks 229 corresponds to the required contact-to-contact spacing at the tight contact-to-contact spacing points.
  • the block mask 229 c masks the contact trench 221 b formed in the first patterning step.
  • the block mask may be formed to a height of 40 nm or greater and may be formed from photoresist, SiN, or TiN.
  • FIGS. 2E-1 and 2E-2 illustrate respective top ( 201 ) and cross-sectional ( 203 ) views of the MOL integration stack 205 after the contact trenches 221 and 225 (as shown in FIG. 2D-2 ) have been etched through the first trench patterning layer 211 down to the contact areas 231 a - 231 e (collectively referred to as contact areas 231 ) of the semiconductor devices 209 and the block masks 229 have been removed.
  • the contact-to-contact spacing at the tight contact-to-contact spacing points 233 a - 233 d correspond to the critical dimensions of the block masks 229 that were used to mask these points (as indicated by the dashed lines).
  • the first trench patterning layer 211 has not been etched in the tight contact-to-contact spacing point 233 c corresponding to the location of the contact trench 221 b ) because of the block masking.
  • the embodiments of the present disclosure can achieve several technical effects, including reduced risk of contact-to-contact short at points with tight tip-to-tip spacing, reduced risk of time dependent dielectric breakdown, as well as increased yield.
  • the present disclosure enjoys industrial applicability in fabricating any of various types of highly integrated semiconductor devices, particularly for 20 nm and beyond technology nodes.

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Abstract

A methodology for forming contact areas by a multiple patterning process that provides increased yield and lower risk of contact-to-contact short at points of tight tip-to-tip spacing and the resulting device are disclosed. Embodiments include forming one or more trench patterning layers on a planarized surface of a wafer, forming one or more trenches in the one or more trench patterning layers, forming a block mask at one or more points along the one or more trenches, extending the one or more trenches down to a substrate level of the wafer, and removing the block mask from the one or more points.

Description

    RELATED APPLICATION
  • The present application is a Divisional application of application Ser. No. 14/045,340, filed on Oct. 3, 2013, which is incorporated herein by reference in its entirety.
    • TECHNICAL FIELD
  • The present disclosure relates to a semiconductor contact integration scheme. The present disclosure is particularly applicable to static random access memory (SRAM) design for 20 nanometer (nm) and beyond technology nodes.
    • BACKGROUND
  • Due to the high resource requirements of extreme ultraviolet (EUV) lithography, 193 nm immersion lithography remains an attractive alternative for the fabrication of 20 nm and beyond technology nodes. However, 193 nm immersion lithography techniques suffer from reliability and yield issues caused by time dependent dielectric breakdown (TDDB), especially for tight contact tip-to-tip spacing. The problems caused by tight tip-to-tip contact spacing are particularly severe in highly integrated circuits with the greatest demands for feature size reduction and scaling (e.g., 10 nm SRAM design).
  • FIG. 1 illustrates a top view 100 of contact trenches 101 and gates 103. Due to the tight contact to gate pitch (CGP) 105, a triple patterning process (e.g., with 193 nm immersion lithography) is used to pattern the contact trenches 101 alongside the gates 103. Despite the high resolution of the triple patterning process, shorts may still occur in tight tip-to-tip contact spacings. For example, the tip-to-tip spacing near gate contacts 109 may be particularly small. Furthermore, process optimization for triple patterning is particularly expensive and resource-intensive because of the unknown variation of the tools at these feature sizes. For example, product overlay does not scale at the same rate as the rate at which chip features are down-scaled. The integration margin for 20 nm nodes is, therefore, not as great as it is for less advanced technology nodes. In addition, mask error remains a problem and further complicates the contact integration process. For example, the risk of contact-to-contact shorts is greater for end-of-line process stages because of the greater mask error enhancement factor (MEEF).
  • A need therefore exists for a methodology enabling less costly middle-of-line (MOL) contact integration with improved yield and reliability, and the resulting device.
    • SUMMARY
  • An aspect of the present disclosure is a method of patterning contacts for a MOL integration stack that results in greatly reduced risk of contact-to-contact shorts and TDDB.
  • Another aspect of the present disclosure is a contact area of a semiconductor device exhibiting greatly reduced risk of contact-to-contact shorts and TDDB.
  • Additional aspects and other features of the present disclosure will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present disclosure. The advantages of the present disclosure may be realized and obtained as particularly pointed out in the appended claims.
  • According to the present disclosure, some technical effects may be achieved in part by a method including: forming one or more trench patterning layers on a planarized surface of a wafer, forming one or more trenches in the one or more trench patterning layers, forming a block mask at one or more points along the one or more trenches, extending the one or more trenches down to a substrate level of the wafer, and removing the block mask from the one or more points.
  • Aspects of the present disclosure include forming the one or more trenches according to a double patterning process. Additional aspects include the one or more points are associated with a tight tip-to-tip contact spacing parameter. Further aspects include determining the one or more points along the trench associated with a tight tip-to-tip contact spacing parameter. Additional aspects include extending the one or more trenches down to one or more contact areas of one or more semiconductor devices formed on the wafer. Further aspects include forming a first dielectric material between one or more semiconductor devices on the wafer, planarizing the wafer down to the one or more semiconductor devices, forming a first trench patterning layer on the planarized wafer surface, and forming a second trench patterning layer on the first trench patterning layer. Additional aspects include forming the first trench patterning layer of a dielectric material to a thickness greater than 10 nm and forming the second trench patterning layer of silicon nitride (SiN), silicon dioxide (SiO2), titanium (Ti) or silicon carbide (SiC) to a thickness greater than 10 nm. Further aspects include a critical dimension of the block mask corresponds to a tip-to-tip contact spacing. Additional aspects include a critical dimension of the block mask is 10 nm to 150 nm. Further aspects include the block mask includes photoresist, SiN, or titanium nitride (TiN). Further aspects include defining one or more large contact-to-contact spacings when forming the one or more first and second trenches.
  • Another aspect of the present disclosure is a device including: a wafer, one or more semiconductor devices including source/drain regions on the wafer, a dielectric material between the one or more semiconductor devices, and one or more contact areas, through the dielectric material, having a tight tip-to-tip contact spacing, wherein the contact areas are formed by forming one or more trench patterning layers on a planarized surface of the wafer, forming one or more trenches in the one or more trench patterning layers, forming a block mask at one or more points along the one or more trenches, extending the one or more trenches down to the source/drain regions, removing the block mask from the one or more points, wherein the tip-to-tip contact spacing corresponds to a critical dimension of the block mask. Additional aspects include the critical dimension of the block mask is 10 nm to 150 nm. Further aspects include the block mask comprises photoresist, SiN, or TiN.
  • Aspects include a method including: forming one or more trench patterning layers on a planarized surface of a wafer, forming one or more first trenches in the one or more trench patterning layers, forming one or more second trenches in the one or more trench patterning layers, determining one or more points along the one or more first and second trenches associated with a tight tip-to-tip contact spacing parameter, forming a block mask at the one or more points, extending the one or more first and second trenches down to a substrate level of the wafer, and removing the block mask from the one or more points.
  • Other aspects include forming the one or more first and second trenches in the one or more trench patterning layers according to a self-aligned double patterning process. Additional aspects include extending the one or more first and second trenches down to one or more contact areas of one or more semiconductive devices on the wafer. Further aspects include a critical dimension of the block mask corresponds to a tip-to-tip contact spacing. Additional aspects include a critical dimension of the block mask is 10 nm to 150 nm. Further aspects include defining one or more large contact-to-contact spacings when forming the one or more first and second trenches.
  • Additional aspects and technical effects of the present disclosure will become readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present disclosure are described simply by way of illustration of the best mode contemplated to carry out the present disclosure. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:
  • FIG. 1 schematically illustrates a top view of a semiconductor wafer patterned according to a conventional contact integration scheme;
  • FIGS. 2A-1 through 2E-1 schematically illustrate top views of a contact integration scheme, in accordance with an exemplary embodiment; and
  • FIGS. 2A-2 through 2E-2 schematically illustrate cross section views of a contact integration scheme, in accordance with an exemplary embodiment.
    •  DETAILED DESCRIPTION
  • In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.”
  • The present disclosure addresses and solves the current problem of contact-to-contact shorts attendant upon tight tip-to-tip spacing in advanced technology nodes. In accordance with embodiments of the present disclosure, a block mask is used to define the tip-to-tip spacing.
  • Methodology in accordance with embodiments of the present disclosure includes forming one or more trench patterning layers on a planarized surface of a wafer, forming one or more trenches in the one or more trench patterning layers, forming a block mask at one or more points along the one or more trenches, extending the one or more trenches down to a substrate level of the wafer, and removing the block mask from the one or more points.
  • Still other aspects, features, and technical effects will be readily apparent to those skilled in this art from the following detailed description, wherein preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated. The disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
  • FIGS. 2A through 2E schematically illustrate a contact integration scheme, in accordance with an exemplary embodiment of the present disclosure.
  • FIGS. 2A-1 and 2A-2 illustrate respective top (201) and cross-sectional (203) views of a MOL integration stack 205. The areas 207 in the top view 201 correspond to gates 207 of the semiconductor devices 209 in the cross section view 203. As shown in FIG. 2A-2, the semiconductor devices 209 are beneath a first trench patterning layer 211 and a second trench patterning layer 213. The first trench patterning layer 211 may also be referred to as an inter-layer dielectric (ILD) layer and may have a thickness greater than 10 nm. The second trench patterning layer 213 may, for example, be formed from SiN, SiO2, Ti, or silicon carbide (SiC) and has a thickness greater than 10 nm. As shown, the semiconductor devices 209 may have shared source/drain regions (e.g., shared source/drain 215). The material 217 deposited between the semiconductor devices 209 and above the substrate may be any dielectric material or another ILD material. As further shown, shallow trench isolation (STI) regions may be present for device isolation.
  • FIGS. 2B-1 and 2B-2 illustrate respective top (201) and cross-sectional (203) views of the MOL integration stack 205 following a first patterning step. As shown in FIG. 2B-2, a photoresist layer 219 was formed on the second trench patterning layer 213 and was etched down to the first trench patterning layer 211 to form contact trenches 221 a-221 c (collectively referred to as contact trenches 221). As shown in FIG. 2B-1, the contact trenches 221 are formed alongside the gates 207.
  • FIGS. 2C-1 and 2C-2 illustrate respective top (201) and cross-sectional (203) views of the MOL integration stack 205 following a second patterning step. A second photoresist layer 223 was formed on the etched second trench patterning layer 213 and was patterned to further etch the second trench patterning layer 213 at contact trenches 225 a-225 c (collectively referred as contact trenches 225). As shown in FIG. 2C-1, the contact trenches 225 are formed alongside the gates 207. The second patterning step does not etch at points 227 that have a large contact-to-contact spacing.
  • The first and second patterning steps may be performed according to a lithography-etch-lithography-etch (LELE) double patterning process. For example, the contact trenches 221 formed in the first patterning step and the contact trenches 225 formed in the second patterning step may correspond to two successive lithography-etch cycles in a LELE double patterning process.
  • FIGS. 2D-1 and 2D-2 illustrate respective top (201) and cross-sectional (203) views of the MOL integration stack 205 after removal of the second photoresist layer 223 and formation of block masks 229 a-229 d (collectively referred to as block masks 229) at tight contact-to-contact spacing points. As used herein, the term “tight” may be used to refer to any tip-to-tip spacing that is greater than or equal to 10 nm and less than or equal to 150 nm. As shown in the top view 201, the critical dimension of the block masks 229 corresponds to the required contact-to-contact spacing at the tight contact-to-contact spacing points. As shown in the cross section view 203, the block mask 229 c masks the contact trench 221 b formed in the first patterning step. The block mask may be formed to a height of 40 nm or greater and may be formed from photoresist, SiN, or TiN.
  • FIGS. 2E-1 and 2E-2 illustrate respective top (201) and cross-sectional (203) views of the MOL integration stack 205 after the contact trenches 221 and 225 (as shown in FIG. 2D-2) have been etched through the first trench patterning layer 211 down to the contact areas 231 a-231 e (collectively referred to as contact areas 231) of the semiconductor devices 209 and the block masks 229 have been removed. As illustrated in FIG. 2E-1, the contact-to-contact spacing at the tight contact-to-contact spacing points 233 a-233 d correspond to the critical dimensions of the block masks 229 that were used to mask these points (as indicated by the dashed lines). As shown in the cross section view 203, the first trench patterning layer 211 has not been etched in the tight contact-to-contact spacing point 233 c corresponding to the location of the contact trench 221 b) because of the block masking.
  • The embodiments of the present disclosure can achieve several technical effects, including reduced risk of contact-to-contact short at points with tight tip-to-tip spacing, reduced risk of time dependent dielectric breakdown, as well as increased yield. The present disclosure enjoys industrial applicability in fabricating any of various types of highly integrated semiconductor devices, particularly for 20 nm and beyond technology nodes.
  • In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.

Claims (20)

What is claimed is:
1. A device comprising:
a wafer;
one or more semiconductor devices including source/drain regions on the wafer;
a dielectric material between the one or more semiconductor devices;
one or more contact areas, through the dielectric material, having a tight tip-to-tip contact spacing,
wherein the contact areas are formed by:
forming one or more trench patterning layers on a planarized surface of the wafer;
forming one or more trenches in the one or more trench patterning layers;
forming a block mask at one or more points along the one or more trenches;
extending the one or more trenches down to a substrate level of the wafer; and
removing the block mask from the one or more points.
2. The device according to claim 1, wherein the critical dimension of the block mask is 10 nanometers (nm) to 150 nm.
3. The device according to claim 1, wherein the block mask comprises photoresist, silicon nitride (SiN), titanium nitride (TiN), or a combination thereof.
4. The device according to claim 1, wherein the one or more trenches are formed with a double patterning process.
5. The device according to claim 1, wherein the one or more points are associated with a tight tip-to-tip contact spacing parameter.
6. The device according to claim 1, wherein the one or more trenches extend down to one or more contact areas of one or more semiconductor devices formed on the wafer.
7. The device according to claim 1, wherein a first trench patterning layer of a dielectric material is formed to a thickness greater than 10 nanometers (nm).
8. The device according to claim 7, wherein a second trench patterning layer of silicon nitride (SiN), silicon dioxide (SiO2), titanium (Ti) or silicon carbide (SiC) is formed to a thickness greater than 10 nm.
9. The device according to claim 8, wherein the one or more semiconductor devices are beneath the first trench patterning layer and second trench patterning layer.
10. The device according to claim 1, wherein a critical dimension of the block mask corresponds to a tip-to-tip contact spacing.
11. The device according to claim 1, further comprising shallow trench isolation (STI) regions.
12. The device according to claim 1, wherein one or more large contact-to-contact spacings are defined when the one or more first and second trenches are formed.
13. A device comprising:
a wafer;
one or more semiconductor devices including source/drain regions on the wafer;
a dielectric material between the one or more semiconductor devices;
one or more contact areas, through the dielectric material, having a tight tip-to-tip contact spacing,
wherein the contact areas are formed by:
forming one or more trench patterning layers on a planarized surface of the wafer;
forming one or more trenches in the one or more trench patterning layers;
forming a block mask at one or more points along the one or more trenches;
extending the one or more trenches down to one or ore source/drain regions of the one or more semiconductor devices formed on the wafer; and
removing the block mask from the one or more points,
wherein the tip-to-tip contact spacing corresponds to a critical dimension (CD) of the block mask, and
a CD of the block mask is 10 nanometers (nm) to 150 nm.
14. The device of claim 13, wherein the block mask comprises photoresist, SiN, titanium nitride (TiN), or a combination thereof.
15. The device according to claim 13, wherein the one or more trenches are formed with a double patterning process.
16. The device according to claim 13, wherein the one or more points are associated with a tight tip-to-tip contact spacing parameter.
17. The device according to claim 13, wherein a first trench patterning layer comprises a dielectric material and is formed to a thickness greater than 10 nanometers (nm).
18. The device according to claim 17, wherein a second trench patterning layer comprises silicon nitride (SiN), silicon dioxide (SiO2), titanium (Ti) or silicon carbide (SiC) and is formed to a thickness greater than 10 nm.
19. The device according to claim 13, further comprising shallow trench isolation (STI) regions.
20. A device comprising:
a wafer;
one or more semiconductor devices including source/drain regions on the wafer;
shallow trench isolation (STI) regions;
a dielectric material between the one or more semiconductor devices;
one or more contact areas, through the dielectric material, having a tight tip-to-tip contact spacing,
wherein the contact areas are formed by:
forming a first and second trench patterning layers on a planarized surface of the wafer, wherein the first trench patterning layer comprises a dielectric material having a thickness of greater than 10 nanometers (nm), and the second trench patterning layer comprises silicon nitride (SiN), silicon dioxide (SiO2), titanium (Ti) or silicon carbide (SiC) and having a thickness greater than 10 nm;
forming one or more trenches in the one or more trench patterning layers;
forming a block mask at one or more points along the one or more trenches;
extending the one or more trenches down to one or ore source/drain regions of the one or more semiconductor devices formed on the wafer; and
removing the block mask from the one or more points,
wherein the tip-to-tip contact spacing corresponds to a critical dimension (CD) of the block mask, and
a CD of the block mask is 10 nanometers (nm) to 150 nm.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160163634A1 (en) * 2014-10-03 2016-06-09 Edward Seymour Power reduced computing

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9406511B2 (en) * 2014-07-10 2016-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned double patterning
US9589847B1 (en) * 2016-02-18 2017-03-07 International Business Machines Corporation Metal layer tip to tip short
CN107123647B (en) * 2016-02-24 2019-10-18 旺宏电子股份有限公司 High Density Patterning Materials for Integrated Circuits
US9786557B1 (en) 2016-04-12 2017-10-10 International Business Machines Corporation Two-dimensional self-aligned super via integration on self-aligned gate contact
US9793160B1 (en) 2016-07-03 2017-10-17 International Business Machines Coporation Aggressive tip-to-tip scaling using subtractive integraton
US9881926B1 (en) 2016-10-24 2018-01-30 International Business Machines Corporation Static random access memory (SRAM) density scaling by using middle of line (MOL) flow
US9934970B1 (en) * 2017-01-11 2018-04-03 International Business Machines Corporation Self aligned pattern formation post spacer etchback in tight pitch configurations
US12087624B2 (en) 2021-09-21 2024-09-10 International Business Machines Corporation Beol tip-to-tip shorting and time dependent dielectric breakdown

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030214043A1 (en) * 2002-05-17 2003-11-20 Toshio Saitoh Semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6265306B1 (en) * 2000-01-12 2001-07-24 Advanced Micro Devices, Inc. Resist flow method for defining openings for conductive interconnections in a dielectric layer
CN102446748A (en) * 2011-08-04 2012-05-09 上海华力微电子有限公司 Method for reducing minimum line width in spacer-defined double patterning process
KR20130089120A (en) * 2012-02-01 2013-08-09 에스케이하이닉스 주식회사 Methods for fabricating semiconductor device with fine pattenrs

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030214043A1 (en) * 2002-05-17 2003-11-20 Toshio Saitoh Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160163634A1 (en) * 2014-10-03 2016-06-09 Edward Seymour Power reduced computing

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