US20150140778A1

US20150140778A1 - Method for manufacturing metal-insulator-metal capacitor structure

Info

Publication number: US20150140778A1
Application number: US14/580,151
Authority: US
Inventors: Ji Feng; Duan-Quan LIAO; Hai-Long Gu; Ying-Tu Chen
Original assignee: United Microelectronics Corp
Current assignee: United Microelectronics Corp
Priority date: 2011-11-09
Filing date: 2014-12-22
Publication date: 2015-05-21
Also published as: US8946854B2; US20130113075A1

Abstract

A method for manufacturing the MIM capacitor structure is provided. A first damascene electrode layer is formed in the first opening formed in a first dielectric layer. An insulating barrier layer is formed to cover the first dielectric layer and the first damascene electrode layer. A second opening and a third opening are formed in the second dielectric layer formed on the insulating barrier layer. The second opening and the third opening are located above the first damascene electrode layer to expose a portion of the insulating barrier layer therefrom. The insulating barrier layer in the third opening is removed to expose a portion of the first damascene electrode layer. A second damascene electrode layer is formed in the second opening to be contacted with the insulating barrier layer and a dual damascene structure is formed in the third opening to be contacted with the first damascene electrode layer.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This is a divisional application of U.S. patent application Ser. No. 13/292156, filed on Nov. 9, 2011, which is currently pending. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

FIELD OF THE INVENTION

The present invention relates to a capacitor structure, and particularly to a method for manufacturing a metal-insulator-metal (MIM) capacitor structure.

BACKGROUND OF THE INVENTION

Generally, a MIM capacitor comprises two metal electrodes separated by an insulator. The MIM capacitor has advantages of small size, stable capacitor value and little parasitic effect, and so on.
With the development of the integrated circuit technology, the MIM capacitor has been widely used so as to improve the performance of the integrated circuit. Currently, in order to electrically connect the MIM capacitor with other electronic components, the MIM capacitor is usually integrated with an interconnection structure. However, in a conventional process for integrating the MIM capacitor with the interconnection structure, it is necessary to form a number of insulating layers and a number of metal layers. Thus, the conventional process for integrating the MIM capacitor with the interconnection structure a number of depositing steps and etching steps, thereby increasing the production cost and causing the final integrated structure to be complicated.

SUMMARY OF THE INVENTION

The present invention also provides a method for manufacturing a MIM capacitor, which has a simple process so as to reduce the production cost.
The present invention provides a method for manufacturing a MIM capacitor. At first, a first opening is formed in a first dielectric layer. A first damascene electrode layer is filled in the first opening. Next, an insulating barrier layer is formed to cover the first dielectric layer and the first damascene electrode layer. Next, a second dielectric layer is formed on the insulating barrier layer. Next, a second opening and a third opening are formed in the second dielectric layer formed on the insulating barrier layer. The second opening and the third opening are located above the first damascene electrode layer to expose a portion of the insulating barrier layer therefrom. Next, the insulating barrier layer in the third opening is removed to expose a portion of the first damascene electrode layer. Next, a second damascene electrode layer is formed in the second opening to be contacted with the insulating barrier layer and a dual damascene structure is formed in the third opening to be contacted with the first damascene electrode layer.
In one embodiment of the present invention, the step of filling the first damascene electrode layer in the first opening includes: forming a metal layer on the first dielectric layer and filling the metal layer into the first opening; and removing a portion of the metal layer outside the first opening to form the first damascene electrode layer.
In one embodiment of the present invention, a chemical mechanical polishing process is applied to remove the portion of the metal layer outside the first opening to form the first damascene electrode layer.
In one embodiment of the present invention, the metal layer is a copper layer.
In one embodiment of the present invention, the step of forming the insulating barrier layer to cover the first dielectric layer and the first damascene electrode layer includes: forming the insulating barrier layer in a single layer structure, and a material of the insulating barrier layer is selected from a group consisting of silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN) and silicon oxynitride (SiON).
In one embodiment of the present invention, the step of forming the insulating barrier layer to cover the first dielectric layer and the first damascene electrode layer includes forming the insulating barrier layer in a multilayer structure.
In one embodiment of the present invention, forming the insulating barrier layer in the multilayer structure includes the following steps. At first, a first insulating layer is formed on the first dielectric layer, and a material of the first insulating layer is selected from a group consisting of silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN) and silicon oxynitride (SiON). Next, a second insulating layer is formed on the first insulating layer, and a material of the second insulating layer is selected from a group consisting of undoped silicate glass (USG), tantalum oxide (Ta₂O₅), zirconium oxide (ZrO₂) and aluminum oxide (Al₂O₃).
In one embodiment of the present invention, forming the third opening in the second dielectric layer includes: forming at least one via; and forming one trench located above and communicated with the at least one via.
In one embodiment of the present invention, the third opening is formed by a trench first process, a via first process or a self-aligned process.
In one embodiment of the present invention, the step of removing the insulating barrier layer in the third opening to expose the portion of the first damascene electrode layer includes the following steps. At first, a patterned mask layer is formed on the second dielectric layer to cover the second opening and to expose the third opening. Next, the portion of the insulating barrier layer exposed from the patterned mask is removed. Next, the patterned mask layer is removed.
In one embodiment of the present invention, the step of forming a second damascene electrode layer in the second opening and forming a dual damascene structure in the third opening includes the following steps. At first, a metal layer is formed on the second dielectric layer and is filled into the second opening to be contacted with the insulating barrier layer and into the third opening to be contacted with the first damascene electrode layer. Then, a portion of the metal layer outside the second opening and the third opening is removed to form the second damascene electrode layer and the dual damascene structure.
In one embodiment of the present invention, a chemical mechanical polishing process is applied to remove the portion of the metal layer outside the second opening and the third opening to form the second damascene electrode layer and the dual damascene structure.
In one embodiment of the present invention, the metal layer is a copper layer.
In the method for manufacturing the MIM capacitor according to the embodiments of the present invention, the first damascene electrode layer and the second damascene electrode layer are both formed by a damascene process and are separated by the insulating barrier layer. The insulating barrier can serve as not only an insulator of the MIM capacitor, but also an etch stop layer during forming the second damascene electrode layer. Thus, the MIM capacitor has a simpler structure, thereby reducing the production cost. The MIM capacitor further includes the dual damascene structure formed in the second dielectric layer and the insulating barrier layer and electrically connected to the first damascene electrode layer. The dual damascene structure and the second damascene electrode layer can be formed in a common step. Thus, the process of integrating the MIM capacitor with an interconnection structure can be simplified, thereby reducing the production cost.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:

FIGS. 1A-1E illustrate a process flow of a method for manufacturing a MIM capacitor in accordance with a first embodiment of the present invention.

FIG. 2 illustrates a schematic view of a MIM capacitor with an interconnection structure fabricated in accordance with the first embodiment of the present invention.

FIGS. 3A-3H illustrate a process flow of a method for manufacturing a MIM capacitor in accordance with a second embodiment of the present invention.

FIG. 4 illustrates a schematic view of a MIM capacitor with an interconnection structure fabricated in accordance with the second embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed.
FIGS. 1A-1E illustrate a process flow of a method for manufacturing a MIM capacitor in accordance with a first embodiment of the present invention.
Referring to FIG. 1A, in the present embodiment, for example, a first damascene electrode layer 120 is formed in a first dielectric layer 110 by a damascene process. In detail, at first, a first opening 112 is formed in the first dielectric layer 110. Then, a metal layer (e.g., a copper layer) is formed on the first dielectric layer 110 and filled into the first opening 112. Thereafter, a chemical mechanical polishing process is applied to the metal layer so that a portion of the metal layer outside the first opening 112 is removed. Thus, the first damascene electrode layer 120 is formed and filled in the first opening 112. In the present embodiment, the first damascene electrode layer 120 is a copper damascene layer.
Referring to FIG. 1B, next, an insulating barrier layer 130 is formed to cover the first dielectric layer 110 and the first damascene electrode layer 120. The insulating barrier layer 130 is a single layer structure. A material of the insulating barrier layer 130 can include silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxynitride (SiON) or other high dielectric constant materials. In the present embodiment, a dielectric constant of the insulating barrier layer 130 is, for example, 5. A thickness of the insulating barrier layer 130 is in a range from 200 to 1500 angstroms.
Referring to FIG. 1C, next, a second dielectric 140 is formed on and contacted with the insulating barrier layer 130. In the present embodiment, a material of the second dielectric 140 and a material of the first dielectric layer 110 are, for example, oxide.
Referring to FIG. 1D to FIG. 1E, in the present embodiment, for example, a second damascene electrode layer 150 is formed in the second dielectric layer 140 by a damascene process. In detail, at first, referring to FIG. 1D, a second opening 142 is formed in the second dielectric layer 140 and is located above the first damascene electrode layer 120 so as to expose a portion of the insulating barrier layer 130.
During forming the second opening 142 in the second dielectric layer 140, the insulating barrier layer 130 can serve as an etch stop layer. That is, due to the etching selectivity of the second dielectric layer 140 and the insulating barrier layer 130, the etching process for forming the second opening 142 in the second dielectric layer 140 will stop on the insulating barrier layer 130. Thus, after the second opening 142 is formed, a portion of insulating barrier layer 130 is exposed from the second opening 142.
Referring to FIG. 1E, next, a metal layer (e.g., a copper layer) is formed on the second dielectric layer 140 and filled into the second opening 142 to cover the portion of the insulating barrier layer 230 exposed from the second opening 142. Then, a chemical mechanical polishing process is applied to the metal layer so that a portion of the metal layer outside the second opening 142 is removed. Thus, the second damascene electrode layer 150 contacted with the insulating barrier layer 130 is formed and filled in the second opening 142. In the present embodiment, the second damascene electrode layer 150 is a copper damascene layer.
After the second damascene electrode layer 150 is formed, the MIM capacitor 100 is manufactured by the method in accordance with the first embodiment. In detail, the MIM capacitor 100 includes the first dielectric layer 110, the first damascene electrode layer 120, the insulating barrier layer 130, the second dielectric layer 140 and the second damascene electrode layer 150. The first damascene electrode layer 120 is formed in the first dielectric layer 110. The insulating barrier layer 130 covers the first dielectric layer 110 and the first damascene electrode layer 120, and is the single layer structure. The second dielectric layer 140 is formed on and contacted with the insulating barrier layer 130. The second damascene electrode layer 150 is formed in the second dielectric layer 140, is located above the first damascene electrode layer 120 and is contacted with the insulating barrier layer 130.
Particularly, in the MIM capacitor 100, the insulating barrier layer 130 can further serve as a capacitor dielectric layer between the first damascene electrode layer 120 and the second damascene electrode layer 150. In other words, in the method for manufacturing the MIM capacitor 100, it is not necessary to deposit extra dielectric layers between the two electrode layers (i.e., the first damascene electrode layer 120 and the second damascene electrode layer 150). Thus, the method can reduce the production cost of the MIM capacitor and manufacture the MIM capacitor 100 with a simple structure.
It is noted that, during forming the second opening 142, a portion of the insulating barrier layer 130 can be etched due to an over etch effect. Thus, after forming the second opening 142, a final thickness of the insulating barrier layer 130 is determined by an original deposition thickness of the insulating barrier layer 130 and an etching rate of an etchant for etching the second dielectric layer 140 to the insulating barrier layer 130.
According to the method for manufacturing the MIM capacitor 100, it is also noted that, the fabrication of the MIM capacitor 100 can be integrated with a fabrication of an interconnection structure. FIG. 2 illustrates a schematic view of a MIM capacitor with an interconnection structure of an integrated circuit. Referring to FIG. 2, in the present embodiment, an interconnection structure 30, for example, a dual damascene interconnection structure, is shown, which includes conductive wire layers 31, 32 and contact plugs 33, 34 electrically connecting the first conductive layers 31, 32. To integrate the process, the interconnection structure 30 is formed in the first dielectric layer 110 and the second dielectric layer 140. The conductive wire layer 31 and the contact plug 33 can be formed in the process of forming the first damascene electrode layer 120. The conductive wire layer 32 and the contact plug 34 can be formed in the process of forming the second damascene electrode layer 150. It is noted that, the insulating barrier layer 130 may not formed in the region for forming the interconnection structure 30.
FIGS. 3A-3H illustrate a process flow of a method for manufacturing a MIM capacitor in accordance with a second embodiment of the present invention.
Referring to FIG. 3A, in the present embodiment, for example, a first damascene electrode layer 220 is formed in a first dielectric layer 210 by a damascene process. In detail, at first, a first opening 212 is formed in the first dielectric layer 210. Then, a metal layer (e.g., a copper layer) is formed on the first dielectric layer 210 and filled into the first opening 212. Thereafter, a chemical mechanical polishing process is applied to the metal layer so that a portion of the metal layer outside the first opening 212 is removed. Thus, the first damascene electrode layer 220 is formed and filled in the first opening 212. In the present embodiment, the first damascene electrode layer 220 is a copper damascene layer.
Referring to FIG. 3B, next, an insulating barrier layer 230 is formed to cover the first dielectric layer 210 and the first damascene electrode layer 220. The insulating barrier layer 230 can be a single layer structure. A material of the insulating barrier layer 230 can include silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxynitride (SiON) or other high dielectric constant materials. A thickness of the insulating barrier layer 130 is in a range from 200 to 1500 angstroms. The insulating barrier layer 230 can also be a multilayer structure, for example, including a first insulating layer (not shown) and a second insulating layer (not shown). The first insulating layer is formed on the first dielectric layer 210 and the first damascene electrode layer 220 and the second insulating layer is formed on the first insulating layer. A material of the first insulating layer is selected from a group consisting of silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN) and silicon oxynitride (SiON). A material of the second insulating layer is selected from a group consisting of undoped silicate glass (USG), tantalum oxide (Ta₂O₅), zirconium oxide (ZrO₂) and aluminum oxide (Al₂O₃). A thickness of the first insulating layer is in a range from 200 to 1500 angstroms. A thickness of the second insulating layer is in a range from 100 to 1000 angstroms.
Referring to FIG. 3C, next, a second dielectric 240 is formed on and contacted with the insulating barrier layer 230. In the present embodiment, a material of the second dielectric 240 and a material of the first dielectric layer 210 are, for example, oxide. The method for manufacturing the MIM capacitor in the second embodiment is similar to the method for manufacturing the MIM capacitor in the first embodiment except the following steps after forming the second dielectric 240.
Referring to FIG. 3D to FIG. 3H, in the present embodiment, for example, a second damascene electrode layer 250 is formed in the second dielectric layer 240 by a damascene process and a dual damascene structure 260 is formed in the second dielectric layer 240 and the insulating barrier layer 230 by a dual damascene process. It is noted that, in fact, the second damascene electrode layer 250 and the dual damascene structure 260 are formed in a common damascene process.
In detail, referring to FIG. 3D, a second opening 242 and a third opening 244 are formed in the second dielectric layer 240 and are located above the first damascene electrode layer 220 so as to expose a portion of the insulating barrier layer 230, respectively. The third opening 244 includes at least a via 246 and a trench 245 located above and communicated with the via 246. In the present embodiment, the third opening 244 includes one trench 245 and one via corresponding to the one trench 245. In another embodiment, the third opening can also includes one trench and a number of vias. In other words, the number and the location of the trench 245 and the via 246 are determined by the interconnection demand. It is noted that, the third opening 244 can be formed by a trench first process, a via first process or a self-aligned process, which are not described here.
For example, the second opening 242 and the third opening 244 can be formed by a photolithography process. During forming the second opening 242 and the third opening 244 in the second dielectric layer 140, the insulating barrier layer 230 can serve as an etch stop layer. That is, due to the etching selectivity of the second dielectric layer 240 and the insulating barrier layer 230, the etching process for forming the second opening 242 and the third opening 244 in the second dielectric layer 240 will stop on the insulating barrier layer 230. Thus, after the second opening 242 and the third opening 244 are formed, a portion of insulating barrier layer 230 is exposed from the second opening 242 and the third opening 244, respectively.
It is noted that, during forming the second opening 242 and the third opening 244, a portion of the insulating barrier layer 230 can be etched due to an over etch effect. Thus, after forming the second opening 242 and the third opening 244, a final thickness of the insulating barrier layer 230 is determined by an original deposition thickness of the insulating barrier layer 230 and an etching rate of an etchant for etching the second dielectric layer 240 to the insulating barrier layer 230.
Next, the portion of the insulating barrier layer 230 exposed from the third opening 244 is removed so as to expose a portion of the first damascene electrode layer 220, thereby forming the dual damascene opening 262. In the present embodiment, referring to FIG. 3E, a patterned mask layer 270 is formed on the second dielectric layer 240 to cover the second dielectric layer 240 and the second opening 242 and to expose the third opening 244. For example, a material of the patterned mask layer 270 can be a photoresist material.
Referring to FIG. 3F, next, the portion of the insulating barrier layer 230 exposed from the patterned mask 270 is removed. For example, an etchant for etching the insulating barrier layer 230 is selected to etch the insulating barrier layer 230 exposed from the patterned mask 270 so that the portion of the insulating barrier layer 230 exposed from the patterned mask 270 is removed so as to expose the portion of the first damascene electrode layer 220. It is noted that, other suitable method for removing the portion of the insulating barrier layer 230 exposed from the patterned mask 270 can also be used. Referring to 3G, next, the patterned mask layer 270 is removed, thereby forming the dual damascene opening 262 in the second dielectric layer 240 and the insulating barrier layer 230.
Referring to FIG. 3H, next, a metal layer (e.g., a copper layer) is formed on the second dielectric layer 240 and is filled into the second opening 242 to cover the portion of the insulating barrier layer 230 exposed from the second opening 242 and is filled into the dual damascene opening 262 to cover the portion of the first damascene electrode layer 220 exposed from the dual damascene opening 262. Then, a chemical mechanical polishing process is applied to the metal layer so that a portion of the metal layer outside the second opening 242 and the dual damascene opening 262 is removed. Thus, the second damascene electrode layer 250 contacted with the insulating barrier layer 230 is formed and filled in the second opening 242, and the dual damascene structure 260 electrically connected to the first damascene electrode layer 220 is formed and filled in the dual damascene opening 262. In the present embodiment, the second damascene electrode layer 250 is a copper damascene layer, and the dual damascene structure 260 is a copper dual damascene layer. That is, a material of the second damascene electrode layer 250 is identical to a material of the dual damascene structure 260.
Still, referring to FIG. 3H, the MIM capacitor 200 is manufactured by the method in accordance with the second embodiment. The MIM capacitor 200 includes the first dielectric layer 210, the first damascene electrode layer 220, the insulating barrier layer 230, the second dielectric layer 240, the second damascene electrode layer 250 and the dual damascene structure 260. The first damascene electrode layer 220 is filled in the first dielectric layer 210. The insulating barrier layer 230 is formed on the first dielectric layer 210 and the first damascene electrode layer 220. The second dielectric layer 240 is formed on the insulating barrier layer 230. The second damascene electrode layer 250 is formed in the second dielectric layer 240, is located above the first damascene electrode layer 220 and is contacted with the insulating barrier layer 230. The dual damascene structure 260 is formed in the second dielectric layer 240 and the insulating barrier layer 230, is located above the first damascene electrode layer 220 and is electrically connected to the first damascene electrode layer 220.
In the present embodiment, the second damascene electrode layer 250 and the dual damascene structure 260 are formed at the same time by using a dual damascene process. Thus, it is not necessary to deposit extra dielectric layers and metal layers, thereby simplifying the MIM capacitor 200 with the interconnection structure and reducing the production cost. Thus, the method can reduce the production cost of the MIM capacitor and manufacture the MIM capacitor 100 with a simple structure. Furthermore, the insulating barrier layer 230 can further serve as an etch stop layer and a capacitor dielectric layer between the first damascene electrode layer 220 and the second damascene electrode layer 250. In other words, in the method for manufacturing the MIM capacitor 200, it is not necessary to deposit extra dielectric layers between the two electrode layers (i.e., the first damascene electrode layer 220 and the second damascene electrode layer 250).
According to the method for manufacturing the MIM capacitor 200, it is also noted that, the fabrication of the MIM capacitor 200 can be integrated with a fabrication of an interconnection structure of an integrated circuit. FIGS. 4 illustrate a schematic view of a MIM capacitor with an interconnection structure of an integrated circuit. Referring to FIG. 4, in the present embodiment, an interconnection structure 40, for example, a dual damascene interconnection structure, is shown, which includes conductive wire layers 41, 42 and contact plugs 43, 44 electrically connecting the conductive layers 41, 42. To integrate the process, the interconnection structure 40 is formed in the first dielectric layer 210 and the second dielectric layer 240. The first conductive wire layer 41 and the contact plug 43 can be formed in the process of forming the second damascene electrode layer 250 and the dual damascene structure 260, the second conductive wire layer 42 and the contact plug 44 can be formed in the process of forming the first damascene electrode layer 220. It is noted that, the insulating barrier layer 230 may not formed in the region for forming the interconnection structure 40.
In the MIM capacitor and the method for manufacturing the MIM capacitor of the present invention, the first damascene electrode layer and the second damascene electrode layer are both formed by a damascene process and are separated by the insulating barrier layer. The insulating barrier can serve as not only an insulator of the MIM capacitor, but also an etch stop layer during forming the second damascene electrode layer. Thus, the MIM capacitor has a simple structure, thereby reducing the production cost. In another embodiment, the MIM capacitor can further includes the dual damascene structure formed in the second dielectric layer and the insulating barrier layer and electrically connected to the first damascene electrode layer. The dual damascene structure and the second damascene electrode layer can be formed in a common step. Thus, the process of integrating the MIM capacitor with an interconnection structure can be simplified, thereby reducing the production cost.
While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.

Claims

What is claimed is:

1. A method for manufacturing a MIM capacitor, comprising:

forming a first opening in a first dielectric layer;

filling a first damascene electrode layer in the first opening;

forming an insulating barrier layer to cover the first dielectric layer and the first damascene electrode layer;

forming a second dielectric layer on the insulating barrier layer;

forming a second opening and a third opening in the second dielectric layer, the second opening and the third opening being located above the first damascene electrode layer to expose a portion of the insulating barrier layer therefrom;

removing the insulating barrier layer in the third opening to expose a portion of the first damascene electrode layer; and

forming a second damascene electrode layer in the second opening to be contacted with the insulating barrier layer and forming a dual damascene structure in the third opening to be contacted with the first damascene electrode layer.

2. The method as claimed in claim 1, wherein the step of filling the first damascene electrode layer in the first opening comprises:

forming a metal layer on the first dielectric layer and filling the metal layer into the first opening; and

removing a portion of the metal layer outside the first opening to form the first damascene electrode layer.

3. The method as claimed in claim 2, wherein a chemical mechanical polishing process is applied to remove the portion of the metal layer outside the first opening to form the first damascene electrode layer.

4. The method as claimed in claim 2, wherein the metal layer is a copper layer.

5. The method as claimed in claim 1, wherein the step of forming the insulating barrier layer to cover the first dielectric layer and the first damascene electrode layer comprises: forming the insulating barrier layer in a single layer structure, and wherein a material of the insulating barrier layer is selected from a group consisting of silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN) and silicon oxynitride (SiON).

6. The method as claimed in claim 1, wherein the step of forming the insulating barrier layer to cover the first dielectric layer and the first damascene electrode layer comprises of forming the insulating barrier layer in a multilayer structure.

7. The method as claimed in claim 6, wherein forming the insulating barrier layer in the multilayer structure comprises:

forming a first insulating layer on the first dielectric layer, and wherein a material of the first insulating layer is selected from a group consisting of silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN) and silicon oxynitride (SiON); and

forming a second insulating layer on the first insulating layer, and wherein a material of the second insulating layer is selected from a group consisting of undoped silicate glass (USG), tantalum oxide (Ta₂O₅), zirconium oxide (ZrO₂) and aluminum oxide (Al₂O₃).

8. The method as claimed in claim 1, wherein forming the third opening in the second dielectric layer comprising: forming at least one via; and

forming one trench located above and communicated with the at least one via.

9. The method as claimed in claim 8, wherein the third opening is formed by a trench first process, a via first process or a self-aligned process.

10. The method as claimed in claim 1, wherein the step of removing the insulating barrier layer in the third opening to expose the portion of the first damascene electrode layer comprises:

forming a patterned mask layer on the second dielectric layer to cover the second opening and to expose the third opening;

removing the portion of the insulating barrier layer exposed from the patterned mask; and

removing the patterned mask layer.

11. The method as claimed in claim 1, wherein the step of forming a second damascene electrode layer in the second opening and forming a dual damascene structure in the third opening comprises:

forming a metal layer on the second dielectric layer and filling the metal layer into the second opening to be contacted with the insulating barrier layer and into the third opening to be contacted with the first damascene electrode layer; and

removing a portion of the metal layer outside the second opening and the third opening to form the second damascene electrode layer and the dual damascene structure.

12. The method as claimed in claim 11, wherein a chemical mechanical polishing process is applied to remove the portion of the metal layer outside the second opening and the third opening to form the second damascene electrode layer and the dual damascene structure.

13. The method as claimed in claim 11, wherein the metal layer is a copper layer.