[go: up one dir, main page]

US20140231997A1 - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

Info

Publication number
US20140231997A1
US20140231997A1 US14/021,002 US201314021002A US2014231997A1 US 20140231997 A1 US20140231997 A1 US 20140231997A1 US 201314021002 A US201314021002 A US 201314021002A US 2014231997 A1 US2014231997 A1 US 2014231997A1
Authority
US
United States
Prior art keywords
layer
interlayer
semiconductor device
semiconductor
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US14/021,002
Inventor
Fumio Sasaki
Hisao Kawasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KAWASAKI, HISAO, SASAKI, FUMIO
Publication of US20140231997A1 publication Critical patent/US20140231997A1/en
Priority to US14/822,224 priority Critical patent/US9269619B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05025—Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05169—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/257—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes

Definitions

  • An embodiment relates to a semiconductor device and a method for manufacturing the same.
  • an electrode provided on a surface of the semiconductor layer and a back electrode provided on a back surface of the semiconductor layer are electrically connected using a via hole.
  • a surface side electrode is grounded and operation of the semiconductor device is stabilized.
  • the surface side electrode consists of an alloy layer containing gold germanium (AuGe), nickel (Ni) and gold (Au), and a reaction layer which is formed by reaction of the alloy layer and the semiconductor layer.
  • a hole of the via hole is formed by etching the semiconductor layer selectively using an RIE (Reactive Ion Etching) method, for example.
  • Etching gas contains chlorine, for example.
  • the surface side electrode may deform with the heat at the time of mounting the semiconductor device on a package or a mounting board, and thereby a contact between the surface side electrode and the back electrode may become unstable.
  • the embodiment supplies a reliable semiconductor device in which a connection between a surface side electrode and a back electrode through a via hole is stable.
  • FIGS. 1A and 1B are schematic diagrams showing a semiconductor device concerning an embodiment
  • FIG. 2 is a flow chart showing a manufacture process of the semiconductor device concerning the embodiment
  • FIGS. 3A-3F are schematic sectional views showing the manufacture process of the semiconductor device concerning the embodiment.
  • FIGS. 4A and 4B are schematic sectional views showing a semiconductor device concerning a comparative example.
  • a semiconductor device includes a semiconductor layer, an interlayer, an electrode provided on the interlayer, and an electrical conductive layer which is electrically connected to the electrode.
  • the semiconductor layer has a first surface and a second surface which is opposite to the first surface.
  • the interlayer is provided on the first surface, and includes a metal layer consisting of only metal whose standard oxidation-reduction potential is not lower than 0 (zero) V in an ionization tendency.
  • the electrical conductive layer covers an inside of a hole which is formed in the semiconductor layer so as to reach the interlayer from the second surface, and is electrically connected to the electrode via the interlayer which is exposed to a bottom of the hole.
  • FIG. 1A and FIG. 1B are schematic diagrams showing a semiconductor device 1 concerning the embodiment.
  • FIG. 1A is a top view showing a part of the semiconductor device.
  • FIG. 1B is a sectional view taken along line 1 B - 1 B shown in FIG. 1A .
  • the semiconductor device 1 is a field effect transistor, for example, and is provided with a functional part 7 and a pad electrode 10 .
  • the functional part 7 contains source electrodes 3 , drain electrodes 4 , and gate electrodes 5 .
  • the pad electrode 10 is connected to a plurality of the source electrodes 3 .
  • the semiconductor device 1 is provided with a semiconductor layer 20 , an electrical conductive layer 30 , and an interlayer 40 .
  • the semiconductor layer 20 has a first surface 20 a , and a second surface 20 b that is opposite to the first surface 20 a.
  • the interlayer 40 is formed in contact with the first side 20 a of the semiconductor layer 20 .
  • the pad electrode 10 is formed on the interlayer 40 .
  • Another layer which has conductivity may be provided between the pad electrode 10 and the interlayer 40 .
  • the semiconductor layer 20 has a via hole 17 .
  • the via hole 17 includes a hole 17 a which penetrates the semiconductor layer 20 in the direction facing to the pad electrode 10 from the second surface 20 b and reaches the interlayer 40 from the second surface 20 b, and a via contact 30 a which covers an inside of the hole 17 a.
  • the electrical conductive layer 30 contains the via contact 30 a and a back electrode 30 b provided on the second surface 20 a.
  • the via contact 30 a is in contact with the interlayer 40 which is exposed to a bottom 17 b of the hole 17 a.
  • the interlayer 40 is an electrical conductive layer containing platinum (Pt), for example, and the electrical conductive layer 30 is electrically connected to the pad electrode 10 via the interlayer 40 .
  • the interlayer 40 contains a metal layer 13 and a reaction layer 15 which is formed by reaction of the metal layer 13 and the semiconductor layer 20 .
  • the electrical conductive layer 30 is in contact with the reaction layer 15 .
  • the reaction layer 15 may be removed at the bottom 17 b of the hole 17 and the electrical conductive layer 30 may be contact with the metal layer 13 directly.
  • the metal layer 13 consists of only metal whose standard oxidation-reduction potential is not lower than 0 (zero) V in an ionization tendency, for example.
  • the interlayer 40 is apart from the functional part 7 which is electrically connected to the pad electrode 10 . That is, the interlayer 40 should just be under the pad electrode 10 , and does not need to be provide under the functional part 7 and a part which connects the functional part 7 and the pad electrode 10 .
  • FIG. 2 is a flow chart showing the manufacture process of the semiconductor device 1 concerning the embodiment.
  • FIGS. 3A-3F are schematic sectional views showing the manufacture process of the semiconductor device concerning the embodiment.
  • FIGS. 3A-3F correspond to steps 01-06 shown in FIG. 2 and show partial cross section of a wafer in each step.
  • the metal layer 13 is formed on the first surface 20 a of the semiconductor layer 20 as shown in FIG. 3A (S 01 ).
  • the semiconductor layer 20 is a high resistance layer of semi-insulation, and gallium arsenide (GaAs), indium phosphate (InP), or gallium nitride (GaN) can be used as the semiconductor layer 20 , for example. Also, a GaAs board or InP board of semi-insulation may be sufficient as the semiconductor layer 20 .
  • GaAs gallium arsenide
  • InP indium phosphate
  • GaN gallium nitride
  • the metal layer 13 is selectively formed on a part of the semiconductor layer 20 on which the pad electrode 10 is formed.
  • the metal layer 13 is desirable to have tolerance for the dry etching which is used for formation of the hole 17 a for the via hole 17 . That is, a metal which is chemically stable and does not react to the active element contained in an etching gas is used as the metal layer 13 .
  • the etching gas contains chlorine when the semiconductor layer 20 is a GaAs layer or an InP layer, for example. Therefore, it is preferable to use platinum (Pt) which is stable chemically to chlorine as the metal layer 13 .
  • the specific resistance of platinum is larger than the specific resistance of gold (Au) which is used for the pad electrode 10 .
  • Au gold
  • the thickness of the metal layer 13 it is desirable that it is not larger than 60 nm, for example.
  • the reaction layer 15 containing platinum is formed between the semiconductor layer 20 and the metal layer 13 .
  • the pad electrode 10 is formed on the metal layer 13 (S 03 ).
  • the pad electrode 10 is a source pad, for example, and is formed so as to be connected to the source electrodes 3 .
  • An Au layer can be used as the pad electrode 10 , for example.
  • the semiconductor layer 20 is thinned (S 04 ).
  • the semiconductor layer 20 is thinned to thickness of several 10 ⁇ m by grinding or polishing.
  • an epitaxially grown layer separated from a growth board may be used as the semiconductor layer 20 .
  • the hole 17 a is formed in the direction which faces to the pad electrode 10 from the second surface 20 b of the semiconductor layer 20 which has been thinned (S 05 ).
  • the semiconductor layer 20 is selectively etched using the RIE (Reactive Ion Etching) method, for example, to thereby form the hole 17 a.
  • An etching gas contains chlorine, for example.
  • the hole 17 a reaches either of the reaction layer 15 and the metal layers 13 .
  • the reaction layer 15 contains platinum.
  • the etching rate of the reaction layer 15 becomes lower than the etching rate of the semiconductor layer 20 . Thereby, it becomes easy to stop etching at the reaction layer 15 . That is, the reaction layer 15 can be exposed to the second surface side of the semiconductor layer 20 . Also, the reaction layer 15 may be removed to thereby expose the metal layer 13 .
  • the electrical conductive layer 30 which covers the inside of the hole 17 a is formed and thereby the via hole 17 is formed (S 06 ).
  • the electrical conductive layer 30 is a gold plate layer, for example.
  • a seed layer 21 is formed on the inside of the hole 17 a and the second surface 20 b, for example.
  • electrolytic plating of gold is performed while flowing current through the seed layer 21 and a gold plate layer is formed on the seed layer 21 .
  • a two-layer film in which titanium (Ti) and gold (Au) are laminated in order from the semiconductor layer 20 side can be used as the seed layer 21 , for example.
  • Ti film raises the adhesion power between the semiconductor layer 20 and the electrical conductive layer 30 , and raises the adhesion power between the reaction layer 15 and the electrical conductive layer 30 .
  • the above-mentioned manufacture process can form a via-structure which electrically connects the pad electrode 10 provided on first surface 20 a of the semiconductor layer 20 and the electrical conductive layer 30 provided in the second surface 20 b side.
  • FIGS. 4A and 4B are schematic sectional views showing a semiconductor device 2 concerning a comparative example.
  • FIG. 4A shows a cross section (refer to FIG. 1B ) taken along an I B -I B line.
  • FIG. 4B is an enlarged drawing of a part A shown in FIG. 4A , and shows a connection structure between the pad electrode 10 and the electrical conductive layer 30 .
  • the semiconductor device 2 includes a metal layer 23 and a reaction layer 25 .
  • the metal layer 23 contains a metal whose standard oxidation-reduction potential is lower than 0 (zero) V in an ionization tendency, for example.
  • the reaction layer 25 contains a metal whose standard oxidation-reduction potential is lower than 0 (zero) V in an ionization tendency, for example.
  • the metal layer 23 contains gold germanium (AuGe), nickel (nickel) and gold (Au) which were laminated in order from the semiconductor layer 20 side, for example, because the semiconductor device 2 uses a metal layer which is simultaneously formed with the ohmic electrode as a surface side electrode. That is, the metal layer 23 contains nickel which reacts chemically with chlorine. And the reaction layer 25 which is formed by heat-treating the metal layer 23 and the semiconductor layer 20 also contains nickel.
  • the semiconductor layer 20 is etched in the direction which faces to the pad electrode 10 from the second surface 20 b of the semiconductor layer 20 by dry etching and thereby the hole 17 a is formed. And the reaction layer 25 is exposed to the second surface 20 b side. At this time, nickel contained in the reaction layer 25 reacts with chlorine contained in an etching gas, and thereby chlorination nickel (NiCl2) is produced on an exposed surface of the reaction layer 25 .
  • Chlorination nickel corrodes the reaction layer 25 in the formation process of the electrical conductive layer 30 , and forms voids 31 in the surface of the reaction layer 25 as shown in FIG. 4B .
  • plating liquid enters into the voids 31 in the process of gold-plating which forms an electrical conductive layer 30 , and the plating liquid may remain in the void 31 as it is.
  • the plating liquid which remains inside the void 31 evaporate to thereby raise the internal pressure of the void 31 .
  • the phenomenon in which the reaction layer 25 is dissociated from the electrical conductive layer 30 , and in which the reaction layer 25 , the metal layer 23 and pad electrode 10 are inflated occurs.
  • an electrical connection between the electrical conductive layer 30 and the pad electrode 10 may be lost, and operation of the semiconductor device 2 may become unstable.
  • the metal layer 13 is chemically stable to chlorine contained in the etching gas. That is, the metal layer 13 does not contain any element that reacts with the active element contained in the etching gas. Even if the metal layer 13 contains such an element that reacts with the active element contained in the etching gas, the concentration of such element is not higher than a level detectable using the measuring means, such as an SIMS (Secondary Ion Mass Spectrometry) and a Auger spectroscopy.
  • SIMS Single Ion Mass Spectrometry
  • the reaction layer 15 that is formed by reaction of the metal layer 13 and the semiconductor layer 20 does not contain any unstable element to chlorine contained in the etching gas. For this reason, the void 31 is not formed between the reaction layer 15 and the electrical conductive layer 30 , and deformation of the reaction layer 15 , the metal layer 13 and the pad electrode 10 can be suppressed. And the electrical connection between the electrical conductive layer 30 and the pad electrode 10 is held stable, and the reliability of the semiconductor device can be improved.
  • a metal which is chemically unstable to chlorine contained in the etching gas is metal whose standard oxidation-reduction potential is lower than 0 (zero) V in an ionization tendency.
  • a metal which is chemically stable to chlorine contained in the etching gas is a metal whose standard oxidation-reduction potential is not lower than 0 (zero) V in an ionization tendency. Copper (Cu), palladium (Pd), platinum (Pt), gold (Au), etc. out of the metals used in a semiconductor process in many cases, correspond to such a metal.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

A semiconductor device concerning the embodiment includes a semiconductor layer which has a first surface and a second surface which is opposite to the first surface, an interlayer which is provided on the first surface and which consists of only metal whose standard oxidation-reduction potential is not lower than 0 (zero) V in an ionization tendency, and an electrode provided on the interlayer. The semiconductor device further includes an electrical conductive layer which covers an inside of a hole which is formed in the semiconductor layer so as to reach the interlayer the interlayer from the second surface, and which is electrically connected to the electrode via the interlayer which is exposed to a bottom of the hole.

Description

    CROSS-REFERENCE TO RELATED APPLICATION(S)
  • This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2013-032528, filed on Feb. 21, 2013, and the prior Japanese Patent Application No. 2013-109204, filed on May 23, 2013, the entire contents of which are incorporated herein by reference.
    • FIELD
  • An embodiment relates to a semiconductor device and a method for manufacturing the same.
    • BACKGROUND
  • As for a lateral semiconductor device in which current flows in the parallel direction to a surface of a semiconductor layer, an electrode provided on a surface of the semiconductor layer and a back electrode provided on a back surface of the semiconductor layer are electrically connected using a via hole. Thereby, a surface side electrode is grounded and operation of the semiconductor device is stabilized. Since a metal layer which is simultaneously formed with an ohmic electrode is generally used as the surface side electrode, the surface side electrode consists of an alloy layer containing gold germanium (AuGe), nickel (Ni) and gold (Au), and a reaction layer which is formed by reaction of the alloy layer and the semiconductor layer. A hole of the via hole is formed by etching the semiconductor layer selectively using an RIE (Reactive Ion Etching) method, for example. Etching gas contains chlorine, for example.
  • The surface side electrode may deform with the heat at the time of mounting the semiconductor device on a package or a mounting board, and thereby a contact between the surface side electrode and the back electrode may become unstable.
  • The embodiment supplies a reliable semiconductor device in which a connection between a surface side electrode and a back electrode through a via hole is stable.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1A and 1B are schematic diagrams showing a semiconductor device concerning an embodiment;
  • FIG. 2 is a flow chart showing a manufacture process of the semiconductor device concerning the embodiment;
  • FIGS. 3A-3F are schematic sectional views showing the manufacture process of the semiconductor device concerning the embodiment; and
  • FIGS. 4A and 4B are schematic sectional views showing a semiconductor device concerning a comparative example.
    •  DETAILED DESCRIPTION
  • According to an embodiment, a semiconductor device includes a semiconductor layer, an interlayer, an electrode provided on the interlayer, and an electrical conductive layer which is electrically connected to the electrode. The semiconductor layer has a first surface and a second surface which is opposite to the first surface. The interlayer is provided on the first surface, and includes a metal layer consisting of only metal whose standard oxidation-reduction potential is not lower than 0 (zero) V in an ionization tendency. The electrical conductive layer covers an inside of a hole which is formed in the semiconductor layer so as to reach the interlayer from the second surface, and is electrically connected to the electrode via the interlayer which is exposed to a bottom of the hole.
  • Hereinafter, an embodiment will be explained referring to drawings. The same numerals are given to the same portions in the drawings, and overlapping explanations are omitted.
  • FIG. 1A and FIG. 1B are schematic diagrams showing a semiconductor device 1 concerning the embodiment. FIG. 1A is a top view showing a part of the semiconductor device. FIG. 1B is a sectional view taken along line 1 B-1 B shown in FIG. 1A.
  • The semiconductor device 1 is a field effect transistor, for example, and is provided with a functional part 7 and a pad electrode 10. The functional part 7 contains source electrodes 3, drain electrodes 4, and gate electrodes 5. As shown in FIG. 1A, the pad electrode 10 is connected to a plurality of the source electrodes 3.
  • In addition, as shown in FIG. 1B, the semiconductor device 1 is provided with a semiconductor layer 20, an electrical conductive layer 30, and an interlayer 40. The semiconductor layer 20 has a first surface 20 a, and a second surface 20 b that is opposite to the first surface 20 a. The interlayer 40 is formed in contact with the first side 20 a of the semiconductor layer 20. The pad electrode 10 is formed on the interlayer 40. Another layer which has conductivity may be provided between the pad electrode 10 and the interlayer 40.
  • The semiconductor layer 20 has a via hole 17. The via hole 17 includes a hole 17 a which penetrates the semiconductor layer 20 in the direction facing to the pad electrode 10 from the second surface 20 b and reaches the interlayer 40 from the second surface 20 b, and a via contact 30 a which covers an inside of the hole 17 a. The electrical conductive layer 30 contains the via contact 30 a and a back electrode 30 b provided on the second surface 20 a.
  • The via contact 30 a is in contact with the interlayer 40 which is exposed to a bottom 17 b of the hole 17 a. The interlayer 40 is an electrical conductive layer containing platinum (Pt), for example, and the electrical conductive layer 30 is electrically connected to the pad electrode 10 via the interlayer 40.
  • For example, the interlayer 40 contains a metal layer 13 and a reaction layer 15 which is formed by reaction of the metal layer 13 and the semiconductor layer 20. The electrical conductive layer 30 is in contact with the reaction layer 15. Also, the reaction layer 15 may be removed at the bottom 17 b of the hole 17 and the electrical conductive layer 30 may be contact with the metal layer 13 directly. Here, the metal layer 13 consists of only metal whose standard oxidation-reduction potential is not lower than 0 (zero) V in an ionization tendency, for example.
  • And the interlayer 40 is apart from the functional part 7 which is electrically connected to the pad electrode 10. That is, the interlayer 40 should just be under the pad electrode 10, and does not need to be provide under the functional part 7 and a part which connects the functional part 7 and the pad electrode 10.
  • Next, a manufacturing method of the semiconductor device 1 is explained with reference to FIG. 2 and FIGS. 3A-3F. FIG. 2 is a flow chart showing the manufacture process of the semiconductor device 1 concerning the embodiment. FIGS. 3A-3F are schematic sectional views showing the manufacture process of the semiconductor device concerning the embodiment. In addition, FIGS. 3A-3F correspond to steps 01-06 shown in FIG. 2 and show partial cross section of a wafer in each step.
  • To begin with, the metal layer 13 is formed on the first surface 20 a of the semiconductor layer 20 as shown in FIG. 3A (S01).
  • The semiconductor layer 20 is a high resistance layer of semi-insulation, and gallium arsenide (GaAs), indium phosphate (InP), or gallium nitride (GaN) can be used as the semiconductor layer 20, for example. Also, a GaAs board or InP board of semi-insulation may be sufficient as the semiconductor layer 20.
  • The metal layer 13 is selectively formed on a part of the semiconductor layer 20 on which the pad electrode 10 is formed. The metal layer 13 is desirable to have tolerance for the dry etching which is used for formation of the hole 17 a for the via hole 17. That is, a metal which is chemically stable and does not react to the active element contained in an etching gas is used as the metal layer 13. The etching gas contains chlorine when the semiconductor layer 20 is a GaAs layer or an InP layer, for example. Therefore, it is preferable to use platinum (Pt) which is stable chemically to chlorine as the metal layer 13.
  • On the other hand, the specific resistance of platinum is larger than the specific resistance of gold (Au) which is used for the pad electrode 10. For this reason, as for the thickness of the metal layer 13, it is desirable that it is not larger than 60 nm, for example.
  • Next, as shown in FIG. 3B, by adding heat treatment to the semiconductor layer 20 and the metal layer 13, the semiconductor layer 20 and the metal layer 13 react to thereby form the reaction layer 15 (S02).
  • When the metal layer 13 is a platinum layer, the reaction layer 15 containing platinum is formed between the semiconductor layer 20 and the metal layer 13.
  • Next, as shown in FIG. 3C, the pad electrode 10 is formed on the metal layer 13 (S03). The pad electrode 10 is a source pad, for example, and is formed so as to be connected to the source electrodes 3. An Au layer can be used as the pad electrode 10, for example.
  • Next, as shown in FIG. 3D, the semiconductor layer 20 is thinned (S04). When a GaAs board or an InP board is used as the semiconductor layer 20, for example, the semiconductor layer 20 is thinned to thickness of several 10 μm by grinding or polishing. In addition, an epitaxially grown layer separated from a growth board may be used as the semiconductor layer 20.
  • Next, as shown in FIG. 3E, the hole 17 a is formed in the direction which faces to the pad electrode 10 from the second surface 20 b of the semiconductor layer 20 which has been thinned (S05). The semiconductor layer 20 is selectively etched using the RIE (Reactive Ion Etching) method, for example, to thereby form the hole 17 a. An etching gas contains chlorine, for example.
  • The hole 17 a reaches either of the reaction layer 15 and the metal layers 13. For example, when a platinum layer is used for the metal layer 13, the reaction layer 15 contains platinum. The etching rate of the reaction layer 15 becomes lower than the etching rate of the semiconductor layer 20. Thereby, it becomes easy to stop etching at the reaction layer 15. That is, the reaction layer 15 can be exposed to the second surface side of the semiconductor layer 20. Also, the reaction layer 15 may be removed to thereby expose the metal layer 13.
  • Next, as shown in FIG. 3F, the electrical conductive layer 30 which covers the inside of the hole 17 a is formed and thereby the via hole 17 is formed (S06). The electrical conductive layer 30 is a gold plate layer, for example. A seed layer 21 is formed on the inside of the hole 17 a and the second surface 20 b, for example. Then, electrolytic plating of gold is performed while flowing current through the seed layer 21 and a gold plate layer is formed on the seed layer 21. A two-layer film in which titanium (Ti) and gold (Au) are laminated in order from the semiconductor layer 20 side can be used as the seed layer 21, for example. Ti film raises the adhesion power between the semiconductor layer 20 and the electrical conductive layer 30, and raises the adhesion power between the reaction layer 15 and the electrical conductive layer 30.
  • The above-mentioned manufacture process can form a via-structure which electrically connects the pad electrode 10 provided on first surface 20 a of the semiconductor layer 20 and the electrical conductive layer 30 provided in the second surface 20 b side.
  • FIGS. 4A and 4B are schematic sectional views showing a semiconductor device 2 concerning a comparative example. FIG. 4A shows a cross section (refer to FIG. 1B) taken along an IB-IB line. FIG. 4B is an enlarged drawing of a part A shown in FIG. 4A, and shows a connection structure between the pad electrode 10 and the electrical conductive layer 30.
  • The semiconductor device 2 includes a metal layer 23 and a reaction layer 25. The metal layer 23 contains a metal whose standard oxidation-reduction potential is lower than 0 (zero) V in an ionization tendency, for example. Accordingly, the reaction layer 25 contains a metal whose standard oxidation-reduction potential is lower than 0 (zero) V in an ionization tendency, for example.
  • The metal layer 23 contains gold germanium (AuGe), nickel (nickel) and gold (Au) which were laminated in order from the semiconductor layer 20 side, for example, because the semiconductor device 2 uses a metal layer which is simultaneously formed with the ohmic electrode as a surface side electrode. That is, the metal layer 23 contains nickel which reacts chemically with chlorine. And the reaction layer 25 which is formed by heat-treating the metal layer 23 and the semiconductor layer 20 also contains nickel.
  • Also in this comparative example, the semiconductor layer 20 is etched in the direction which faces to the pad electrode 10 from the second surface 20 b of the semiconductor layer 20 by dry etching and thereby the hole 17 a is formed. And the reaction layer 25 is exposed to the second surface 20 b side. At this time, nickel contained in the reaction layer 25 reacts with chlorine contained in an etching gas, and thereby chlorination nickel (NiCl2) is produced on an exposed surface of the reaction layer 25.
  • Chlorination nickel corrodes the reaction layer 25 in the formation process of the electrical conductive layer 30, and forms voids 31 in the surface of the reaction layer 25 as shown in FIG. 4B. And plating liquid enters into the voids 31 in the process of gold-plating which forms an electrical conductive layer 30, and the plating liquid may remain in the void 31 as it is.
  • When the semiconductor device 2 is heated in a case that the semiconductor device 2 is mounted on a package or a mounting board, the plating liquid which remains inside the void 31 evaporate to thereby raise the internal pressure of the void 31. For this reason, the phenomenon in which the reaction layer 25 is dissociated from the electrical conductive layer 30, and in which the reaction layer 25, the metal layer 23 and pad electrode 10 are inflated occurs. As a result, an electrical connection between the electrical conductive layer 30 and the pad electrode 10 may be lost, and operation of the semiconductor device 2 may become unstable.
  • On the other hand, according to the embodiment, the metal layer 13 is chemically stable to chlorine contained in the etching gas. That is, the metal layer 13 does not contain any element that reacts with the active element contained in the etching gas. Even if the metal layer 13 contains such an element that reacts with the active element contained in the etching gas, the concentration of such element is not higher than a level detectable using the measuring means, such as an SIMS (Secondary Ion Mass Spectrometry) and a Auger spectroscopy.
  • Also the reaction layer 15 that is formed by reaction of the metal layer 13 and the semiconductor layer 20 does not contain any unstable element to chlorine contained in the etching gas. For this reason, the void 31 is not formed between the reaction layer 15 and the electrical conductive layer 30, and deformation of the reaction layer 15, the metal layer 13 and the pad electrode 10 can be suppressed. And the electrical connection between the electrical conductive layer 30 and the pad electrode 10 is held stable, and the reliability of the semiconductor device can be improved.
  • A metal which is chemically unstable to chlorine contained in the etching gas is metal whose standard oxidation-reduction potential is lower than 0 (zero) V in an ionization tendency. Aluminum (Al), titanium (Ti), tantalum (Ta), chromium (Cr), nickel (nickel), tin (Sn), etc. out of the metals used in a semiconductor process in many cases, correspond to such a metal.
  • A metal which is chemically stable to chlorine contained in the etching gas is a metal whose standard oxidation-reduction potential is not lower than 0 (zero) V in an ionization tendency. Copper (Cu), palladium (Pd), platinum (Pt), gold (Au), etc. out of the metals used in a semiconductor process in many cases, correspond to such a metal.
  • While the embodiment has been described, the embodiment has been presented by way of example only, and is not intended to limit the scope of the inventions. Indeed, the novel embodiment described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiment described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

Claims (8)

What is claimed is:
1. A semiconductor device, comprising:
a semiconductor layer which has a first surface and a second surface which is opposite to the first surface;
an interlayer which is provided on the first surface, and which includes a metal layer consisting of only metal whose standard oxidation-reduction potential is not lower than 0 (zero) V in an ionization tendency;
an electrode provided on the interlayer; and
an electrical conductive layer which covers an inside of a hole which is formed in the semiconductor layer so as to reach the interlayer from the second surface, and which is electrically connected to the electrode via the interlayer which is exposed to a bottom of the hole.
2. The semiconductor device according to claim 1, wherein the metal layer of the interlayer consists of platinum (Pt).
3. The semiconductor device according to claim 1, wherein the metal layer of the interlayer consists of one metal or plural metals selected from a group consisting of copper (Cu), palladium (Pd), platinum (Pt), and gold (Au).
4. The semiconductor device according to claim 1, wherein the interlayer contains the metal layer and a reaction layer which is formed by reaction of the metal layer and the semiconductor layer, and the electrical conductive layer is in contact with the reaction layer.
5. The semiconductor device according to claim 4, wherein the interlayer contains a platinum layer and the reaction layer which is formed by reaction of the platinum layer and the semiconductor layer, and the electrical conductive layer is in contact with the reaction layer.
6. The semiconductor device according to claim 1, further comprising a functional part which is electrically connected to the electrode, and wherein the interlayer is separated from the functional part.
7. A method for manufacturing a semiconductor device, comprising:
forming a metal layer consisting of only metal whose standard oxidation-reduction potential is not lower than 0 (zero) V in an ionization tendency on a first surface of a semiconductor layer;
forming a reaction layer by heat-treating the metal layer and the semiconductor layer;
forming an electrode on the metal layer;
exposing at least one of the reaction layer and the metal layer to the second surface of the semiconductor layer which is opposite to the first surface by forming a hole which penetrates the semiconductor layer in the direction facing to the electrode from the second surface; and
forming an electrical conductive layer which covers the inside of the hole and is electrically connected to the electrode.
8. The method for making semiconductor device according to claim 7, wherein the metal layer is a platinum layer.
US14/021,002 2013-02-21 2013-09-09 Semiconductor device and method for manufacturing the same Abandoned US20140231997A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/822,224 US9269619B2 (en) 2013-02-21 2015-08-10 Semiconductor device and method for manufacturing the same

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2013032528 2013-02-21
JP2013-032528 2013-02-21
JP2013-109204 2013-05-23
JP2013109204A JP6034747B2 (en) 2013-02-21 2013-05-23 Semiconductor device and manufacturing method thereof

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US14/822,224 Division US9269619B2 (en) 2013-02-21 2015-08-10 Semiconductor device and method for manufacturing the same

Publications (1)

Publication Number Publication Date
US20140231997A1 true US20140231997A1 (en) 2014-08-21

Family

ID=49118404

Family Applications (2)

Application Number Title Priority Date Filing Date
US14/021,002 Abandoned US20140231997A1 (en) 2013-02-21 2013-09-09 Semiconductor device and method for manufacturing the same
US14/822,224 Active US9269619B2 (en) 2013-02-21 2015-08-10 Semiconductor device and method for manufacturing the same

Family Applications After (1)

Application Number Title Priority Date Filing Date
US14/822,224 Active US9269619B2 (en) 2013-02-21 2015-08-10 Semiconductor device and method for manufacturing the same

Country Status (6)

Country Link
US (2) US20140231997A1 (en)
EP (1) EP2770529B1 (en)
JP (1) JP6034747B2 (en)
KR (2) KR20140104887A (en)
CN (1) CN104009017A (en)
TW (1) TWI570868B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12382697B2 (en) 2020-12-22 2025-08-05 Mitsubishi Electric Corporation Semiconductor device and method for manufacturing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120104563A1 (en) * 2009-11-12 2012-05-03 Daishiro Saito Semiconductor device and method for manufacturing semiconductor device
US20120138128A1 (en) * 2010-12-01 2012-06-07 Industrial Technology Research Institute Solar Cell

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2803408B2 (en) * 1991-10-03 1998-09-24 三菱電機株式会社 Semiconductor device
EP0881694A1 (en) * 1997-05-30 1998-12-02 Interuniversitair Micro-Elektronica Centrum Vzw Solar cell and process of manufacturing the same
US7892974B2 (en) * 2000-04-11 2011-02-22 Cree, Inc. Method of forming vias in silicon carbide and resulting devices and circuits
JP2004056031A (en) * 2002-07-24 2004-02-19 Mitsubishi Electric Corp Semiconductor device
JP2005327956A (en) * 2004-05-17 2005-11-24 New Japan Radio Co Ltd Semiconductor device and manufacturing method thereof
JP5117698B2 (en) * 2006-09-27 2013-01-16 ルネサスエレクトロニクス株式会社 Semiconductor device
JP2008098581A (en) * 2006-10-16 2008-04-24 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method thereof
JP5298559B2 (en) * 2007-06-29 2013-09-25 富士通株式会社 Semiconductor device and manufacturing method thereof
KR101528382B1 (en) * 2007-10-17 2015-06-12 헤레우스 프레셔스 메탈즈 노스 아메리카 콘쇼호켄 엘엘씨 Dielectric coating for single sided back contact solar cells
US20100012175A1 (en) * 2008-07-16 2010-01-21 Emcore Solar Power, Inc. Ohmic n-contact formed at low temperature in inverted metamorphic multijunction solar cells
DE102008033632B4 (en) * 2008-07-17 2012-06-14 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Solar cell and solar cell module
US8343806B2 (en) * 2009-03-05 2013-01-01 Raytheon Company Hermetic packaging of integrated circuit components
JP5318051B2 (en) 2010-09-08 2013-10-16 株式会社東芝 Semiconductor device
JP5700502B2 (en) * 2010-07-28 2015-04-15 住友電工デバイス・イノベーション株式会社 Semiconductor device and manufacturing method
JP5958732B2 (en) * 2011-03-11 2016-08-02 ソニー株式会社 Semiconductor device, manufacturing method, and electronic apparatus
CN103477450A (en) * 2011-04-21 2013-12-25 应用材料公司 Method of forming P-N junction in solar cell substrate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120104563A1 (en) * 2009-11-12 2012-05-03 Daishiro Saito Semiconductor device and method for manufacturing semiconductor device
US20120138128A1 (en) * 2010-12-01 2012-06-07 Industrial Technology Research Institute Solar Cell

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12382697B2 (en) 2020-12-22 2025-08-05 Mitsubishi Electric Corporation Semiconductor device and method for manufacturing the same

Also Published As

Publication number Publication date
JP6034747B2 (en) 2016-11-30
KR20150099493A (en) 2015-08-31
TWI570868B (en) 2017-02-11
TW201434126A (en) 2014-09-01
EP2770529A2 (en) 2014-08-27
US20150348841A1 (en) 2015-12-03
JP2014187342A (en) 2014-10-02
EP2770529B1 (en) 2020-02-12
EP2770529A3 (en) 2016-07-27
CN104009017A (en) 2014-08-27
KR20140104887A (en) 2014-08-29
US9269619B2 (en) 2016-02-23

Similar Documents

Publication Publication Date Title
US9245845B2 (en) Semiconductor device
CN103582939B (en) Nitride semiconductor device
US9355958B2 (en) Semiconductor device having a corrosion-resistant metallization and method for manufacturing thereof
TW201621989A (en) Semiconductor device and method of manufacturing same
US9991349B2 (en) Semiconductor device and method for manufacturing semiconductor device
JP6425508B2 (en) Thin film transistor
US9627335B2 (en) Method for processing a semiconductor workpiece and semiconductor workpiece
JP6107508B2 (en) Compound semiconductor device and manufacturing method thereof
CN105448751B (en) Method of the deposited Au to form golden metallization structure in copper seed layer
JP2007184553A (en) Semiconductor device and manufacturing method thereof
JP2015106638A5 (en)
US9269619B2 (en) Semiconductor device and method for manufacturing the same
US9105701B2 (en) Semiconductor devices having compact footprints
EP2605294B1 (en) Semiconductor light emitting device
US8237170B2 (en) Schottky diamond semiconductor device and manufacturing method for a Schottky electrode for diamond semiconductor device
KR102761384B1 (en) Semiconductor device and its manufacturing method
US9099425B2 (en) Semiconductor device and method for manufacturing the same
US20120018880A1 (en) Semiconductor structure and manufacturing method thereof
US9953894B2 (en) Semiconductor device and manufacturing method thereof
US20200176640A1 (en) Method of producing a layer stack and layer stack
CN112242306A (en) Method for manufacturing semiconductor device and method for laminating metal
JP2013080978A (en) Semiconductor light-emitting device
HK1184911A (en) Semiconductor light emitting device

Legal Events

Date Code Title Description
AS Assignment

Owner name: KABUSHIKI KAISHA TOSHIBA, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SASAKI, FUMIO;KAWASAKI, HISAO;REEL/FRAME:031164/0468

Effective date: 20130904

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION