US20130034917A1

US20130034917A1 - Method for fabricating magnetic tunnel junction device

Info

Publication number: US20130034917A1
Application number: US13/315,011
Authority: US
Inventors: Min Suk Lee
Original assignee: Individual
Current assignee: SK Hynix Inc; Samsung Semiconductor Inc
Priority date: 2011-08-04
Filing date: 2011-12-08
Publication date: 2013-02-07
Anticipated expiration: 2031-12-08
Also published as: KR101870873B1; US8642358B2; KR20130015564A

Abstract

A method for fabricating a semiconductor device includes forming a plurality of layers which are stacked as a bottom layer, an MTJ layer, and a top layer, patterning the top layer and the MTJ layer using an etch mask pattern to form a top layer pattern and an MTJ pattern, forming a carbon spacer on the sidewalls of the MTJ pattern and the top layer pattern to protect the MTJ pattern and the top layer pattern, and patterning the bottom layer using the carbon spacer and the etch mask pattern as an etch mask to form a bottom layer pattern.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No. 10-2011-0077616, filed on Aug. 4, 2011, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Field
Exemplary embodiments of the present invention relate to a device used in an integrated circuit, and more particularly, to a magnetic tunnel junction device.
2. Description of the Related Art
A dynamic random access memory (DRAM) is an exemplary memory device which has been widely used. A DRAM has a feature of operating at a high speed and may be highly integrated. Here, a DRAM is a volatile memory loses data when power is interrupted, and a refresh operation is to be performed to rewrite data periodically.
Also, a flash memory characterized by non-volatility and high degree of integration may have a relatively low operating speed. A magnetoresistive memory device which stores data using a magneto-resistance change may be fabricated as a highly integrated circuit while having non-volatility and high speed operation characteristics.
The magnetoresistive memory device refers to a nonvolatile memory device which stores data using a magneto-resistance changes due to changes in magnetization directions of ferromagnetic materials. The magnetoresistive memory device may include a magneto-resistance element of two magnetic layers. The magneto-resistance element generally has a small resistance when spin directions (magnetic momentum directions) of two magnetic layers are equal to each other and has large resistance when spin directions of the two magnetic layers are opposite to each other. Data may be written to a magnetoresistive memory device by using the fact that the resistance of the magneto-resistance element changes depending on the magnetization states of the magnetic layers.
A magnetoresistive memory device of an MTJ (Magnetic Tunnel Junction) device has a structure of ferromagnetic layer/insulation layer/ferromagnetic layer. When electrons having passed through a first ferromagnetic layer pass through an insulation layer served as a tunneling barrier, a tunneling probability changes depending on a magnetization direction of a second ferromagnetic layer. The tunneling probability becomes a maximum value when the magnetization directions of the two ferromagnetic layers are parallel to each other and the tunneling probability becomes a minimum when the magnetization directions of the two ferromagnetic layers are anti-parallel to each other. The amount of the tunneling current flowing between two ferromagnetic layers depends on the tunneling probability. For example, it may be considered that data ‘1’ (or ‘0’) is written when the tunneling current is large and data ‘0’ (or ‘1’) is written when the tunneling current is small. One of the two ferromagnetic layers serves as a fixed magnetic layer whose magnetization direction is fixed, and the other serves as a free magnetic layer whose magnetization direction is changed in response to an external magnetic field or electric current.
Here, it is difficult to pattern materials constituting an MTJ element, in a general process for manufacturing a semiconductor. A hard mask pattern is generally used for patterning the materials constituting the MTJ element. Since electrode layers disposed over and under an MTJ element are to be patterned by a different patterning process from that of the MTJ element, it becomes more difficult to fabricate a semiconductor device including an MTJ element. A spacer layer may be further formed to protect the MTJ element before patterning the electrode layers. Therefore, a manufacturing process of the semiconductor device may be more complicated.

SUMMARY

An embodiment of the present invention is directed to a method for fabricating a semiconductor device including a magnetic tunnel junction device, which may decrease the number of processes to be performed.
In accordance with an embodiment of the present invention, a method for fabricating a semiconductor device includes forming a plurality of layers which are stacked as a bottom layer, a magnetic tunnel junction (MTJ) layer, and a top layer, patterning the top layer and the MTJ layer using an etch mask pattern to form a top layer pattern and an MTJ pattern, forming a carbon spacer on the sidewalls of the MTJ pattern and the top layer pattern to protect the MTJ pattern and the top layer pattern, and patterning the bottom layer using the carbon spacer and the etch mask pattern as an etch mask to form a bottom layer pattern.
In accordance with another embodiment of the present invention, a method for fabricating a semiconductor device includes forming a plurality of layers which are stacked as a bottom layer, a magnetic tunnel junction (MTJ) layer, and a top layer, patterning the top layer, the MTJ layer, and the bottom layer using an etch mask pattern to form a top layer pattern, an MTJ pattern, and a bottom layer pattern, forming a carbon spacer on the sidewalls of the bottom layer pattern, the MTJ pattern, and the top layer pattern, and performing a cleaning process for removing residues resulting from the patterning of the top, MTJ, and bottom layers wherein the carbon spacer protects the bottom layer pattern, the MTJ pattern, and the top layer pattern during the cleaning process.
In accordance with further embodiment of the present invention, a method for fabricating a semiconductor device includes forming a fixed magnetization layer, a tunnel insulation layer, and a free magnetization layer for a magnetic tunnel junction (MTJ) element, forming an etch mask pattern for the MTJ element over the fixed magnetization layer, the tunnel insulation layer, and the free magnetization layer, patterning the free magnetization layer and the tunnel insulation layer using the etch mask pattern as an etch mask to form a free magnetization layer pattern and a tunnel insulation layer pattern, forming a carbon spacer on the sidewalls of the free magnetization layer pattern and the tunnel insulation layer pattern, and patterning the fixed magnetization layer using the carbon spacer as an etch mask to form a fixed magnetization layer pattern.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1F are cross-sectional views illustrating a method for fabricating a magnetic tunnel junction device to illustrate an exemplary embodiment of the present invention.

FIGS. 2A to 2H are cross-sectional views illustrating a method for fabricating a magnetic tunnel junction device in accordance with an exemplary embodiment of the present invention.

DETAILED DESCRIPTION

Exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.
In an embodiment of the present invention, a carbon spacer is formed by an in-situ process using a carbon-containing etching gas during an etching process of an MTJ element. The carbon spacer might be a carbon polymer spacer. A nitride spacer deposition process in a low temperature and an etching process using the nitride spacer deposition as a mask according to the conventional art might be replaced with an etching process using the carbon polymer space as an etch barrier.
In using conventional methods, after a patterning process for an MTJ element is performed, an insulation layer is formed over the MTJ element for protection. Then, a bottom layer below the MTJ element is patterned with the insulation layer protecting the MTJ element. A part of the insulation layer is removed during the patterning process for the bottom layer. The patterning process is typically implemented in an ex-situ. The ex-situ means that the patterning processes for the bottom layer and for the MTJ element are implemented in different process chambers.
In an embodiment of the present invention, the carbon spacer is formed by changing process condition in the same chamber where the MTJ element is patterned. The carbon spacer is used as a spacer for protecting an MTJ element. When patterning a bottom layer for a bottom electrode which is placed under the MTJ element, the carbon spacer protects the MTJ element. A protecting layer for an MTJ element may be formed by an in-situ process. That is, the MTJ element and the carbon spacer are formed in the same process chamber.
FIGS. 1A to 1F are cross-sectional views illustrating a method for fabricating a semiconductor device to illustrate an exemplary embodiment of the present invention.
Referring to FIG. 1A, in the fabrication of a magnetic tunnel junction (MTJ) device, a conductive layer 11 for a bottom electrode is formed on a substrate 10, and a layer 12 for an MTJ element is formed on the conductive layer 11. The layer 12 for an MTJ element may include a plurality of layers for the MTJ element but is illustrated as one layer as an example. A conductive layer 13 for a top electrode is formed over the layer 12. Layers 14, 15, and 16 for a hard mask are formed on the conductive layer 13. The respective layers 14, 15, and 16 for a hard mask may include a tantalum layer, a USG layer, and a carbon layer. For example, the tantalum layer may be formed to have a height of 500 Å. Subsequently, a photoresist pattern 17 for a patterning process is formed on the layers 14, 15, and 16.
Referring to FIG. 1B, a pattern is formed by etching the layer 16 for a hard mask using the photoresist pattern 17 as an etch mask. By patterning the layers 14 and 15 for a hard mask using the pattern as an etch mask, hard mask patterns 14 a and 15 a are formed. The pattern of the layer 16 for a hard mask is then removed.
Referring to FIG. 1C, a top electrode 13 a and an MTJ element 12 a are formed by patterning the conductive layer 13 for a top electrode and the layer 12 for an MTJ element using the hard mask patterns 14 a and 15 a.
Referring to FIG. 1D, a spacer layer 18 is formed to protect the MTJ element 12 a. The spacer layer 18 is formed as a nitride layer in an ex-situ process.
Referring to FIG. 1E, a pattern 19 for patterning a bottom electrode is formed.
Referring to FIG. 1F, a bottom electrode 11 a is formed by patterning the conductive layer 11 for a bottom electrode using the pattern 19 as an etch mask.
As described above, two step etch processes are performed in order to form the MTJ element and the bottom electrode. That is, the manufacturing procedure for the MTJ element and the bottom electrode is complicated.
In particular, an ex-situ process is to be implemented in order to form the spacer layer and the bottom electrode. Two process chambers are to be used for forming a protecting layer of The MTJ element, i.e., the spacer layer, and etching the conductive layer 11 for a bottom electrode. In this procedure, properties of the MTJ element are likely to deteriorate due to contamination from particles, etc.
It may be considered that a bottom electrode is formed with an MTJ element in a single etching process. In this case, when etching an MTJ element, a bottom layer for a bottom electrode (for example, a tantalum/titanium nitride layer) is also etched.
In order to etch the bottom layer which might be a metal layer, Cl or F-based etching gas is to be used. These gases may give a bad influence on characteristics of layers constituting the MTJ element. Therefore, it is difficult to perform an etching process for a bottom electrode without the spacer layer 18 for protecting the MTJ element. In order to address these concerns, one etching process for forming the bottom electrode and the MTJ element may be performed using an etching gas such as CH3OH. However, in this case, since a hard mask pattern used as an etch mask is also etched, the hard mask pattern is to be formed with an increased thickness, thereby reducing a process margin for a semiconductor device including an MTJ element.
Moreover, if the MTJ element is formed using the etching gas such as CH3OH, a cleaning process for removing residues remaining on the substrate is to be performed. Since the MTJ element is likely to be damaged during the cleaning process, it is not easy to perform the cleaning process.
In the present invention, a carbon spacer is formed around an MTJ element by adjusting etching conditions of the MTJ element, e.g., bias power, and using an etching gas of the MTJ element, e.g., CH₃OH, for an etching equipment of the MTJ element. Then, by using the spacer as an etch barrier, a process for patterning a conductive layer for a bottom electrode placed under the MTJ element is performed as an in-situ process in the same chamber used for patterning the MTJ element.
Namely, a forming process for the carbon spacer and a patterning process for a bottom electrode may be performed in the same etching chamber. The in-situ process includes the MTJ etching process.
Such processes as in situ processes may contribute to the simplification of processes. Since it is not necessary to exchange chambers for processing, problems caused by moving a wafer from a chamber to another chamber may be reduced. For instance, particles on the water may be minimized.
The carbon spacer protects the exposed surface of the MTJ element and serves as an etch barrier during a subsequent process. Due to the carbon spacer, the conductive layer for a bottom electrode may be etched using Cl or F-based etching gases, and residues on the surface of a substrate may be removed in a wet cleaning process while the MTJ element is safely protected.
FIGS. 2A to 2H are cross-sectional views illustrating a method for fabricating a semiconductor device in accordance with an exemplary embodiment of the present invention.
Referring to FIG. 2A, in the fabrication of an MTJ element, a conductive layer 21 for a bottom electrode is formed on a substrate 20, and a layer 22 for an MTJ element is formed on the conductive layer 21. A conductive layer 23 for a top electrode is formed over the layer 22. Each of the conductive layers 21 and 23 may use at least one selected from the group of a titanium (Ti) layer, a tantalum (Ta) layer, a platinum (Pt) layer, a copper (Cu) layer, a tungsten (W) layer, an aluminum (Al) layer, a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, and a tungsten silicide (WSi) layer, an alloy layer thereof, or a stacked layer thereof.
The layer 22 for an MTJ element may include a fixed magnetization layer, a tunnel insulation layer, and a free magnetization layer and may also be realized by stacking various types of layers. The fixed magnetization layer is a layer of which magnetization direction is fixed, and the free magnetization layer is a layer of which magnetization direction is changed depending upon a stored data. The fixed magnetization layer may include a pinning layer and/or a pinned layer.
The pinning layer functions to pin the magnetization direction of the pinned layer and may be formed by using a material of anti-ferromagnetism. For example, the material with anti-ferromagnetism may include IrMn, PtMn, MnO, MnS, MnTe, MnF2, FeF2, FeCl2, FeO, CoCl2, CoO, NiCl2, or NiO. The pinning layer may be formed as a single layer constituted by any one of these materials of anti-ferromagnetism or a stacked layer of these materials of anti-ferromagnetism.
The pinned layer, of which magnetization direction is pinned by the pinning layer, and the free magnetization layer may be formed using a material of ferromagnetism. For example, the material with ferromagnetism may include Fe, Co, Ni, Gd, Dy, NIFe, CoFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO, or Y3Fe5O12. The pinned layer or the free magnetization layer may be formed as a single layer constituted by any one of these materials of ferromagnetism or a stacked layer of these materials of ferromagnetism.
Also, the pinned layer and the free magnetization layer may be formed by stacking any one of the materials with ferromagnetism and a ruthenium (Ru) layer (for example, as CdFe/Ru/CoFe). Further, the pinned layer and the free magnetization layer may be formed as a synthetic anti-ferromagnetic (SAF) layer in which an anti-ferromagnetic coupling spacer layer and a ferromagnetic layer are sequentially stacked. The tunnel insulation layer serves as a tunneling barrier between the fixed magnetization layer and the free magnetization layer and may use any material of insulation characteristics. For example, the tunnel insulation layer may be formed as a magnesium oxide (MgO) layer.
Returning to FIG. 2A, layers 24, 25, and 26 for a hard mask are formed on the conductive layer 23. The respective layers 24, 25, and 26 for a hard mask may use a tantalum layer, a USG layer, and a carbon layer. For example, the tantalum layer may be formed to have a height of 500 Å. A photoresist pattern 27 for a patterning process is formed on the layers 24, 25, and 26.
Referring to FIG. 2B, by etching the layer 26 using the photoresist pattern 27 as an etch mask, a pattern is formed from the layer 26. After the layers 24 and 25 for a hard mask are patterned using the pattern as an etch mask, hard mask patterns 24 a and 25 a are formed. The pattern formed from the layer 26 and the photoresist pattern 27 are removed.
Referring to FIG. 2C, the conductive layer 23 for a top electrode and the layer 22 for an MTJ element are patterned using the hard mask patterns 24 a and 25 a, and a top electrode 23 a and an MTJ element 22 a are formed. CH₃OH or CO/NH₃may be used as an etching gas for the MTJ element 22 a, and in particular, a carbon-containing CxHyOz-based gas may be used when the layer 22 for an MTJ element is patterned. Further, a carbon-containing gas may include CH3OH, CO/NH3, or CH4.
Referring to FIG. 2D, a carbon coating layer 28 is formed to cover the MTJ element 22 a.
In the case where the MTJ element 22 a is etched using the above-described gas, a carbon-based deposition layer may be generated instead of etching the surface of the substrate if bombardment of ions generated from plasma gas does not occur on the surface of the substrate. The carbon coating layer has properties similar to an amorphous carbon deposition layer and contains some hydrogen and oxygen.
After the etching process for the MTJ element including MgO or CoFe is completed using the CxHyOz gas, if bias power applied to the surface of the substrate is adjusted in a predetermined range, the carbon coating layer is deposited on the surface of the substrate. The adjusting operation includes that the supply of the bias power is interrupted or is reduced. The carbon coating layer formed in this process is a kind of layer deposited by a plasma enhanced chemical vapor deposition (PECVD) process, and it may be uniformly deposited on the sidewall of a pattern structure perpendicular to the plane of the substrate.
Referring to FIG. 2E, a carbon spacer 28 a is formed using the carbon coating layer 28. By dry-etching the carbon coating layer deposited on the entire surface of the wafer using an etching gas such as O, F, and Cl, the carbon spacer 28 a is formed for protecting the MTJ element 22 a.
Referring to FIG. 2F, after the carbon spacer 28 a is formed on the sidewall of the MTJ element 22 a, the conductive layer 21 for a bottom electrode, for example, a Ta/TiN layer, is etched by using the carbon spacer 28 a as an etch barrier. In order to etch Ta and TiN layers, a halogen element such as F and Cl is to be used. Because an etching gas using the halogen element might exert an influence on the characteristics of the MTJ element 22 a, a spacer for protecting the sidewall of the MTJ element 22 a is to be formed. The carbon spacer 28 a according to present embodiment protects the sidewall of the MTJ element 22 a.
After a bottom metal electrode is formed using an F or Cl gas, etching residues are removed through a wet-etching process. Due to the carbon spacer 28 a, the MTJ element 22 a may be protected during the wet-etching process.
Due to the carbon spacer 28 a, Cl₂gas capable of removing a metal at a high etching speed may be used with CH₃OH or CO/NH₃as an etching gas. Therefore, etching selectivity to the hard mask pattern 24 a may be sufficiently increased, and the loss of the hard mask pattern 24 a may be reduced. Accordingly, the process margin of the hard mask pattern may be increased.
Referring to FIG. 2G, the carbon spacer 28 a is removed by an O2 asking process. The carbon spacer 28 a may remain if the carbon spacer 28 a does not exert a substantial influence on a subsequent process. Referring to FIG. 2H, a capping layer 29 is formed over the MTJ element 22 a.
In another embodiment, an MTJ element fabrication process may be performed in a variety of ways depending upon when the carbon spacer layer is formed. In order for the MTJ element, the spacer layer may be formed after the MTJ layer is entirely or partially etched. Otherwise, the carbon spacer may be formed after the conductive layer for a bottom electrode is etched. In other words, while the MTJ layer is constituted by the structure of a fixed layer, a tunnel insulation layer, and a free layer, the carbon spacer may be formed when the tunnel insulation layer is etched and the fixed layer is exposed.
Also, when etching the conductive layer for a bottom electrode after the etching process for the MTJ layer is completed, the carbon spacer layer may be formed in order to protect the exposed surface of the MTJ element from an etching gas and a subsequent cleaning process. In addition, the carbon spacer may be formed after the bottom electrode is formed, and the carbon spacer may be used as a capping material for the MTJ element during a subsequent cleaning process. When performing a wet etching for the surface of the substrate, the sidewall of the MTJ element may be protected.
As described above, in the method shown in FIGS. 1A to 1F, two etching patterns are to be formed for finishing the upper electrode, the MTJ element, and the bottom electrode. One pattern is the photoresist pattern 17 for patterning the layers 14, 15, and 16 and the other is the pattern 19 for patterning the bottom electrode. However, the method in accordance with the embodiment of the present invention may include one etch pattern for finishing the upper electrode, the MTJ element, and the bottom electrode due to the presence of the carbon spacer layer. The one etch pattern is the photoresist pattern 27 for the layers 24, 25, and 26. That is, if a carbon spacer is used according to the embodiment of the present invention, it is not necessary to perform two masking processes for forming a semiconductor device including an MTJ element.
If a nitride spacer instead of a carbon spacer is formed to protect an MTJ layer, two chambers are to be employed for finishing an MTJ element. On contrary, if the carbon spacer according to the embodiment of the present invention is used, an in-situ process may be performed and one chamber is to be used for finishing an MT) element. That is to say, the in-situ process means that an etching process for an MTJ element, a carbon spacer deposition process, and an etching process using a carbon spacer may be sequentially performed in the same etching chamber.
As the carbon spacer is formed after etching the MT) layer, a conductive layer for a bottom electrode may be etched using a halogen element such as Cl and F. Therefore, etching selectivity to a hard mask pattern may be increased, and thus, the process margin of a hard mask pattern used as an etch mask arranged on the MTJ layer may be increased.
While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims

1. A method for fabricating a semiconductor device, comprising:

forming a plurality of layers which are stacked as a bottom layer, a magnetic tunnel junction (MTJ) layer, and a top layer;

patterning the top layer and the MTJ layer using an etch mask pattern to form a top layer pattern and an MTJ pattern;

forming a carbon spacer on the sidewalls of the MTJ pattern and the top layer pattern to protect the MTJ pattern and the top layer pattern; and

patterning the bottom layer using the carbon spacer and the etch mask pattern as an etch mask to form a bottom layer pattern.

2. The method according to claim 1, wherein the forming of the top layer pattern and the MTJ pattern and the forming of the carbon spacer on the sidewalls are performed as an in-situ process.

3. The method according to claim 1, wherein the forming of the top layer pattern and the MTJ pattern, the forming of the carbon spacer on the sidewalls, and the forming of the bottom layer pattern are performed as an in-situ process.

4. The method according to claim 1, wherein the top layer and the bottom layer comprises at least one selected from the group including a titanium (Ti) layer, a tantalum (Ta) layer, a platinum (Pt) layer, a copper (Cu) layer, a tungsten (W) layer, an aluminum (Al) layer, a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, and a tungsten silicide (WSi) layer.

5. The method according to claim 1, wherein the patterning of the top layer and the MTJ layer is performed using a carbon-containing etching gas, and the forming of the carbon spacer on the sidewalls is performed by using the carbon-containing etching gas and controlling a bias power.

6. The method according to claim 1, wherein the forming of the carbon spacer on the sidewalls is performed under the same conditions as the patterning of the top layer and the MTJ layer by adjusting a bias power of the conditions.

7. A method for fabricating a semiconductor device, comprising:

patterning the top layer, the MTJ layer, and the bottom layer using an etch mask pattern to form a top layer pattern, an MTJ pattern, and a bottom layer pattern;

forming a carbon spacer on the sidewalls of the bottom layer pattern, the MD pattern, and the top layer pattern; and

performing a cleaning process for removing residues resulting from the patterning of the top, MTJ, and bottom layers wherein the carbon spacer protects the bottom layer pattern, the MTJ pattern, and the top layer pattern during the cleaning process.

8. The method according to claim 7, wherein the forming of the top layer pattern, the MTJ pattern, and the bottom layer pattern and the forming of the carbon spacer on the sidewalls are performed as an in-situ process.

9. The method according to claim 7, wherein the top layer and the bottom comprises at least one selected from the group of a titanium (Ti) layer, a tantalum (Ta) layer, a platinum (Pt) layer, a copper (Cu) layer, a tungsten (W) layer, an aluminum (Al) layer, a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, and a tungsten silicide (WSi) layer.

10. The method according to claim 7, wherein the patterning of the top layer, the MTJ layer, the bottom layer is performed using a carbon-containing etching gas, and the forming of the carbon spacer on the sidewalls is performed by using the carbon-containing etching gas and controlling a bias power.

11. A method for fabricating a semiconductor device, comprising:

forming a fixed magnetization layer, a tunnel insulation layer, and a free magnetization layer for a magnetic tunnel junction (MTJ) element;

forming an etch mask pattern for the MTJ element over the fixed magnetization layer, the tunnel insulation layer, and the free magnetization layer;

patterning the free magnetization layer and the tunnel insulation layer using the etch mask pattern as an etch mask to form a free magnetization layer pattern and a tunnel insulation layer pattern;

forming a carbon spacer on the sidewalls of the free magnetization layer pattern and the tunnel insulation layer pattern; and

patterning the fixed magnetization layer using the carbon spacer as an etch mask to form a fixed magnetization layer pattern.

12. The method according to claim 11, wherein the forming of the free magnetization layer pattern and the tunnel insulation layer pattern and the forming of the carbon spacer on the sidewalls are performed as an in-situ process.

13. The method according to claim 11, wherein the forming of the free magnetization layer pattern and the tunnel insulation layer pattern, the forming of the carbon spacer on the sidewalls, and the forming of the fixed magnetization layer are performed as an in-situ process.

14. The method according to claim 11, wherein the forming the free magnetization layer pattern and the tunnel insulation layer pattern is performed using a carbon-containing etching gas, and the forming of the carbon spacer on the sidewalls is performed by using the carbon-containing etching gas and controlling a bias power.

15. The method according to claim 11, wherein the forming of the carbon spacer on the sidewalls is performed under the same conditions as the forming of the free magnetization layer pattern and the tunnel insulation layer pattern by adjusting a bias power applied in the method.