[go: up one dir, main page]

US20120320632A1 - Power switch controllers and methods used therein for improving conversion effeciency of power converters - Google Patents

Power switch controllers and methods used therein for improving conversion effeciency of power converters Download PDF

Info

Publication number
US20120320632A1
US20120320632A1 US13/163,729 US201113163729A US2012320632A1 US 20120320632 A1 US20120320632 A1 US 20120320632A1 US 201113163729 A US201113163729 A US 201113163729A US 2012320632 A1 US2012320632 A1 US 2012320632A1
Authority
US
United States
Prior art keywords
power switch
time
signal
minimum
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/163,729
Inventor
Siarhei KALODKA
Chien-Liang Lin
Sergey Gaitukevich
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shamrock Micro Devices Corp
Original Assignee
Shamrock Micro Devices Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shamrock Micro Devices Corp filed Critical Shamrock Micro Devices Corp
Priority to US13/163,729 priority Critical patent/US20120320632A1/en
Assigned to SHAMROCK MICRO DEVICES CORP. reassignment SHAMROCK MICRO DEVICES CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GAITUKEVICH, SERGEY, KALODKA, SIARHEI, LIN, CHIEN-LIANG
Publication of US20120320632A1 publication Critical patent/US20120320632A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/22—Conversion of DC power input into DC power output with intermediate conversion into AC
    • H02M3/24—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters
    • H02M3/28—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
    • H02M3/325—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H02M1/0058—Transistor switching losses by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present disclosure relates generally to power supplies and the control methods used therein.
  • Power converters or adapters are devices that convert electric energy provided from batteries or power grid lines into power source with a specific voltage or current, such that electronic apparatuses are powered accordingly.
  • conversion efficiency which is the ratio of the power provided to a load powered by a power converter over the power delivered to the power converter over, is always a big concern. The less the power consumed by a power converter itself, the higher the conversion efficiency of the power converter.
  • QR quasi-resonant
  • FIG. 1 illustrates a flyback converter 8 , which is capable of operating in QR mode.
  • Circuit 10 illustrates flyback topology, including power switch 15 , primary winding PRM and secondary winding SEC of a transformer, a diode, and a current sense resistor.
  • power switch 15 When power switch 15 is ON, performing a short circuit, primary winding PRM energizes.
  • power switch 15 When power switch 15 is OFF, performing an open circuit, secondary winding SEC de-energizes to power node OUT through a diode.
  • Power switch controller 18 controls ON time T ON or OFF time T OFF of power switch 15 , based on feedback signal V FB provided at node FB by feedback circuit 20 , which monitors node OUT.
  • Operating voltage source generator 12 provides voltage source V cc at node VCC to power switch controller 18 .
  • Resistor 14 connects one terminal of auxiliary winding AUX to node ZCD of power switch controller 18 , to provide the energy status of the transformer.
  • FIGS. 2A and 2B show waveforms of voltage signal V ZCD at node ZCD under different load conditions.
  • FIG. 2A corresponds to a relatively heavier load
  • FIG. 2B to a relatively lighter load.
  • voltage signal V ZCD starts to oscillate after the transformer de-energizes completely and results in voltage valleys VLY 1 , VLY 2 , VLY 3 , and so forth.
  • a power supply in QR mode can operate to start energizing at the moment when any one of the voltage valleys occurs.
  • switch frequency f CYC is the inverse of cycle time T CYC , which is the summation of ON time T ON and OFF time T OFF , ON time T ON referring to the time period when a power switch is ON, and OFF time T OFF to the time period when it is OFF.
  • Curve 22 1 shows the V FB -to-f CYC relationship if power switch 15 is switched at the moment when voltage valley VLY 1 occurs.
  • Curve 22 2 shows the V FB -to-f CYC relationship if power switch 15 is switched at the moment when voltage valley VLY 2 occurs. And so forth. As shown in FIG.
  • switch frequency f CYC increases adversely as feedback V FB decreases.
  • the higher switch frequency f CYC the higher power to charge and discharge a control node of a power switch, resulting in less conversion efficiency.
  • Embodiments of the present invention disclose a power switch controller suitable to control a power switch connected to an inductive device.
  • the power switch controller includes a window provider, a sensor and a logic controller.
  • the window provider provides minimum and maximum time signals to indicate the elapses of a minimum time and a maximum time, respectively.
  • the sensor detects a terminal of the inductive device, to generate a trigger signal.
  • the logic controller prevents the power switch from being turned on before the elapse of the minimum time, forces the power switch to be turned on after the elapse of the maximum time, and turns on the power switch if the trigger signal is asserted.
  • Embodiments of the present invention disclose a method for controlling a power switch connected to an inductive device.
  • a terminal of the inductive device is detected to generate a trigger signal.
  • the power switch is turned on if the trigger signal is asserted. Before the elapse of a minimum time, the power switch is prevented from being turned on. After the elapse of a maximum time, the power switch is enforced to be turned on.
  • FIG. 1 illustrates a flyback converter
  • FIGS. 2A and 2B show waveforms of voltage signal V ZCD at node ZCD under different load conditions
  • FIG. 3 illustrates the relationships between switch frequency f CYC and feedback signal V FB at node FB;
  • FIG. 4 exemplifies a power switch controller adaptable to the flayback converter of FIG. 1 ;
  • FIG. 5 exemplifies a window provider
  • FIG. 6 illustrates the waveforms of signals in FIGS. 4 and 5 ;
  • FIG. 7 illustrates two diagrams, the upper one showing the changes of minimum time T MIN and maximum time T MAX vs. feedback signal V FB , and the lower one showing the changes of maximum frequency f MAX and minimum frequency f MIN vs. feedback signal V FB ;
  • FIG. 8 includes curve 50 illustrating the relationship between switch frequency f CYC and feedback signal V FB for power switch controller 30 in FIG. 4 ;
  • FIGS. 9A and 9B show two window providers
  • FIG. 10 illustrates the relationship between switch frequency f CYC and feedback signal V FB for power switch controller 30 in FIG. 4 if window provider 40 is embodied by window provider 60 a or 60 b.
  • flyback converters are exemplified by flyback converters, but are not intended to limit the scope of the invention.
  • a person skilled in the art could apply the concept of the invention to converters with different topologies, such as bulk converters, buck-boost converters, boost converters, and so forth.
  • FIG. 4 exemplifies power switch controller 30 adaptable to flyback converter 8 of FIG. 1 .
  • Comparator 32 , delay circuit 33 and pulse generator 36 as a whole acting as a sensor, detects one terminal of auxiliary winding AUX to generate trigger signal S PLS with pulses, each expectedly corresponding to an occurrence of a voltage valley at node ZCD.
  • Window provider 40 provides minimum and maximum time signals, S MIN and S MAX , to indicate the elapses of a minimum time T MIN and a maximum time T MAX .
  • Logic controller 38 includes several logic gates, controls the S terminal of SR register 34 , and determines when power switch 15 is switched to be ON.
  • trigger signal S PLS is possible to pass through logic controller 38 and, if asserted, set SR register 34 . In other words, logic controller 38 prevents power switch 15 from being turned on before the elapse of minimum time T MIN . If trigger signal S PLS is not asserted and maximum time T MAX elapses, maximum time signal S MAX sets SR register 34 anyway, power switch 15 is forced to be turned ON, and the flyback converter enters into a following switch cycle.
  • signal V CS at current sense node CS exceeds the voltage at the inverse input of comparator 42 , SR register 34 is reset and power switch 15 is switched to be OFF. Accordingly, feedback signal V FB at node FB substantially decides the peak voltage of signal V CS or the power supplied to node OUT in a switch cycle.
  • FIG. 5 exemplifies window provider 40 , which receives set signal S SET , and outputs minimum and maximum time signals, S MIN and S MAX .
  • ramp signal V RMP When set signal is asserted, ramp signal V RMP is grounded. When set signal is de-asserted, ramp signal V RMP starts to increase, with a slope determined by the output current of voltage-controllable current source 70 , which is controlled by feedback signal V FB at node FB.
  • Feedback signal V FB substantially represents the power required by a load at node OUT.
  • minimum and maximum time signals S MIN and S MAX are toggled or asserted, respectively, indicating the elapses of minimum time T MIN and maximum time T MAX , respectively.
  • Reference voltage V REFL should be less than reference voltage V REFH , such that minimum time signal S MIN is asserted earlier. If the output current of voltage-controllable current source 70 decreases, the slope of ramp signal V RMP is less and it takes more time for ramp signal V RMP to reach reference voltages V REFL and V REFH , such that both minimum time T MIN and maximum time T MAX increase. It can be derived by those skilled in the art that minimum time T MIN and maximum time T MAX provided in FIG. 5 are in proportion.
  • FIG. 6 illustrates the waveforms of signals in FIGS. 4 and 5 .
  • Waveforms in FIG. 6 are, from top to bottom, voltage signal V ZCD at node ZCD, signal S DET from comparator 32 , signal S DLY from delay circuit 33 , trigger signal S PLS from pulse generator 36 , set signal S SET at S terminal of SR register 34 , gate signal S GATE at node GATE, ramp signal V RMP in FIG. 5 , and minimum time signal S MIN from comparator 42 .
  • the pulse of set signal S SET at time t 1 turns on power switch 15 and grounds ramp signal V RMP .
  • ON time T ON is determined by feedback signal V FB , such that gate signal S GATE changes at time t 2 , causing the rising of voltage signal V ZCD , the logic change of signal S DET , and the logic change of signal S DLY , which is delayed by delay time T delay in comparison with signal S DET .
  • V FB feedback signal
  • minimum time signal S MIN remains 0 in logic, such that pulses in trigger signal S PLS , if any, are blocked from reaching S terminal of SR register 34 and set signal S SET remains 0 in logic.
  • ramp signal V RMP has exceeded reference voltage V REFL and minimum time signal S MIN changes into logic 1, such that at time t 5 the pulse in trigger signal S PLS is passed to be set signal S SET and turn on power switch 15 , starting a following switch cycle. As shown in FIG.
  • each pulse in trigger signal S PLS could represent the occurrence of a voltage valley of voltage signal V ZCD and power switch 15 is turned ON at time t 5 when voltage valley VLY 3 occurs, substantially performing an operation in QR mode.
  • FIG. 7 illustrates two diagrams, the upper one showing the changes of minimum time T MIN and maximum time T MAX vs. feedback signal V FB , and the lower one showing the changes of maximum frequency f MAX and minimum frequency f MIN vs. feedback signal V FB .
  • minimum time T MIN is the earliest time that power switch controller 30 in FIG. 4 can turn ON a power switch
  • its inverse, 1/T MIN defines a maximum switching frequency f MAX that power switch controller 30 can perform.
  • 1/T MAX the inverse of maximum time T MAX , defines a minimum frequency f MIN .
  • Voltage-controllable current source 70 in FIG. 5 could be well designed to achieve the curves in FIG. 7 .
  • the output current from voltage-controllable current source 70 is a respectively-lower constant if feedback signal V FB is under reference voltage V REF2 , increases linearly if feedback signal V FB approaches from reference voltage V REF2 to reference voltage V REF3 , and is a respectively-higher constant if feedback signal V FB is over reference voltage V REF3 . It is shown in FIG. 7 that minimum time T MIN decreases as feedback signal V FB increases if feedback signal V FB is between reference voltages V REF2 and V REF3 .
  • FIG. 8 includes curve 50 illustrating the relationship between switch frequency f CYC and feedback signal V FB for power switch controller 30 in FIG. 4 .
  • the dashed curves in FIG. 8 duplicate maximum frequency f MAX and minimum frequency f MIN of FIG. 7 , and the curves in FIG. 3 showing the relationships between switch frequency f CYC and feedback signal V FB .
  • power switch controller 30 turns on power switch 15 substantially at the occurrence of the earlier voltage valley after minimum time T MIN , but no later than maximum T MAX .
  • curve 50 is limited to locate somewhere between minimum frequency f MIN and maximum frequency f MAX , and traces the highest one among curves 22 1 , 22 2 , 22 3 . .
  • switch frequency f CYC power switch controller 30 provides is somehow lower for light load when feedback signal V FB is less, because the switching of a power switch might shift to the moment when a subsequent voltage valley occurs.
  • the control node of power switch 15 is charged and discharged once, requiring a certain amount of power.
  • Less switch frequency f CYC results in less power for charging and discharging the control node of power switch 15 , increasing power conversion efficiency for light load.
  • FIGS. 9A and 9B show window providers 60 a and 60 b that are two alternatives to window provider 40 and could solve this concern, using the technology of jittering.
  • each of window providers 60 a and 60 b has counter 66 cycling its digital outputs S 0 ⁇ S n every several milliseconds while switch frequency f CYC has a clock cycle time around the order of microseconds.
  • window provider 60 a there is a digital-to-analog converter 72 that receives digital outputs S 0 ⁇ S n and generates a corresponding relatively-little current I JIT , such that the total current charging the capacitor jitters over time.
  • window provider 60 b the effective capacitance of capacitor array 76 in FIG. 9B jitters because it is slightly changed by digital outputs S 0 ⁇ S n .
  • both minimum frequency f MIN and maximum frequency f MAX are no more two constants for a certain feedback signal V FB , but jitter over time.
  • FIG. 10 illustrates the relationship between switch frequency f CYC and feedback signal V FB for power switch controller 30 in FIG. 4 if window provider 40 is embodied by window provider 60 a or 60 b .
  • the curves representing minimum frequency f MIM and maximum frequency f MAX are dashed and triple-lined to indicate that they are not constant but jittering. Shown in FIG. 10 , for very heavy load when feedback signal V FB is so high, switch frequency f CYC is no more a constant but jitters as minimum frequency f MIN does.
  • a power switch controller could switch a power switch at the moment when the voltage cross the power switch is around a voltage valley, performing almost lossless switching.
  • this valley could be the 1 st voltage valley.
  • switch frequency f CYC is limited to be between minimum frequency f MIM and maximum frequency f MAX , this valley could change into the 2 nd , 3 rd or even a further subsequent voltage valley.
  • switch frequency f CYC become lower too, saving the power to charge or discharge the control node of the power switch.
  • uttering minimum frequency f MIM prevents or reduces the concern of EMI.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

Power switch controllers and methods used therein are disclosed. An exemplifying power switch controller includes a window provider, a sensor and a logic controller. The window provider provides minimum and maximum time signals to indicate the elapses of a minimum time and a maximum time, respectively. The sensor detects a terminal of an inductive device, to generate a trigger signal. The logic controller prevents a power switch connected to the inductive device from being turned on before the elapse of the minimum time, forces the power switch to be turned on after the elapse of the maximum time, and turns on the power switch if the trigger signal is asserted.

Description

    BACKGROUND
  • The present disclosure relates generally to power supplies and the control methods used therein.
  • Power converters or adapters are devices that convert electric energy provided from batteries or power grid lines into power source with a specific voltage or current, such that electronic apparatuses are powered accordingly. For modern apparatuses that are required to be friendly to the world we live, conversion efficiency, which is the ratio of the power provided to a load powered by a power converter over the power delivered to the power converter over, is always a big concern. The less the power consumed by a power converter itself, the higher the conversion efficiency of the power converter.
  • Power converters operating in quasi-resonant (QR) mode are proved, in both theory and practice, to work more efficiently than most of other power converters, due to that power switches operated in QR mode are switched at zero current or voltage, resulting in an essentially lossless switch.
  • FIG. 1 illustrates a flyback converter 8, which is capable of operating in QR mode. Circuit 10 illustrates flyback topology, including power switch 15, primary winding PRM and secondary winding SEC of a transformer, a diode, and a current sense resistor. When power switch 15 is ON, performing a short circuit, primary winding PRM energizes. When power switch 15 is OFF, performing an open circuit, secondary winding SEC de-energizes to power node OUT through a diode. Power switch controller 18 controls ON time TON or OFF time TOFF of power switch 15, based on feedback signal VFB provided at node FB by feedback circuit 20, which monitors node OUT. The higher the feedback signal VFB, the higher the output power required to maintain the voltage at node OUT. Operating voltage source generator 12 provides voltage source Vcc at node VCC to power switch controller 18. Resistor 14 connects one terminal of auxiliary winding AUX to node ZCD of power switch controller 18, to provide the energy status of the transformer.
  • FIGS. 2A and 2B show waveforms of voltage signal VZCD at node ZCD under different load conditions. FIG. 2A corresponds to a relatively heavier load, and FIG. 2B to a relatively lighter load. It can be seen from FIGS. 2A and 2B that voltage signal VZCD starts to oscillate after the transformer de-energizes completely and results in voltage valleys VLY1, VLY2, VLY3, and so forth. The lighter the load, the earlier the completion of de-energizing, the earlier the occurrences of voltage valleys. A power supply in QR mode can operate to start energizing at the moment when any one of the voltage valleys occurs. FIG. 3 illustrates the relationships between switch frequency fCYC and feedback signal VFB at node FB, where switch frequency fCYC is the inverse of cycle time TCYC, which is the summation of ON time TON and OFF time TOFF, ON time TON referring to the time period when a power switch is ON, and OFF time TOFF to the time period when it is OFF. For example, Curve 22 1 shows the VFB-to-fCYC relationship if power switch 15 is switched at the moment when voltage valley VLY1 occurs. Curve 22 2 shows the VFB-to-fCYC relationship if power switch 15 is switched at the moment when voltage valley VLY2 occurs. And so forth. As shown in FIG. 3, if a power supply is designed to switch its power switch at a specific voltage valley, switch frequency fCYC increases adversely as feedback VFB decreases. The higher switch frequency fCYC, the higher power to charge and discharge a control node of a power switch, resulting in less conversion efficiency.
    • SUMMARY
  • Embodiments of the present invention disclose a power switch controller suitable to control a power switch connected to an inductive device. The power switch controller includes a window provider, a sensor and a logic controller. The window provider provides minimum and maximum time signals to indicate the elapses of a minimum time and a maximum time, respectively. The sensor detects a terminal of the inductive device, to generate a trigger signal. The logic controller prevents the power switch from being turned on before the elapse of the minimum time, forces the power switch to be turned on after the elapse of the maximum time, and turns on the power switch if the trigger signal is asserted.
  • Embodiments of the present invention disclose a method for controlling a power switch connected to an inductive device. A terminal of the inductive device is detected to generate a trigger signal. The power switch is turned on if the trigger signal is asserted. Before the elapse of a minimum time, the power switch is prevented from being turned on. After the elapse of a maximum time, the power switch is enforced to be turned on.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The invention can be more fully understood by the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
  • FIG. 1 illustrates a flyback converter;
  • FIGS. 2A and 2B show waveforms of voltage signal VZCD at node ZCD under different load conditions;
  • FIG. 3 illustrates the relationships between switch frequency fCYC and feedback signal VFB at node FB;
  • FIG. 4 exemplifies a power switch controller adaptable to the flayback converter of FIG. 1;
  • FIG. 5 exemplifies a window provider;
  • FIG. 6 illustrates the waveforms of signals in FIGS. 4 and 5;
  • FIG. 7 illustrates two diagrams, the upper one showing the changes of minimum time TMIN and maximum time TMAX vs. feedback signal VFB, and the lower one showing the changes of maximum frequency fMAX and minimum frequency fMIN vs. feedback signal VFB;
  • FIG. 8 includes curve 50 illustrating the relationship between switch frequency fCYC and feedback signal VFB for power switch controller 30 in FIG. 4;
  • FIGS. 9A and 9B show two window providers; and
  • FIG. 10 illustrates the relationship between switch frequency fCYC and feedback signal VFB for power switch controller 30 in FIG. 4 if window provider 40 is embodied by window provider 60 a or 60 b.
    • DETAILED DESCRIPTION
  • Objects of the present invention and more practical merits obtained by the present invention will become more apparent from the description of the embodiments which will be given below with reference to the accompanying drawings. For explanation purposes, components with equivalent or similar functionalities are represented by the same symbols. Hence components of different embodiments with the same symbol are not necessarily identical. Here, it is to be noted that the present invention is not limited thereto.
  • The following embodiments are exemplified by flyback converters, but are not intended to limit the scope of the invention. A person skilled in the art could apply the concept of the invention to converters with different topologies, such as bulk converters, buck-boost converters, boost converters, and so forth.
  • FIG. 4 exemplifies power switch controller 30 adaptable to flyback converter 8 of FIG. 1. Comparator 32, delay circuit 33 and pulse generator 36, as a whole acting as a sensor, detects one terminal of auxiliary winding AUX to generate trigger signal SPLS with pulses, each expectedly corresponding to an occurrence of a voltage valley at node ZCD. Window provider 40 provides minimum and maximum time signals, SMIN and SMAX, to indicate the elapses of a minimum time TMIN and a maximum time TMAX. Logic controller 38 includes several logic gates, controls the S terminal of SR register 34, and determines when power switch 15 is switched to be ON. Only when minimum time signal SMIN is asserted to indicate that minimum time TMIN has elapsed, trigger signal SPLS is possible to pass through logic controller 38 and, if asserted, set SR register 34. In other words, logic controller 38 prevents power switch 15 from being turned on before the elapse of minimum time TMIN. If trigger signal SPLS is not asserted and maximum time TMAX elapses, maximum time signal SMAX sets SR register 34 anyway, power switch 15 is forced to be turned ON, and the flyback converter enters into a following switch cycle. When signal VCS at current sense node CS exceeds the voltage at the inverse input of comparator 42, SR register 34 is reset and power switch 15 is switched to be OFF. Accordingly, feedback signal VFB at node FB substantially decides the peak voltage of signal VCS or the power supplied to node OUT in a switch cycle.
  • FIG. 5 exemplifies window provider 40, which receives set signal SSET, and outputs minimum and maximum time signals, SMIN and SMAX. When set signal is asserted, ramp signal VRMP is grounded. When set signal is de-asserted, ramp signal VRMP starts to increase, with a slope determined by the output current of voltage-controllable current source 70, which is controlled by feedback signal VFB at node FB. Feedback signal VFB substantially represents the power required by a load at node OUT. At the moments when ramp signal VRMP exceeds reference voltages VREFL and VREFH, minimum and maximum time signals SMIN and SMAX are toggled or asserted, respectively, indicating the elapses of minimum time TMIN and maximum time TMAX, respectively. Reference voltage VREFL should be less than reference voltage VREFH, such that minimum time signal SMIN is asserted earlier. If the output current of voltage-controllable current source 70 decreases, the slope of ramp signal VRMP is less and it takes more time for ramp signal VRMP to reach reference voltages VREFL and VREFH, such that both minimum time TMIN and maximum time TMAX increase. It can be derived by those skilled in the art that minimum time TMIN and maximum time TMAX provided in FIG. 5 are in proportion.
  • FIG. 6 illustrates the waveforms of signals in FIGS. 4 and 5. Waveforms in FIG. 6 are, from top to bottom, voltage signal VZCD at node ZCD, signal SDET from comparator 32, signal SDLY from delay circuit 33, trigger signal SPLS from pulse generator 36, set signal SSET at S terminal of SR register 34, gate signal SGATE at node GATE, ramp signal VRMP in FIG. 5, and minimum time signal SMIN from comparator 42. The pulse of set signal SSET at time t1 turns on power switch 15 and grounds ramp signal VRMP. ON time TON is determined by feedback signal VFB, such that gate signal SGATE changes at time t2, causing the rising of voltage signal VZCD, the logic change of signal SDET, and the logic change of signal SDLY, which is delayed by delay time Tdelay in comparison with signal SDET. At time t3, it is the first time that voltage signal VZCD drops across 0V after the completion of de-energization, causing after delay time Tdelay the rising edge of signal SDLY, which accordingly results in a pulse in trigger signal SPLS output from pulse generator 36. Before time t4, as ramp signal VRMP is under reference voltage VREFL, minimum time signal SMIN remains 0 in logic, such that pulses in trigger signal SPLS, if any, are blocked from reaching S terminal of SR register 34 and set signal SSET remains 0 in logic. After time t4 when minimum time TMIN has elapsed, ramp signal VRMP has exceeded reference voltage VREFL and minimum time signal SMIN changes into logic 1, such that at time t5 the pulse in trigger signal SPLS is passed to be set signal SSET and turn on power switch 15, starting a following switch cycle. As shown in FIG. 6, if delay time Tdelay is well designed, each pulse in trigger signal SPLS could represent the occurrence of a voltage valley of voltage signal VZCD and power switch 15 is turned ON at time t5 when voltage valley VLY3 occurs, substantially performing an operation in QR mode.
  • FIG. 7 illustrates two diagrams, the upper one showing the changes of minimum time TMIN and maximum time TMAX vs. feedback signal VFB, and the lower one showing the changes of maximum frequency fMAX and minimum frequency fMIN vs. feedback signal VFB. As minimum time TMIN is the earliest time that power switch controller 30 in FIG. 4 can turn ON a power switch, its inverse, 1/TMIN, defines a maximum switching frequency fMAX that power switch controller 30 can perform. Similarly, 1/TMAX, the inverse of maximum time TMAX, defines a minimum frequency fMIN.
  • Voltage-controllable current source 70 in FIG. 5 could be well designed to achieve the curves in FIG. 7. For example, the output current from voltage-controllable current source 70 is a respectively-lower constant if feedback signal VFB is under reference voltage VREF2, increases linearly if feedback signal VFB approaches from reference voltage VREF2 to reference voltage VREF3, and is a respectively-higher constant if feedback signal VFB is over reference voltage VREF3. It is shown in FIG. 7 that minimum time TMIN decreases as feedback signal VFB increases if feedback signal VFB is between reference voltages VREF2 and VREF3.
  • FIG. 8 includes curve 50 illustrating the relationship between switch frequency fCYC and feedback signal VFB for power switch controller 30 in FIG. 4. The dashed curves in FIG. 8 duplicate maximum frequency fMAX and minimum frequency fMIN of FIG. 7, and the curves in FIG. 3 showing the relationships between switch frequency fCYC and feedback signal VFB. It can be derived based on the aforementioned teaching that power switch controller 30 turns on power switch 15 substantially at the occurrence of the earlier voltage valley after minimum time TMIN, but no later than maximum TMAX. Accordingly, curve 50 is limited to locate somewhere between minimum frequency fMIN and maximum frequency fMAX, and traces the highest one among curves 22 1, 22 2, 22 3 . . . . It can be seen from FIG. 8 that switch frequency fCYC power switch controller 30 provides is somehow lower for light load when feedback signal VFB is less, because the switching of a power switch might shift to the moment when a subsequent voltage valley occurs. Within the time period of a switch cycle, the control node of power switch 15 is charged and discharged once, requiring a certain amount of power. Less switch frequency fCYC results in less power for charging and discharging the control node of power switch 15, increasing power conversion efficiency for light load.
  • As shown in FIG. 8, for very heavy load when feedback signal VFB is so high, switch frequency fCYC substantially stays at the constant defined by minimum frequency fMIN, raising the concern of electromagnetic interference (EMI). FIGS. 9A and 9B show window providers 60 a and 60 b that are two alternatives to window provider 40 and could solve this concern, using the technology of jittering. In addition to what is shown in window provider 40 of FIG. 5, each of window providers 60 a and 60 b has counter 66 cycling its digital outputs S0˜Sn every several milliseconds while switch frequency fCYC has a clock cycle time around the order of microseconds. Of window provider 60 a, there is a digital-to-analog converter 72 that receives digital outputs S0˜Sn and generates a corresponding relatively-little current IJIT, such that the total current charging the capacitor jitters over time. Of window provider 60 b, the effective capacitance of capacitor array 76 in FIG. 9B jitters because it is slightly changed by digital outputs S0˜Sn. As the current charging the capacitor or the capacitance of the capacitor array jitters, both minimum frequency fMIN and maximum frequency fMAX are no more two constants for a certain feedback signal VFB, but jitter over time. FIG. 10 illustrates the relationship between switch frequency fCYC and feedback signal VFB for power switch controller 30 in FIG. 4 if window provider 40 is embodied by window provider 60 a or 60 b. In FIG. 10, the curves representing minimum frequency fMIM and maximum frequency fMAX are dashed and triple-lined to indicate that they are not constant but jittering. Shown in FIG. 10, for very heavy load when feedback signal VFB is so high, switch frequency fCYC is no more a constant but jitters as minimum frequency fMIN does.
  • Benefits of the aforementioned embodiments include the followings. A power switch controller according to the invention could switch a power switch at the moment when the voltage cross the power switch is around a voltage valley, performing almost lossless switching. For heavy load, this valley could be the 1st voltage valley. For light load or even no load, as switch frequency fCYC is limited to be between minimum frequency fMIM and maximum frequency fMAX, this valley could change into the 2nd, 3rd or even a further subsequent voltage valley. For light load or no load, since minimum frequency fMIM and maximum frequency fMAX become lower, switch frequency fCYC become lower too, saving the power to charge or discharge the control node of the power switch. In case of the very heavy load condition, uttering minimum frequency fMIM prevents or reduces the concern of EMI.
  • While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims (13)

1. A power switch controller, suitable to control a power switch connected to an inductive device, comprising:
a window provider, for providing minimum and maximum time signals to indicate the elapses of a minimum time and a maximum time, respectively;
a sensor for detecting a terminal of the inductive device, to generate a trigger signal; and
a logic controller, for preventing the power switch from being turned on before the elapse of the minimum time, forcing the power switch to be turned on after the elapse of the maximum time, and turning on the power switch if the trigger signal is asserted.
2. The power switch controller as claimed in claim 1, wherein a feedback signal is provided to substantially represent the power required by a load, and the minimum time decreases as the feedback signal increases.
3. The power switch controller as claimed in claim 1, wherein the maximum time increases if the minimum time increases.
4. The power switch controller as claimed in claim 1, wherein the maximum time and the minimum time jitter over time.
5. The power switch controller as claimed in claim 1, wherein the maximum and minimum signals are generated based on a ramp signal.
6. The power switch controller as claimed in claim 1, wherein the inductive device is a transformer with a primary winding and an auxiliary winding, and the sensor detects a terminal of the auxiliary winding.
7. A method for controlling a power switch connected to an inductive device, comprising:
detecting a terminal of the inductive device to generate a trigger signal;
turning on the power switch if the trigger signal is asserted;
preventing the power switch from being turned on before the elapse of a minimum time; and
enforcing the power switch to be turned on after the elapse of a maximum time.
8. The method as claimed in claim 7, further comprising:
providing a feedback signal representing the power required by a load; and
decreasing the minimum time if the feedback signal is increased.
9. The method as claimed in claim 7, wherein the maximum time is in proportion to the minimum time.
10. The method as claimed in claim 7, further comprising:
uttering the maximum time over time.
11. The method as claimed in claim 7, further comprising:
providing a ramp signal;
generating a minimum time signal based on the ramp signal, to indicate the elapse of the minimum time.
12. The method as claimed in claim 11, further comprising:
generating a maximum time signal based on the ramp signal, to indicate the elapse of the maximum time.
13. The method as claimed in claim 7, wherein the inductive device is a transformer with a primary winding and an auxiliary winding, and the step of detecting detects one terminal of the auxiliary winding.
US13/163,729 2011-06-20 2011-06-20 Power switch controllers and methods used therein for improving conversion effeciency of power converters Abandoned US20120320632A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/163,729 US20120320632A1 (en) 2011-06-20 2011-06-20 Power switch controllers and methods used therein for improving conversion effeciency of power converters

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/163,729 US20120320632A1 (en) 2011-06-20 2011-06-20 Power switch controllers and methods used therein for improving conversion effeciency of power converters

Publications (1)

Publication Number Publication Date
US20120320632A1 true US20120320632A1 (en) 2012-12-20

Family

ID=47353540

Family Applications (1)

Application Number Title Priority Date Filing Date
US13/163,729 Abandoned US20120320632A1 (en) 2011-06-20 2011-06-20 Power switch controllers and methods used therein for improving conversion effeciency of power converters

Country Status (1)

Country Link
US (1) US20120320632A1 (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140036558A1 (en) * 2012-07-31 2014-02-06 Leadtrend Technology Corporation Power Controllers, Power Supplies and Control Methods Therefor
US20150029763A1 (en) * 2013-07-23 2015-01-29 Leadtrend Technology Corp. Controller for generating jitters in a quasi resonant mode and method for generating jitters in a quasi resonant mode
CN104734542A (en) * 2013-12-18 2015-06-24 绿达光电股份有限公司 Power controller for switching at the bottom of voltage valley and related control method
CN105515390A (en) * 2014-10-09 2016-04-20 立锜科技股份有限公司 Flyback power supply circuit with programmable function and control circuit and control method thereof
US20160268901A1 (en) * 2015-03-13 2016-09-15 Fuji Electric Co., Ltd. Switching power supply device control circuit and switching power supply device
US20180083538A1 (en) * 2015-10-26 2018-03-22 Dialog Semiconductor Inc. Adaptive valley mode switching
US20190013726A1 (en) * 2017-07-10 2019-01-10 Semiconductor Components Industries, Llc Method of forming a semiconductor device
US20190036458A1 (en) * 2017-07-25 2019-01-31 Weltrend Semiconductor Inc. Power Controllers and Power Converters with Configurable Feedback Loop for Different Nominal Output Voltages
US10199942B2 (en) * 2010-11-17 2019-02-05 Leadtrend Technology Corp. Controller and power supply
US10317968B2 (en) * 2017-03-28 2019-06-11 Qualcomm Incorporated Power multiplexing with an active load
US12341497B2 (en) 2023-06-23 2025-06-24 Qualcomm Incorporated Power multiplexer

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4814685A (en) * 1987-12-04 1989-03-21 Pacesetter Infusion, Ltd. Inductive power converter for use with variable input and output voltages
US5659460A (en) * 1994-11-03 1997-08-19 Vlt Corporation Switch control in quantized power converters
US5994846A (en) * 1995-10-09 1999-11-30 U.S. Philips Corporation Buck converter switching scheme
US8345456B2 (en) * 2008-11-06 2013-01-01 Fuji Electric Co., Ltd. Control system of a power factor correction circuit
US8625311B2 (en) * 2009-04-14 2014-01-07 Murata Manufacturing Co., Ltd. Switching power supply apparatus including a plurality of switching elements

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4814685A (en) * 1987-12-04 1989-03-21 Pacesetter Infusion, Ltd. Inductive power converter for use with variable input and output voltages
US5659460A (en) * 1994-11-03 1997-08-19 Vlt Corporation Switch control in quantized power converters
US5994846A (en) * 1995-10-09 1999-11-30 U.S. Philips Corporation Buck converter switching scheme
US8345456B2 (en) * 2008-11-06 2013-01-01 Fuji Electric Co., Ltd. Control system of a power factor correction circuit
US8625311B2 (en) * 2009-04-14 2014-01-07 Murata Manufacturing Co., Ltd. Switching power supply apparatus including a plurality of switching elements

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10199942B2 (en) * 2010-11-17 2019-02-05 Leadtrend Technology Corp. Controller and power supply
US20140036558A1 (en) * 2012-07-31 2014-02-06 Leadtrend Technology Corporation Power Controllers, Power Supplies and Control Methods Therefor
US20150029763A1 (en) * 2013-07-23 2015-01-29 Leadtrend Technology Corp. Controller for generating jitters in a quasi resonant mode and method for generating jitters in a quasi resonant mode
US9577515B2 (en) * 2013-07-23 2017-02-21 Leadtrend Technology Corp. Controller for generating jitters in a quasi resonant mode and method for generating jitters in a quasi resonant mode
CN104734542A (en) * 2013-12-18 2015-06-24 绿达光电股份有限公司 Power controller for switching at the bottom of voltage valley and related control method
CN105515390A (en) * 2014-10-09 2016-04-20 立锜科技股份有限公司 Flyback power supply circuit with programmable function and control circuit and control method thereof
US20160268901A1 (en) * 2015-03-13 2016-09-15 Fuji Electric Co., Ltd. Switching power supply device control circuit and switching power supply device
CN105978317A (en) * 2015-03-13 2016-09-28 富士电机株式会社 Switching power supply device control circuit and switching power supply device
US9847711B2 (en) * 2015-03-13 2017-12-19 Fuji Electric Co., Ltd. Switching power supply device control circuit and switching power supply device
US20180083538A1 (en) * 2015-10-26 2018-03-22 Dialog Semiconductor Inc. Adaptive valley mode switching
US10084382B2 (en) * 2015-10-26 2018-09-25 Dialog Semiconductor Inc. Adaptive valley mode switching
TWI676887B (en) * 2017-03-28 2019-11-11 美商高通公司 Power multiplexing with an active load
US10317968B2 (en) * 2017-03-28 2019-06-11 Qualcomm Incorporated Power multiplexing with an active load
US10199918B2 (en) * 2017-07-10 2019-02-05 Semiconductor Components Industries, Llc Method of forming a semiconductor device
US20190013726A1 (en) * 2017-07-10 2019-01-10 Semiconductor Components Industries, Llc Method of forming a semiconductor device
US10833575B2 (en) 2017-07-10 2020-11-10 Semiconductor Components Industries, Llc Method of forming a semiconductor device
US20190036458A1 (en) * 2017-07-25 2019-01-31 Weltrend Semiconductor Inc. Power Controllers and Power Converters with Configurable Feedback Loop for Different Nominal Output Voltages
US10897205B2 (en) * 2017-07-25 2021-01-19 Weltrend Semiconductor Inc. Power controllers and power converters with configurable feedback loop for different nominal output voltages
US11545904B2 (en) 2017-07-25 2023-01-03 Weltrend Semiconductor Inc. Power controllers and power converters with configurable feedback loop for different nominal output voltages
US12341497B2 (en) 2023-06-23 2025-06-24 Qualcomm Incorporated Power multiplexer

Similar Documents

Publication Publication Date Title
US20120320632A1 (en) Power switch controllers and methods used therein for improving conversion effeciency of power converters
US11736030B2 (en) Switching circuit, synchronous rectification control circuit and control method thereof
US8994351B2 (en) Smooth mode transition plateau for a power supply controller
US7940035B2 (en) Control circuit having an impedance modulation controlling power converter for saving power
CN105515355B (en) System and method for dc-dc converter
US9391528B2 (en) Active clamp circuits for flyback power converters
CN102355145B (en) Control circuit of power converter
US8880969B2 (en) Switching converter with pulse skipping mode and control method thereof
CN102969874B (en) Control circuit with deep burst mode for power converter
US20150002115A1 (en) Series-capacitor buck converter multiphase controller
US8634212B2 (en) Controller and controlling method for power converter
US9209702B2 (en) Flyback converter and method for controlling a flyback converter
US9287773B2 (en) Switch power supply controller and control method
US9698677B2 (en) Brownout recovery circuit for bootstrap capacitor and switch power supply circuit
US20120300499A1 (en) Control circuit of a switched-mode power converter and method thereof
CN107834822B (en) Controller for switch mode power converter and power converter
US8194418B2 (en) Frequency-hopping control method and module, and DC/DC converter
US7855899B2 (en) Controller with loop impedance modulation for power converter
US9991798B2 (en) Constant on-time control for power converter
US20160087534A1 (en) Methods and power controllers for primary side control
TWI487253B (en) Switching regulator controlling method and circuit
CN102891603A (en) Power controller and control method
US9046382B2 (en) Power control circuits and methods
US8476883B2 (en) Compensation circuits and control methods of switched mode power supply
CN102832817B (en) Method and circuit for controlling voltage across power switch of switching power converter

Legal Events

Date Code Title Description
AS Assignment

Owner name: SHAMROCK MICRO DEVICES CORP., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KALODKA, SIARHEI;LIN, CHIEN-LIANG;GAITUKEVICH, SERGEY;REEL/FRAME:026487/0094

Effective date: 20110614

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION