[go: up one dir, main page]

US20120074504A1 - Semiconductor device and method of fabricating the same - Google Patents

Semiconductor device and method of fabricating the same Download PDF

Info

Publication number
US20120074504A1
US20120074504A1 US13/289,111 US201113289111A US2012074504A1 US 20120074504 A1 US20120074504 A1 US 20120074504A1 US 201113289111 A US201113289111 A US 201113289111A US 2012074504 A1 US2012074504 A1 US 2012074504A1
Authority
US
United States
Prior art keywords
insulating film
film
gate electrode
gate
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/289,111
Inventor
Motoyuki Sato
Takeshi Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to US13/289,111 priority Critical patent/US20120074504A1/en
Publication of US20120074504A1 publication Critical patent/US20120074504A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0181—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET

Definitions

  • the present invention relates to a semiconductor device and a method of fabricating the same.
  • a gate insulating film decreases as downsizing of MOSFETs advances, and this poses the problem that a gate leakage current increases.
  • a high-k film having a relative dielectric constant higher than that of a silicon oxide (SiO 2 ) film is used as a gate insulating film.
  • An example of this high-k film is a hafnium silicate nitride (HfSiON) film.
  • a complementary MOS transistor (to be referred to as a CMOSFET hereinafter) including a PMOSFET and NMOSFET is to be formed, however, if this hafnium silicate nitride (HfSiON) film is used as a gate insulating film, the gate threshold voltage of the PMOSFET fluctuates more than that of the NMOSFET.
  • a CMOSFET complementary MOS transistor
  • HfSiON hafnium silicate nitride
  • a reference related to a CMOSFET using a high-k gate insulating film is as follows.
  • a semiconductor device fabrication method comprising:
  • first gate electrode via a first gate insulating film on a P-type semiconductor region formed in a surface portion of a semiconductor substrate, and forming a second gate electrode via a second gate insulating film on an N-type semiconductor region formed in the surface portion of the semiconductor substrate;
  • first insulating film on side surfaces of the first gate electrode and the first gate insulating film, and forming a second insulating film on side surfaces of the second gate electrode and the second gate insulating film;
  • first gate electrode sidewall insulating film on the side surfaces of the first insulating film, and forming a second gate electrode sidewall insulating film on the side surfaces of the second gate electrode and the second gate insulating film, thereby forming an interface insulating film in an interface between the second gate electrode and the second gate insulating film.
  • a semiconductor device comprising:
  • first gate electrode sidewall insulating film formed on side surfaces of said first gate electrode and said first gate insulating film via an insulating film
  • an N-channel transistor having a first source region and a first drain region formed on two sides of a first channel region formed in a surface portion of said P-type semiconductor region below said first gate electrode;
  • a P-channel transistor having a second source region and a second drain region formed on two sides of a second channel region formed in a surface portion of said N-type semiconductor region below said second gate electrode.
  • FIG. 1 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating a CMOSFET according to an embodiment of the present invention
  • FIG. 2 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET;
  • FIG. 3 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET;
  • FIG. 4 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET;
  • FIG. 5 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET
  • FIG. 6 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET
  • FIG. 7 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET
  • FIG. 8 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET
  • FIG. 9 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET.
  • FIG. 10 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET;
  • FIG. 11 is a graph showing the current-voltage characteristics of an NMOSFET and PMOSFET forming the CMOSFET.
  • FIG. 12 is a graph showing the current-voltage characteristics of an NMOSFET and PMOSFET forming the CMOS FET.
  • FIGS. 1 to 10 illustrate a method of fabricating a CMOSFET according to an embodiment of the present invention.
  • a resist mask having a desired pattern is formed on a semiconductor substrate 10 by photolithography, and used as a mask to ion-implant boron (B), gallium (G), indium (In), or the like.
  • a resist mask having a desired pattern is formed on the semiconductor substrate 10 , and used as a mask to ion-implant phosphorus (P), arsenic (As), antimony (Sb), or the like. Annealing is then performed to form a P-type semiconductor region 20 and N-type semiconductor region 30 as shown in FIG. 1 . Subsequently, as shown in FIG. 2 , an element isolation insulating film 40 is formed in a desired region on the semiconductor substrate 10 .
  • an insulating film made of, e.g., a hafnium silicate nitride (HfSiON) film is formed on the surface of the semiconductor substrate 10 .
  • this insulating film is not limited to the hafnium silicate nitride film. That is, it is possible to use various types of high-k films having relative dielectric constants higher than that of a silicon oxide (SiO 2 ) film.
  • Examples are a hafnium oxide (HfOx) film, a zirconium oxide (ZrOx) film, a silicate film of a hafnium oxide film, an aluminate film of a hafnium oxide film, a silicate film of a zirconium oxide film, an aluminate film of a zirconium oxide film, a silicate nitride film of a hafnium oxide film, an aluminate nitride film of a hafnium oxide film, a silicate nitride film of a zirconium oxide film, and an aluminate nitride film of a zirconium oxide film.
  • HfOx hafnium oxide
  • ZrOx zirconium oxide
  • a silicate film of a hafnium oxide film an aluminate film of a hafnium oxide film
  • a silicate film of a zirconium oxide film an a
  • Polysilicon is deposited on this insulating film by CVD or the like to form a polysilicon film.
  • a polysilicon germanium film may also be formed by depositing polysilicon germanium on the insulating film.
  • the polysilicon film and hafnium silicate nitride (HfSiON) film are sequentially patterned by lithography and RIE, thereby forming a gate electrode 70 and gate insulating film 50 on the P-type semiconductor region 20 , and a gate electrode 80 and gate insulating film 60 on the N-type semiconductor region 30 .
  • a silicon nitride (SiN) film 90 about 2 nm thick is formed on the entire surface.
  • the silicon nitride (SiN) film 90 is removed by RIE except for the silicon nitride (SiN) film 90 formed on the side surfaces of the gate electrode 70 and gate insulating film 50 , and on the side surfaces of the gate electrode 80 and gate insulating film 60 .
  • offset spacers 100 A and 100 B are formed on the side surfaces of the gate electrode 70 and gate insulating film 50
  • offset spacers 110 A and 110 B are formed on the side surfaces of the gate electrode 80 and gate insulating film 60 .
  • an N-type dopant such as phosphorus (P) is ion-implanted into the P-type semiconductor region 20 , and annealing is so performed as to diffuse this phosphorus (P), thereby forming a shallow-junction, lightly doped source extension region 120 A and drain extension region 120 B.
  • P phosphorus
  • a P-type dopant such as boron (B) is ion-implanted into the N-type semiconductor region 30 , and annealing is so performed as to diffuse this boron (B), thereby forming a shallow-junction, lightly doped source extension region 130 A and drain extension region 130 B.
  • the semiconductor substrate 10 , gate electrodes 70 and 80 , and offset spacers 100 and 110 are coated with a photoresist, and the photoresist is exposed and developed to form a resist mask 140 having a pattern which opens over the N-type semiconductor region 30 , thereby covering the P-type semiconductor region 20 with the resist mask 140 .
  • the resist mask 140 is used as a mask to etch away the offset spacers 110 A and 110 B formed in the N-type semiconductor region 30 .
  • the offset spacers 110 A and 110 B may also be removed after they are changed into an oxynitride film or oxide film by radical oxidation or thermal oxidation.
  • the source extension region 130 A and drain extension region 130 B may also be formed after the offset spacers 110 A and 110 B are removed.
  • a silicon oxide (SiO 2 ) film made of, e.g., a TEOS (tetraethoxysilane) film is formed on the entire surface of the semiconductor substrate 10 .
  • this silicon oxide (SiO 2 ) film is etched by RIE to form gate electrode side walls 150 A and 150 B on the side surfaces of the offset spacers 100 A and 100 B, and gate electrode side walls 160 A and 160 B on the side surfaces of the gate electrode 80 and gate insulating film 60 .
  • the gate electrode side walls 160 A and 160 B act on the interface between the gate electrode 80 and gate insulating film 60 formed on the N-type semiconductor region 30 , thereby forming a low-k interface insulating film (interface layer) 170 made of a silicon oxide (SiO 2 ) film about 2 to 3 nm thick in the interface between the gate electrode 80 and gate insulating film 60 .
  • interface layer silicon oxide
  • the offset spacers 100 A and 100 B are already formed on the side surfaces of the gate electrode 70 and gate insulating film 50 formed on the P-type semiconductor region 20 . Therefore, even when the gate electrode side walls 150 A and 150 B are formed, they do not act on the interface between the gate electrode 70 and gate insulating film 50 , so almost no interface insulating film forms.
  • a silicon oxide film made of a TEOS film is used as the gate electrode side walls 150 and 160 in this embodiment, it is also possible to use any of various silicon oxide films such as HTO (High Temperature Oxide), BPSG (Borophosphosilicate Glass), PSG (Phosphosilicate Glass), and BSG (Boron-Silicate Glass).
  • an N-type dopant such as phosphorus (P) is ion-implanted into the P-type semiconductor region 20 , and annealing is so performed as to diffuse this phosphorus (P), thereby forming a source region 180 A and drain region 180 B.
  • P phosphorus
  • a P-type dopant such as boron (B) is ion-implanted into the N-type semiconductor region 30 , and annealing is so performed as to diffuse this boron (B), thereby forming a source region 190 A and drain region 190 B.
  • silicides 200 A to 200 C for reducing the parasitic resistance on the surface of the gate electrode 70 and in the surface portions of the source region 180 A and drain region 180 B, and form silicides 210 A to 210 C on the surface of the gate electrode 80 and in the surface portions of the source region 190 A and drain region 190 B.
  • a metal film made of, e.g., cobalt (Co), nickel (Ni), or platinum (Pt) is formed by sputtering
  • annealing is performed to form silicides 200 A to 200 C for reducing the parasitic resistance on the surface of the gate electrode 70 and in the surface portions of the source region 180 A and drain region 180 B, and form silicides 210 A to 210 C on the surface of the gate electrode 80 and in the surface portions of the source region 190 A and drain region 190 B.
  • an interlayer dielectric film (not shown) is formed, and a wiring step is performed by forming contact plugs (not shown) in this interlayer dielectric film, thereby forming a CMOSFET 240 including an NMOSFET 220 and PMOSFET 230 .
  • the element isolation insulating film 40 is formed in the surface portion of the semiconductor substrate 10 .
  • the gate electrode 70 is formed via the gate insulating film 50 formed on the surface of the semiconductor substrate 10 .
  • the gate electrode side walls 150 A and 150 B are formed on the side surfaces of the gate electrode 70 and gate insulating film 50 via the offset spacers 100 A and 100 B about 2 nm thick. Also, a channel region 250 is formed near the surface of the
  • the source extension region 120 A and drain extension region 120 B are formed on the two ends of the channel region 250 .
  • the source region 180 A is formed between the source extension region 120 A and an element isolation insulating film (not shown).
  • the drain region 180 B is formed between the drain extension region 120 B and element isolation insulating film 40 .
  • silicides 200 A to 200 C for reducing the parasitic resistance are formed on the surface of the gate electrode 70 and on the surfaces of the source region 180 A and drain region 180 B.
  • the gate electrode 80 is formed near the central portion of the N-type semiconductor region 30 via the gate insulating film 60 formed on the surface of the semiconductor substrate 10 , and the interface insulating film 170 made of a silicon oxide (SiO 2 ) film about 2 to 3 nm thick.
  • the gate electrode side walls 160 A and 160 B are formed on the side surfaces of the gate electrode 80 , interface insulating film 170 , and gate insulating film 60 . Also, a channel region 260 is formed near the surface of the semiconductor substrate 10 below the gate electrode 80 .
  • the source extension region 130 A and drain extension region 130 B are formed on the two ends of the channel region 260 .
  • the source region 190 A is formed between the source extension region 130 A and element isolation insulating film 40 .
  • the drain region 190 B is formed between the drain extension region 130 B and an element isolation insulating film (not shown).
  • the silicides 210 A to 210 C for reducing the parasitic resistance are formed on the surface of the gate electrode 80 and on the surfaces of the source region 190 A and drain region 190 B.
  • FIGS. 11 and 12 illustrate the current-voltage characteristics of the NMOSFET and PMOSFET forming the CMOSFET.
  • the abscissa indicates the gate voltage applied to the gate electrode
  • the ordinate indicates the drain current (the driving current flowing through the channel region).
  • the gate threshold voltage of the PMOSFET changes by about 0.6 V in the negative direction, but that of the NMOSFET changes only by about 0.2 V in the positive direction, compared to the case in which a silicon oxide (SiO 2 ) film is used as the gate insulating film.
  • the driving current flowing through the channel region reduces more in the PMOSFET than in the NMOSFET, so the drivability of the PMOSFET decreases. This produces a large difference in drivability between the PMOSFET and NMOSFET.
  • the offset spacers 100 A and 100 B are formed on the side surfaces of the gate electrode 70 and gate insulating film 50 only in the NMOSFET 220 , and no offset spacers are formed in the PMOSFET 230 , thereby forming the interface insulating film 170 in the interface between the gate electrode 80 and gate insulating film 60 in the PMOSFET 230 .
  • Negative fixed electric charge is generated in the interface insulating film 170 .
  • the gate threshold voltage of the PMOSFET 230 changes by about 0.16 V in the positive direction ( FIG. 12 ), compared to the case in which no interface insulating film is formed.
  • the driving current largely increases, and this improves the drivability of the PMOSFET 230 , compared to the case in which no interface insulating film is formed. Consequently, the difference in drivability between the NMOSFET 220 and PMOSFET 230 can be reduced.
  • the semiconductor device and the method of fabricating the same according to the above embodiment can improve the drivability of a PMOSFET in a CMOSFET using a high-k gate insulating film.
  • the above embodiment is merely an example and does not limit the present invention.

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A semiconductor device fabrication method includes forming a first gate electrode via a first gate insulating film on a P-type semiconductor region formed in a surface portion of a semiconductor substrate; forming a second gate electrode via a second gate insulating film on an N-type semiconductor region formed in the surface portion of the semiconductor substrate; forming a first insulating film; forming a second insulating film; forming a mask having a pattern corresponding to the P-type semiconductor region; etching away the second insulating film by using the mask; removing the mask; and forming a first gate electrode sidewall insulating film and forming a second gate electrode sidewall insulating film.

Description

    CROSS REFERENCE TO RELATED APPLICATION
  • This application is based upon and claims benefit of priority under 35 USC §119 from the Japanese Patent Application No. 2005-281537, filed on Sep. 28, 2005, the entire contents of which are incorporated herein by reference.
    • BACKGROUND OF THE INVENTION
  • The present invention relates to a semiconductor device and a method of fabricating the same.
  • Recently, the film thickness of a gate insulating film decreases as downsizing of MOSFETs advances, and this poses the problem that a gate leakage current increases. To suppress this gate leakage current, therefore, it is proposed to use a high-k film having a relative dielectric constant higher than that of a silicon oxide (SiO2) film as a gate insulating film. An example of this high-k film is a hafnium silicate nitride (HfSiON) film.
  • When a complementary MOS transistor (to be referred to as a CMOSFET hereinafter) including a PMOSFET and NMOSFET is to be formed, however, if this hafnium silicate nitride (HfSiON) film is used as a gate insulating film, the gate threshold voltage of the PMOSFET fluctuates more than that of the NMOSFET.
  • In this case, a driving current flowing through a channel region reduces more in the PMOSFET than in the NMOSFET, so the drivability of the PMOSFET decreases. This produces a large difference in drivability between the PMOSFET and NMOSFET.
  • A reference related to a CMOSFET using a high-k gate insulating film is as follows.
  • Japanese Patent Laid-Open No. 2004-289061
    • SUMMARY OF THE INVENTION
  • According to one aspect of the invention, there is provided a semiconductor device fabrication method comprising:
  • forming a first gate electrode via a first gate insulating film on a P-type semiconductor region formed in a surface portion of a semiconductor substrate, and forming a second gate electrode via a second gate insulating film on an N-type semiconductor region formed in the surface portion of the semiconductor substrate;
  • forming a first insulating film on side surfaces of the first gate electrode and the first gate insulating film, and forming a second insulating film on side surfaces of the second gate electrode and the second gate insulating film;
  • forming a mask having a pattern corresponding to the P-type semiconductor region;
  • etching away the second insulating film by using the mask;
  • removing the mask; and
  • forming a first gate electrode sidewall insulating film on the side surfaces of the first insulating film, and forming a second gate electrode sidewall insulating film on the side surfaces of the second gate electrode and the second gate insulating film, thereby forming an interface insulating film in an interface between the second gate electrode and the second gate insulating film.
  • According to one aspect of the invention, there is provided a semiconductor device comprising:
  • a first gate insulating film formed on a P-type semiconductor region in a surface portion of a semiconductor substrate;
  • a first gate electrode formed on said first gate insulating film;
  • a first gate electrode sidewall insulating film formed on side surfaces of said first gate electrode and said first gate insulating film via an insulating film;
  • an N-channel transistor having a first source region and a first drain region formed on two sides of a first channel region formed in a surface portion of said P-type semiconductor region below said first gate electrode;
  • a second gate insulating film formed on an N-type semiconductor region in the surface portion of said semiconductor substrate;
  • a second gate electrode formed on said second gate insulating film via an interface insulating film;
  • a second gate electrode sidewall insulating film formed on side surfaces of said second gate electrode, said interface insulating film, and said second gate insulating film; and
  • a P-channel transistor having a second source region and a second drain region formed on two sides of a second channel region formed in a surface portion of said N-type semiconductor region below said second gate electrode.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating a CMOSFET according to an embodiment of the present invention;
  • FIG. 2 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET;
  • FIG. 3 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET;
  • FIG. 4 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET;
  • FIG. 5 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET;
  • FIG. 6 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET;
  • FIG. 7 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET;
  • FIG. 8 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET;
  • FIG. 9 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET;
  • FIG. 10 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a method of fabricating the CMOSFET;
  • FIG. 11 is a graph showing the current-voltage characteristics of an NMOSFET and PMOSFET forming the CMOSFET; and
  • FIG. 12 is a graph showing the current-voltage characteristics of an NMOSFET and PMOSFET forming the CMOS FET.
    •  DETAILED DESCRIPTION OF THE INVENTION
  • An embodiment of the present invention will be described below with reference to the accompanying drawings.
  • FIGS. 1 to 10 illustrate a method of fabricating a CMOSFET according to an embodiment of the present invention. First, a resist mask having a desired pattern is formed on a semiconductor substrate 10 by photolithography, and used as a mask to ion-implant boron (B), gallium (G), indium (In), or the like.
  • Similarly, a resist mask having a desired pattern is formed on the semiconductor substrate 10, and used as a mask to ion-implant phosphorus (P), arsenic (As), antimony (Sb), or the like. Annealing is then performed to form a P-type semiconductor region 20 and N-type semiconductor region 30 as shown in FIG. 1. Subsequently, as shown in FIG. 2, an element isolation insulating film 40 is formed in a desired region on the semiconductor substrate 10.
  • After that, an insulating film made of, e.g., a hafnium silicate nitride (HfSiON) film is formed on the surface of the semiconductor substrate 10. Note that this insulating film is not limited to the hafnium silicate nitride film. That is, it is possible to use various types of high-k films having relative dielectric constants higher than that of a silicon oxide (SiO2) film. Examples are a hafnium oxide (HfOx) film, a zirconium oxide (ZrOx) film, a silicate film of a hafnium oxide film, an aluminate film of a hafnium oxide film, a silicate film of a zirconium oxide film, an aluminate film of a zirconium oxide film, a silicate nitride film of a hafnium oxide film, an aluminate nitride film of a hafnium oxide film, a silicate nitride film of a zirconium oxide film, and an aluminate nitride film of a zirconium oxide film.
  • Polysilicon is deposited on this insulating film by CVD or the like to form a polysilicon film. In this case, a polysilicon germanium film may also be formed by depositing polysilicon germanium on the insulating film.
  • As shown in FIG. 3, the polysilicon film and hafnium silicate nitride (HfSiON) film are sequentially patterned by lithography and RIE, thereby forming a gate electrode 70 and gate insulating film 50 on the P-type semiconductor region 20, and a gate electrode 80 and gate insulating film 60 on the N-type semiconductor region 30.
  • As shown in FIG. 4, a silicon nitride (SiN) film 90 about 2 nm thick is formed on the entire surface. As shown in FIG. 5, the silicon nitride (SiN) film 90 is removed by RIE except for the silicon nitride (SiN) film 90 formed on the side surfaces of the gate electrode 70 and gate insulating film 50, and on the side surfaces of the gate electrode 80 and gate insulating film 60. In this manner, offset spacers 100A and 100B are formed on the side surfaces of the gate electrode 70 and gate insulating film 50, and offset spacers 110A and 110B are formed on the side surfaces of the gate electrode 80 and gate insulating film 60.
  • As shown in FIG. 6, an N-type dopant such as phosphorus (P) is ion-implanted into the P-type semiconductor region 20, and annealing is so performed as to diffuse this phosphorus (P), thereby forming a shallow-junction, lightly doped source extension region 120A and drain extension region 120B.
  • Also, a P-type dopant such as boron (B) is ion-implanted into the N-type semiconductor region 30, and annealing is so performed as to diffuse this boron (B), thereby forming a shallow-junction, lightly doped source extension region 130A and drain extension region 130B.
  • As shown in FIG. 7, the semiconductor substrate 10, gate electrodes 70 and 80, and offset spacers 100 and 110 are coated with a photoresist, and the photoresist is exposed and developed to form a resist mask 140 having a pattern which opens over the N-type semiconductor region 30, thereby covering the P-type semiconductor region 20 with the resist mask 140.
  • The resist mask 140 is used as a mask to etch away the offset spacers 110A and 110B formed in the N-type semiconductor region 30.
  • Note that wet etching using hydrofluoric acid (HF) may also be performed instead of RIE. In this case, the offset spacers 110A and 110B may also be removed after they are changed into an oxynitride film or oxide film by radical oxidation or thermal oxidation. Alternatively, the source extension region 130A and drain extension region 130B may also be formed after the offset spacers 110A and 110B are removed.
  • As shown in FIG. 8, after the resist mask 90 is removed, a silicon oxide (SiO2) film made of, e.g., a TEOS (tetraethoxysilane) film is formed on the entire surface of the semiconductor substrate 10. As shown in FIG. 9, this silicon oxide (SiO2) film is etched by RIE to form gate electrode side walls 150A and 150B on the side surfaces of the offset spacers 100A and 100B, and gate electrode side walls 160A and 160B on the side surfaces of the gate electrode 80 and gate insulating film 60.
  • In this state, the gate electrode side walls 160A and 160B act on the interface between the gate electrode 80 and gate insulating film 60 formed on the N-type semiconductor region 30, thereby forming a low-k interface insulating film (interface layer) 170 made of a silicon oxide (SiO2) film about 2 to 3 nm thick in the interface between the gate electrode 80 and gate insulating film 60.
  • On the other hand, the offset spacers 100A and 100B are already formed on the side surfaces of the gate electrode 70 and gate insulating film 50 formed on the P-type semiconductor region 20. Therefore, even when the gate electrode side walls 150A and 150B are formed, they do not act on the interface between the gate electrode 70 and gate insulating film 50, so almost no interface insulating film forms.
  • Although a silicon oxide film made of a TEOS film is used as the gate electrode side walls 150 and 160 in this embodiment, it is also possible to use any of various silicon oxide films such as HTO (High Temperature Oxide), BPSG (Borophosphosilicate Glass), PSG (Phosphosilicate Glass), and BSG (Boron-Silicate Glass).
  • As shown in FIG. 10, an N-type dopant such as phosphorus (P) is ion-implanted into the P-type semiconductor region 20, and annealing is so performed as to diffuse this phosphorus (P), thereby forming a source region 180A and drain region 180B.
  • Also, a P-type dopant such as boron (B) is ion-implanted into the N-type semiconductor region 30, and annealing is so performed as to diffuse this boron (B), thereby forming a source region 190A and drain region 190B.
  • After a metal film made of, e.g., cobalt (Co), nickel (Ni), or platinum (Pt) is formed by sputtering, annealing is performed to form silicides 200A to 200C for reducing the parasitic resistance on the surface of the gate electrode 70 and in the surface portions of the source region 180A and drain region 180B, and form silicides 210A to 210C on the surface of the gate electrode 80 and in the surface portions of the source region 190A and drain region 190B.
  • Subsequently, an interlayer dielectric film (not shown) is formed, and a wiring step is performed by forming contact plugs (not shown) in this interlayer dielectric film, thereby forming a CMOSFET 240 including an NMOSFET 220 and PMOSFET 230.
  • In the CMOSFET 240 fabricated by the above method, as shown in FIG. 10, the element isolation insulating film 40 is formed in the surface portion of the semiconductor substrate 10.
  • Near the central portion of the P-type semiconductor region 20 isolated by the element isolation insulating film 40, the gate electrode 70 is formed via the gate insulating film 50 formed on the surface of the semiconductor substrate 10.
  • The gate electrode side walls 150A and 150B are formed on the side surfaces of the gate electrode 70 and gate insulating film 50 via the offset spacers 100A and 100B about 2 nm thick. Also, a channel region 250 is formed near the surface of the
  • semiconductor substrate 10 below the gate electrode 70. The source extension region 120A and drain extension region 120B are formed on the two ends of the channel region 250.
  • The source region 180A is formed between the source extension region 120A and an element isolation insulating film (not shown). The drain region 180B is formed between the drain extension region 120B and element isolation insulating film 40.
  • In addition, the silicides 200A to 200C for reducing the parasitic resistance are formed on the surface of the gate electrode 70 and on the surfaces of the source region 180A and drain region 180B.
  • On the other hand, the gate electrode 80 is formed near the central portion of the N-type semiconductor region 30 via the gate insulating film 60 formed on the surface of the semiconductor substrate 10, and the interface insulating film 170 made of a silicon oxide (SiO2) film about 2 to 3 nm thick.
  • The gate electrode side walls 160A and 160B are formed on the side surfaces of the gate electrode 80, interface insulating film 170, and gate insulating film 60. Also, a channel region 260 is formed near the surface of the semiconductor substrate 10 below the gate electrode 80.
  • The source extension region 130A and drain extension region 130B are formed on the two ends of the channel region 260.
  • The source region 190A is formed between the source extension region 130A and element isolation insulating film 40.
  • The drain region 190B is formed between the drain extension region 130B and an element isolation insulating film (not shown).
  • In addition, the silicides 210A to 210C for reducing the parasitic resistance are formed on the surface of the gate electrode 80 and on the surfaces of the source region 190A and drain region 190B.
  • FIGS. 11 and 12 illustrate the current-voltage characteristics of the NMOSFET and PMOSFET forming the CMOSFET. In each of FIGS. 11 and 12, the abscissa indicates the gate voltage applied to the gate electrode, and the ordinate indicates the drain current (the driving current flowing through the channel region).
  • As shown in FIG. 11, when a hafnium silicate nitride (HfSiON) film is used as the gate insulating film, the gate threshold voltage of the PMOSFET changes by about 0.6 V in the negative direction, but that of the NMOSFET changes only by about 0.2 V in the positive direction, compared to the case in which a silicon oxide (SiO2) film is used as the gate insulating film.
  • As described above, the driving current flowing through the channel region reduces more in the PMOSFET than in the NMOSFET, so the drivability of the PMOSFET decreases. This produces a large difference in drivability between the PMOSFET and NMOSFET.
  • In this embodiment, therefore, the offset spacers 100A and 100B are formed on the side surfaces of the gate electrode 70 and gate insulating film 50 only in the NMOSFET 220, and no offset spacers are formed in the PMOSFET 230, thereby forming the interface insulating film 170 in the interface between the gate electrode 80 and gate insulating film 60 in the PMOSFET 230.
  • Negative fixed electric charge is generated in the interface insulating film 170. When the interface insulating film 170 is formed, therefore, the gate threshold voltage of the PMOSFET 230 changes by about 0.16 V in the positive direction (FIG. 12), compared to the case in which no interface insulating film is formed.
  • As described above, when the interface insulating film 170 is formed, the driving current largely increases, and this improves the drivability of the PMOSFET 230, compared to the case in which no interface insulating film is formed. Consequently, the difference in drivability between the NMOSFET 220 and PMOSFET 230 can be reduced.
  • Accordingly, the semiconductor device and the method of fabricating the same according to the above embodiment can improve the drivability of a PMOSFET in a CMOSFET using a high-k gate insulating film.
  • Note that the above embodiment is merely an example and does not limit the present invention. For example, it is also possible to form an N-type semiconductor region in the surface portion of a P-type semiconductor substrate, and a P-type semiconductor region in the surface portion of an N-type semiconductor substrate, instead of forming the P-type semiconductor region 20 and N-type semiconductor region 30 in the surface portion of the semiconductor substrate 10.

Claims (6)

1.-13. (canceled)
14. A semiconductor device comprising:
a first gate insulating film formed on a P-type semiconductor region in a surface portion of a semiconductor substrate;
a first gate electrode formed on said first gate insulating film;
a first gate electrode sidewall insulating film formed on side surfaces of said first gate electrode and said first gate insulating film via an insulating film;
an N-channel transistor having a first source region and a first drain region formed on two sides of a first channel region formed in a surface portion of said P-type semiconductor region below said first gate electrode;
a second gate insulating film formed on an N-type semiconductor region in the surface portion of said semiconductor substrate;
a second gate electrode formed on said second gate insulating film via an interface insulating film;
a second gate electrode sidewall insulating film formed on side surfaces of said second gate electrode, said interface insulating film, and said second gate insulating film; and
a P-channel transistor having a second source region and a second drain region formed on two sides of a second channel region formed in a surface portion of said N-type semiconductor region below said second gate electrode.
15. A device according to claim 14, wherein each of said first gate insulating film and said second gate insulating film is made of a material selected from the group consisting of a hafnium oxide film, a zirconium oxide film, a silicate film of a hafnium oxide film, an aluminate film of a hafnium oxide film, a silicate film of a zirconium oxide film, an aluminate film of a zirconium oxide film, a silicate nitride film of a hafnium oxide film, an aluminate nitride film of a hafnium oxide film, a silicate nitride film of a zirconium oxide film, and an aluminate nitride film of a zirconium oxide film.
16. A device according to claim 14, wherein said interface insulating film is made of a silicon oxide film, and has a film thickness of 2 to 3 nm.
17. A device according to claim 14, wherein said insulating film is made of a silicon nitride film, and has a film thickness of about 2 nm.
18. A method according to claim 14, wherein said first gate electrode sidewall insulating film and said second gate electrode sidewall insulating film are made of a same material.
US13/289,111 2005-09-28 2011-11-04 Semiconductor device and method of fabricating the same Abandoned US20120074504A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/289,111 US20120074504A1 (en) 2005-09-28 2011-11-04 Semiconductor device and method of fabricating the same

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2005-281537 2005-09-28
JP2005281537A JP5072209B2 (en) 2005-09-28 2005-09-28 Semiconductor device and manufacturing method thereof
US11/377,686 US8076193B2 (en) 2005-09-28 2006-03-17 CMOS device fabrication method with PMOS interface insulating film formed concurrently with sidewall insulating film
US13/289,111 US20120074504A1 (en) 2005-09-28 2011-11-04 Semiconductor device and method of fabricating the same

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US11/377,686 Division US8076193B2 (en) 2005-09-28 2006-03-17 CMOS device fabrication method with PMOS interface insulating film formed concurrently with sidewall insulating film

Publications (1)

Publication Number Publication Date
US20120074504A1 true US20120074504A1 (en) 2012-03-29

Family

ID=37892817

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/377,686 Expired - Fee Related US8076193B2 (en) 2005-09-28 2006-03-17 CMOS device fabrication method with PMOS interface insulating film formed concurrently with sidewall insulating film
US13/289,111 Abandoned US20120074504A1 (en) 2005-09-28 2011-11-04 Semiconductor device and method of fabricating the same

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US11/377,686 Expired - Fee Related US8076193B2 (en) 2005-09-28 2006-03-17 CMOS device fabrication method with PMOS interface insulating film formed concurrently with sidewall insulating film

Country Status (2)

Country Link
US (2) US8076193B2 (en)
JP (1) JP5072209B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9202906B2 (en) 2013-03-14 2015-12-01 Northrop Grumman Systems Corporation Superlattice crenelated gate field effect transistor

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5527080B2 (en) * 2010-07-22 2014-06-18 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device
US8772118B2 (en) * 2011-07-08 2014-07-08 Texas Instruments Incorporated Offset screen for shallow source/drain extension implants, and processes and integrated circuits

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6504214B1 (en) * 2002-01-11 2003-01-07 Advanced Micro Devices, Inc. MOSFET device having high-K dielectric layer
US6696327B1 (en) * 2003-03-18 2004-02-24 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
US20050067704A1 (en) * 2003-09-26 2005-03-31 Akio Kaneko Semiconductor device and method of manufacturing the same
US7344934B2 (en) * 2004-12-06 2008-03-18 Infineon Technologies Ag CMOS transistor and method of manufacture thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09205151A (en) * 1996-01-26 1997-08-05 Sony Corp Method of manufacturing complementary semiconductor device
US6187645B1 (en) 1999-01-19 2001-02-13 United Microelectronics Corp. Method for manufacturing semiconductor device capable of preventing gate-to-drain capacitance and eliminating birds beak formation
JP4524995B2 (en) 2003-03-25 2010-08-18 ルネサスエレクトロニクス株式会社 Semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6504214B1 (en) * 2002-01-11 2003-01-07 Advanced Micro Devices, Inc. MOSFET device having high-K dielectric layer
US6696327B1 (en) * 2003-03-18 2004-02-24 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
US20050067704A1 (en) * 2003-09-26 2005-03-31 Akio Kaneko Semiconductor device and method of manufacturing the same
US7344934B2 (en) * 2004-12-06 2008-03-18 Infineon Technologies Ag CMOS transistor and method of manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9202906B2 (en) 2013-03-14 2015-12-01 Northrop Grumman Systems Corporation Superlattice crenelated gate field effect transistor

Also Published As

Publication number Publication date
US8076193B2 (en) 2011-12-13
JP2007095887A (en) 2007-04-12
JP5072209B2 (en) 2012-11-14
US20070069303A1 (en) 2007-03-29

Similar Documents

Publication Publication Date Title
TWI399798B (en) Method of manufacturing semiconductor device with metal gate stack
US7723192B2 (en) Integrated circuit long and short channel metal gate devices and method of manufacture
US7381649B2 (en) Structure for a multiple-gate FET device and a method for its fabrication
CN101728328B (en) Semiconductor device and method of fabricating a semiconductor device having a metal gate stack
CN102376538B (en) Method of forming polysilicon resistor device and semiconductor device
US20250142932A1 (en) Contacts for Semiconductor Devices and Methods of Forming the Same
US9741810B2 (en) Strained channel of gate-all-around transistor
US20090090977A1 (en) Resistor and fet formed from the metal portion of a mosfet metal gate stack
US8084828B2 (en) Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods
JP2009503902A (en) Metal gate MOSFET obtained by complete conversion to semiconductor metal alloy and method of manufacturing the same
CN103137624A (en) High gate density devices and methods
US7187031B2 (en) Semiconductor device having a low dielectric constant film and manufacturing method thereof
KR20030050995A (en) Method for fabricating high-integrated transistor
US20060157750A1 (en) Semiconductor device having etch-resistant L-shaped spacer and fabrication method thereof
US7521380B2 (en) Methods for fabricating a stress enhanced semiconductor device having narrow pitch and wide pitch transistors
CN101743630A (en) MOS transistor for thin SOI integration and fabrication method thereof
US20120074504A1 (en) Semiconductor device and method of fabricating the same
US20060237788A1 (en) Semiconductor device and its fabrication method
JP4939548B2 (en) Method for manufacturing a semiconductor device structure
US6958278B2 (en) Semiconductor devices and methods for fabricating the same
US20180096894A1 (en) Method of forming a semiconductor device structure and semiconductor device structure
US20060226558A1 (en) Method of manufacturing a semiconductor device and semiconductor device
US7348233B1 (en) Methods for fabricating a CMOS device including silicide contacts
US11251095B2 (en) High gain transistor for analog applications
JP5073158B2 (en) Semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION