[go: up one dir, main page]

US20120018862A1 - Semiconductor package - Google Patents

Semiconductor package Download PDF

Info

Publication number
US20120018862A1
US20120018862A1 US13/248,045 US201113248045A US2012018862A1 US 20120018862 A1 US20120018862 A1 US 20120018862A1 US 201113248045 A US201113248045 A US 201113248045A US 2012018862 A1 US2012018862 A1 US 2012018862A1
Authority
US
United States
Prior art keywords
ground
die pad
wires
leads
bar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/248,045
Inventor
Nan-Jang Chen
Yau-Wai Wong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MediaTek Inc
Original Assignee
MediaTek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MediaTek Inc filed Critical MediaTek Inc
Priority to US13/248,045 priority Critical patent/US20120018862A1/en
Assigned to MEDIATEK INC. reassignment MEDIATEK INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, NAN-JANG, WONG, YAU-WAI
Publication of US20120018862A1 publication Critical patent/US20120018862A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48253—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a potential ring of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10162—Shape being a cuboid with a square active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Definitions

  • This invention relates generally to packaging of semiconductors, and in particular, to a leadframe semiconductor package.
  • a conventional leadframe typically includes a plurality of metal leads temporarily held together in a planar arrangement about a central region during package manufacture by a rectangular frame.
  • a die pad is supported in the central region by a plurality of tie bars that attach to the frame.
  • the leads extend from a first end integral with the frame to an opposite second end adjacent to, but spaced apart from, the die pad.
  • a semiconductor die is attached to the die pad.
  • Wire-bonding pads on the die are then connected to selected ones of the inner ends of the leads by fine, conductive bonding wires to convey power, ground or signals between the die and the leads.
  • a protective body of an epoxy resin is molded over the assembly to enclose and seal the die, the inner ends of the leads, and the wire bonds against harmful environmental elements.
  • the rectangular frame and the outer ends of the leads are left exposed outside of the body, and after molding, the frame is cut away from the leads and discarded, and the outer ends of the leads are appropriately formed for interconnection of the package with an external printed circuit board.
  • E-pad exposed die pad
  • the exposed die pad acts as a heat sink and can improve the heat-dissipation efficiency.
  • the exposed die pad is electrically connected to a ground plane of the external printed circuit board.
  • the E-pad leadframe package is subject to attacks of moisture.
  • the ground wires extended from the ground pads of the semiconductor die are not directly bonded onto the surface of the die pad, but instead the ground wires are bonded to a rectangular ring shaped ground bridge bar that encircles the die pad at different downset planes.
  • the ground bridge bar is supported by tie bars that connected with the die pad.
  • the prior art leadframe package with such ground bridge bar configuration has a shortcoming of that the analog and digital ground wires randomly bonded together onto the ground bridge bar can result in noise or ground coupling, which is also known as water wave effects in TV systems.
  • Another shortcoming is that the ground bridge bar is vulnerable to twist and deform, leading to poor bonding strength. It is therefore desirable to provide an improved leadframe package structure that may eliminate the aforesaid digital and analog ground coupling and the water wave effects in TV systems.
  • a semiconductor package including a die pad; a semiconductor die mounted on the die pad; a plurality of leads in a first horizontal plane disposed along peripheral edges of the die pad; a ground bar downset from the first horizontal plane to a second horizontal plane between the leads and the die pad; a plurality of downset tie bars connecting the ground bar with the die pad; a plurality of ground wires bonding to both of the ground bar and the die pad; and a molding compound at least partially encapsulating the die pad, inner ends of the leads such that bottom surface of the die pad is exposed within the molding compound.
  • a semiconductor package includes a die pad; a semiconductor die mounted on the die pad; a plurality of leads in a first horizontal plane disposed along peripheral edges of the die pad; a first ground bar downset from the first horizontal plane to a second horizontal plane; a second ground bar flush with the leads; a first downset tie bar connecting the first ground bar to the die pad; a second downset tie bar connecting the second ground bar with the first ground bar; a plurality of first ground wires for conveying digital ground bonding to the first ground bar; a plurality of second ground wires for conveying analog ground bonding to the second ground bar; and a molding compound at least partially encapsulating the die pad, inner ends of the leads such that bottom surface of the die pad is exposed within the molding compound.
  • FIG. 1 is a top view of a semiconductor package according to one embodiment of the present invention.
  • FIG. 2 is a schematic, cross-sectional view of the semiconductor package of FIG. 1 ;
  • FIG. 3 shows some examples of the separated ground bar segments according to this invention
  • FIG. 4 is a schematic, cross-sectional view of a semiconductor package in accordance with another embodiment of this invention.
  • FIG. 5 is a partial plan view of the semiconductor package in FIG. 4 .
  • E-pad LQFP exposed pad low-profile quad flat package
  • one problem relates to delamination of the leadframe components from the plastic package body, and the attendant problem of penetration of the package by moisture.
  • the various parts of a semiconductor package experience greatly different amounts of thermal expansion and contraction with temperature changes due to the relatively large differences in the coefficients of thermal expansion of their respective materials, e.g., metal, epoxy resin, and silicon.
  • the leadframe components can become delaminated from the package body with temperature cycling of the package during manufacture or operation.
  • ground wires are typically not bonded onto the surface of the die pad. Instead, the ground wires, either digital ground wires or analog ground wires, are bonded to a ground bridge bar that encircles the die pad at different downset planes. However, such configuration results in ground signal coupling noise.
  • the present invention addresses this problem.
  • FIG. 1 is a top view of a semiconductor package according to one embodiment of the present invention.
  • FIG. 2 is a schematic, cross-sectional view of the semiconductor package of FIG. 1 .
  • a semiconductor package 10 comprises a semiconductor die 20 mounted onto the first surface 110 a of a die pad 110 , a plurality of leads 120 in a first horizontal plane disposed along the peripheral edges of the die pad 110 , a ground bar 130 downset from the first horizontal plane to a second horizontal plane between inner ends 120 a of the leads 120 and the die pad 110 , four connecting bars 142 extending outward from four corners of the die pad 110 , and a plurality of downset tie bars 144 connecting the ground bar 130 with the die pad 110 .
  • a molding compound 30 at least partially encapsulates the die pad 110 , the inner ends 120 a of the leads 120 such that the bottom surface 110 b of the die pad 110 is exposed within the molding compound 30 .
  • a peripheral groove 112 is etched into the first surface 110 a of the die pad 110 and is disposed around the semiconductor die 20 .
  • a plating layer 114 such as silver or noble metals may be formed within the peripheral groove 112 for wire bonding purposes.
  • the peripheral groove 112 can increase the coupling strength.
  • the bottom surface 110 b of the die pad 110 may be partially etched along the periphery of the die pad 110 to form a step 116 .
  • the semiconductor die 20 comprises a plurality of bonding pads 202 on its active surface 20 a .
  • the bonding pads 202 further comprise a plurality of first ground pads 202 a and a plurality of second ground pads 202 b .
  • the plurality of first ground pads 202 a are sensitive analog ground pads
  • the plurality of second ground pads 202 b are digital ground pads.
  • the plurality of first ground pads 202 a are digital ground pads
  • the plurality of second ground pads 202 b are sensitive analog ground pads.
  • a plurality of first bonding wires 212 are provided to connect the respective first ground pads 202 a to the ground bar 130 .
  • a plurality of second bonding wires 214 are provided to connect the respective second ground pads 202 b to the plated top surface of the peripheral groove 112 .
  • a plurality of third bonding wires 216 are provided to connect the bond pads 202 c such as signal or power pads to the leads 120 .
  • a plurality of fourth bonding wires 218 are provided to connect the die pad 110 with the ground bar 130 in order to reduce the ground inductance.
  • the ground bar 130 may have a continuous ring shape. However, the present invention is not limited thereto. Discontinuities 132 may be provided in the ground bar 130 , thereby forming separated ground bar segments 130 a and 130 b . Each of the ground bar segments 130 a and 130 b are supported by respective tie bars 144 . A plurality of fifth bonding wires 220 are provided to connect the second ground pads 202 b to the ground bar segment 130 b . A plurality of sixth bonding wires 222 are provided to connect the first ground pads 202 a to the ground bar segment 130 a . Since the digital ground path is separated from the analog ground path by wire bonding to separate ground bar segments 130 a and 130 b , the sensitive analog ground signal is not interfered by the digital ground signal.
  • the separated ground bar segments may have various shapes, for example, T shape, U shape, ⁇ shape, L shape, serpentine shape or irregular shapes.
  • FIG. 3 shows some examples of the separated ground bar segments according to this invention. It is one germane feature of the present invention that the bonding wires for conveying digital ground signal are boned to one of the separated ground bar segments, while the bonding wires for conveying analog ground signal are bonded to the other. In doing so, the interference between the digital ground and the analog ground is avoided.
  • FIG. 4 is a schematic, cross-sectional view of a semiconductor package 10 a in accordance with another embodiment of this invention.
  • FIG. 5 is a partial plan view of the semiconductor package in FIG. 4 .
  • the semiconductor package 10 a comprises a semiconductor die 20 mounted onto the first surface 110 a of a die pad 110 , a plurality of leads 120 in a first horizontal plane disposed along the peripheral edges of the die pad 110 , a ground bar 320 downset from the first horizontal plane to a second horizontal plane between inner ends 120 a of the leads 120 and the die pad 110 , and a plurality of downset tie bars 144 a connecting the ground bar 320 with the die pad 110 .
  • An extended ground bar 330 that is flush with the plurality of leads 120 in the first horizontal plane is provided between the inner ends 120 a of the leads 120 and the ground bar 320 .
  • the extended ground bar 330 is supported by the downset tie bar 144 b that connects to the ground bar 320 .
  • a molding compound 30 at least partially encapsulates the die pad 110 , the inner ends 120 a of the leads 120 such that the bottom surface 110 b of the die pad 110 is exposed within the molding compound 30 .
  • the bottom surface 110 b of the die pad 110 may be partially etched along the periphery of the die pad 110 to form a step 116 .
  • a peripheral groove may be etched into the first surface 110 a of the die pad 110 to improve the interlock between the molding compound 30 and the die pad 110 .
  • the semiconductor die 20 comprises a plurality of bonding pads 202 on its active surface 20 a .
  • the bonding pads 202 further comprise a plurality of first ground pads 202 a and a plurality of second ground pads 202 b .
  • the plurality of first ground pads 202 a are digital ground pads, while the plurality of second ground pads 202 b are sensitive analog ground pads.
  • a plurality of first bonding wires 312 are provided to connect the respective first ground pads 202 a to the ground bar 320 .
  • a plurality of second bonding wires 314 are provided to connect the respective second ground pads 202 b to the extended ground bar 330 .
  • a plurality of third bonding wires 316 are provided to connect the bond pads 202 c such as signal or power pads to the leads 120 .
  • a plurality of fourth bonding wires 318 are provided to connect the die pad 110 with the die 20 .

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A semiconductor package includes a die pad; a semiconductor die mounted on the die pad; a plurality of leads in a first horizontal plane disposed along peripheral edges of the die pad; a ground bar downset from the first horizontal plane to a second horizontal plane between the leads and the die pad; a plurality of downset tie bars connecting the ground bar with the die pad; a plurality of ground wires bonding to both of the ground bar and the die pad; and a molding compound at least partially encapsulating the die pad, inner ends of the leads such that bottom surface of the die pad is exposed within the molding compound.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This is a continuation application of U.S. patent application Ser. No. 12/273,559 filed Nov. 19, 2008, which is incorporated herein by reference.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • This invention relates generally to packaging of semiconductors, and in particular, to a leadframe semiconductor package.
  • 2. Description of the Prior Art
  • Leadframe semiconductor packages are well known in the art. A conventional leadframe typically includes a plurality of metal leads temporarily held together in a planar arrangement about a central region during package manufacture by a rectangular frame. A die pad is supported in the central region by a plurality of tie bars that attach to the frame. The leads extend from a first end integral with the frame to an opposite second end adjacent to, but spaced apart from, the die pad.
  • During package manufacture, a semiconductor die is attached to the die pad. Wire-bonding pads on the die are then connected to selected ones of the inner ends of the leads by fine, conductive bonding wires to convey power, ground or signals between the die and the leads. A protective body of an epoxy resin is molded over the assembly to enclose and seal the die, the inner ends of the leads, and the wire bonds against harmful environmental elements. The rectangular frame and the outer ends of the leads are left exposed outside of the body, and after molding, the frame is cut away from the leads and discarded, and the outer ends of the leads are appropriately formed for interconnection of the package with an external printed circuit board.
  • One known type of the leadframe semiconductor packages is the so-called exposed die pad (E-pad) leadframe package that exposes the bottom surface of the die pad to the outside of the encapsulation body. The exposed die pad acts as a heat sink and can improve the heat-dissipation efficiency. Typically, the exposed die pad is electrically connected to a ground plane of the external printed circuit board.
  • It has been found that the E-pad leadframe package is subject to attacks of moisture. To avoid reliability problems due to moisture attacks and delamination along the plastic body-metal interface, the ground wires extended from the ground pads of the semiconductor die are not directly bonded onto the surface of the die pad, but instead the ground wires are bonded to a rectangular ring shaped ground bridge bar that encircles the die pad at different downset planes. Typically, the ground bridge bar is supported by tie bars that connected with the die pad.
  • However, the prior art leadframe package with such ground bridge bar configuration has a shortcoming of that the analog and digital ground wires randomly bonded together onto the ground bridge bar can result in noise or ground coupling, which is also known as water wave effects in TV systems. Another shortcoming is that the ground bridge bar is vulnerable to twist and deform, leading to poor bonding strength. It is therefore desirable to provide an improved leadframe package structure that may eliminate the aforesaid digital and analog ground coupling and the water wave effects in TV systems.
    • SUMMARY OF THE INVENTION
  • It is one objective of this invention to provide an improved semiconductor package structure with improved performance and reduced ground coupling.
  • To these ends, according to one aspect of the present invention, there is provided a semiconductor package including a die pad; a semiconductor die mounted on the die pad; a plurality of leads in a first horizontal plane disposed along peripheral edges of the die pad; a ground bar downset from the first horizontal plane to a second horizontal plane between the leads and the die pad; a plurality of downset tie bars connecting the ground bar with the die pad; a plurality of ground wires bonding to both of the ground bar and the die pad; and a molding compound at least partially encapsulating the die pad, inner ends of the leads such that bottom surface of the die pad is exposed within the molding compound.
  • In one aspect, a semiconductor package includes a die pad; a semiconductor die mounted on the die pad; a plurality of leads in a first horizontal plane disposed along peripheral edges of the die pad; a first ground bar downset from the first horizontal plane to a second horizontal plane; a second ground bar flush with the leads; a first downset tie bar connecting the first ground bar to the die pad; a second downset tie bar connecting the second ground bar with the first ground bar; a plurality of first ground wires for conveying digital ground bonding to the first ground bar; a plurality of second ground wires for conveying analog ground bonding to the second ground bar; and a molding compound at least partially encapsulating the die pad, inner ends of the leads such that bottom surface of the die pad is exposed within the molding compound.
  • These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:
  • FIG. 1 is a top view of a semiconductor package according to one embodiment of the present invention;
  • FIG. 2 is a schematic, cross-sectional view of the semiconductor package of FIG. 1;
  • FIG. 3 shows some examples of the separated ground bar segments according to this invention;
  • FIG. 4 is a schematic, cross-sectional view of a semiconductor package in accordance with another embodiment of this invention; and
  • FIG. 5 is a partial plan view of the semiconductor package in FIG. 4.
    •  DETAILED DESCRIPTION
  • The technology trend in the consumer electronics can be summarized as more functionalities in a smaller geometry with low cost. The exposed pad low-profile quad flat package (E-pad LQFP) is a low cost solution for multimedia chips, but its disadvantages are limited pin count and worse electrical characteristics.
  • As previously mentioned, one problem relates to delamination of the leadframe components from the plastic package body, and the attendant problem of penetration of the package by moisture. In particular, the various parts of a semiconductor package experience greatly different amounts of thermal expansion and contraction with temperature changes due to the relatively large differences in the coefficients of thermal expansion of their respective materials, e.g., metal, epoxy resin, and silicon. As a result, the leadframe components can become delaminated from the package body with temperature cycling of the package during manufacture or operation.
  • Where delamination occurs at a boundary of the package body, a microscopic crack is created for the penetration of the package by moisture. The moisture can corrode metallization present in its path, resulting in subsequent current leakage through the corrosive path. To avoid reliability problems due to moisture attacks and delamination, the ground wires are typically not bonded onto the surface of the die pad. Instead, the ground wires, either digital ground wires or analog ground wires, are bonded to a ground bridge bar that encircles the die pad at different downset planes. However, such configuration results in ground signal coupling noise. The present invention addresses this problem.
  • One or more implementations of the present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures are not necessarily drawn to scale.
  • FIG. 1 is a top view of a semiconductor package according to one embodiment of the present invention. FIG. 2 is a schematic, cross-sectional view of the semiconductor package of FIG. 1. As shown in FIG. 1 and FIG. 2, according to the first embodiment of this invention, a semiconductor package 10 comprises a semiconductor die 20 mounted onto the first surface 110 a of a die pad 110, a plurality of leads 120 in a first horizontal plane disposed along the peripheral edges of the die pad 110, a ground bar 130 downset from the first horizontal plane to a second horizontal plane between inner ends 120 a of the leads 120 and the die pad 110, four connecting bars 142 extending outward from four corners of the die pad 110, and a plurality of downset tie bars 144 connecting the ground bar 130 with the die pad 110. A molding compound 30 at least partially encapsulates the die pad 110, the inner ends 120 a of the leads 120 such that the bottom surface 110 b of the die pad 110 is exposed within the molding compound 30.
  • According to this embodiment, a peripheral groove 112 is etched into the first surface 110 a of the die pad 110 and is disposed around the semiconductor die 20. A plating layer 114 such as silver or noble metals may be formed within the peripheral groove 112 for wire bonding purposes. The peripheral groove 112 can increase the coupling strength. To securely lock the leadframe components to the plastic body of the package, thereby effectively reducing both the amount of delamination of the leadframe from the body and the resulting penetration of the body by moisture, the bottom surface 110 b of the die pad 110 may be partially etched along the periphery of the die pad 110 to form a step 116.
  • The semiconductor die 20 comprises a plurality of bonding pads 202 on its active surface 20 a. The bonding pads 202 further comprise a plurality of first ground pads 202 a and a plurality of second ground pads 202 b. According to this embodiment, the plurality of first ground pads 202 a are sensitive analog ground pads, while the plurality of second ground pads 202 b are digital ground pads. In another embodiment, the plurality of first ground pads 202 a are digital ground pads, while the plurality of second ground pads 202 b are sensitive analog ground pads.
  • A plurality of first bonding wires 212 are provided to connect the respective first ground pads 202 a to the ground bar 130. A plurality of second bonding wires 214 are provided to connect the respective second ground pads 202 b to the plated top surface of the peripheral groove 112. A plurality of third bonding wires 216 are provided to connect the bond pads 202 c such as signal or power pads to the leads 120. According to this embodiment, a plurality of fourth bonding wires 218 are provided to connect the die pad 110 with the ground bar 130 in order to reduce the ground inductance. By separating the digital ground path from the analog ground path, the sensitive analog ground signal is not interfered by the digital ground signal during operation and the water wave effect can be eliminated.
  • The ground bar 130 may have a continuous ring shape. However, the present invention is not limited thereto. Discontinuities 132 may be provided in the ground bar 130, thereby forming separated ground bar segments 130 a and 130 b. Each of the ground bar segments 130 a and 130 b are supported by respective tie bars 144. A plurality of fifth bonding wires 220 are provided to connect the second ground pads 202 b to the ground bar segment 130 b. A plurality of sixth bonding wires 222 are provided to connect the first ground pads 202 a to the ground bar segment 130 a. Since the digital ground path is separated from the analog ground path by wire bonding to separate ground bar segments 130 a and 130 b, the sensitive analog ground signal is not interfered by the digital ground signal.
  • The separated ground bar segments may have various shapes, for example, T shape, U shape, Π shape, L shape, serpentine shape or irregular shapes. FIG. 3 shows some examples of the separated ground bar segments according to this invention. It is one germane feature of the present invention that the bonding wires for conveying digital ground signal are boned to one of the separated ground bar segments, while the bonding wires for conveying analog ground signal are bonded to the other. In doing so, the interference between the digital ground and the analog ground is avoided.
  • FIG. 4 is a schematic, cross-sectional view of a semiconductor package 10 a in accordance with another embodiment of this invention. FIG. 5 is a partial plan view of the semiconductor package in FIG. 4. As shown in FIG. 4 and FIG. 5, likewise, the semiconductor package 10 a comprises a semiconductor die 20 mounted onto the first surface 110 a of a die pad 110, a plurality of leads 120 in a first horizontal plane disposed along the peripheral edges of the die pad 110, a ground bar 320 downset from the first horizontal plane to a second horizontal plane between inner ends 120 a of the leads 120 and the die pad 110, and a plurality of downset tie bars 144 a connecting the ground bar 320 with the die pad 110.
  • An extended ground bar 330 that is flush with the plurality of leads 120 in the first horizontal plane is provided between the inner ends 120 a of the leads 120 and the ground bar 320. The extended ground bar 330 is supported by the downset tie bar 144 b that connects to the ground bar 320. A molding compound 30 at least partially encapsulates the die pad 110, the inner ends 120 a of the leads 120 such that the bottom surface 110 b of the die pad 110 is exposed within the molding compound 30.
  • To securely lock the leadframe components to the plastic body of the package, thereby effectively reducing both the amount of delamination of the leadframe from the body and the resulting penetration of the body by moisture, the bottom surface 110 b of the die pad 110 may be partially etched along the periphery of the die pad 110 to form a step 116. In addition, a peripheral groove may be etched into the first surface 110 a of the die pad 110 to improve the interlock between the molding compound 30 and the die pad 110.
  • The semiconductor die 20 comprises a plurality of bonding pads 202 on its active surface 20 a. The bonding pads 202 further comprise a plurality of first ground pads 202 a and a plurality of second ground pads 202 b. According to this embodiment, the plurality of first ground pads 202 a are digital ground pads, while the plurality of second ground pads 202 b are sensitive analog ground pads. A plurality of first bonding wires 312 are provided to connect the respective first ground pads 202 a to the ground bar 320. A plurality of second bonding wires 314 are provided to connect the respective second ground pads 202 b to the extended ground bar 330. A plurality of third bonding wires 316 are provided to connect the bond pads 202 c such as signal or power pads to the leads 120. Optionally, a plurality of fourth bonding wires 318 are provided to connect the die pad 110 with the die 20. By separating the digital ground path from the analog ground path, the sensitive analog ground signal is not interfered by the digital ground signal during operation and the water wave effect can be eliminated.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (9)

1. A semiconductor package, comprising:
a die pad;
a semiconductor die mounted on the die pad;
a plurality of leads in a first horizontal plane disposed along peripheral edges of the die pad;
a ground bar downset from the first horizontal plane to a second horizontal plane between the leads and the die pad;
a plurality of downset tie bars connecting the ground bar with the die pad;
a set of first ground wires directly electrically connected to the semiconductor die and the ground bar;
a set of second ground wires directly electrically connected to the semiconductor die and the die pad;
a molding compound at least partially encapsulating the die pad, inner ends of the leads such that bottom surface of the die pad is exposed within the molding compound;
a plurality of signal wires provided to connect signal pads on the semiconductor die to the leads; and
a plurality of power wires provided to connect power pads on the semiconductor die to the leads.
2. The semiconductor package according to claim 1 wherein the first ground wires are analog ground and the second ground wires are digital ground.
3. The semiconductor package according to claim 2 wherein the first ground wires are directly bonded to the ground bar and the second ground wires are directly bonded to the die pad.
4. The semiconductor package according to claim 3 wherein the second ground wires are bonded to a peripheral groove partially etched into the die pad.
5. The semiconductor package according to claim 2 wherein the first and second ground wires are all bonded to the ground bar, and wherein at least one discontinuity is provided in the ground bar to separate the first ground wires from the second ground wires.
6. The semiconductor package according to claim 1 wherein the ground bar has T shape, U shape, Π shape, L shape, serpentine shape or irregular shapes.
7. The semiconductor package according to claim 1 wherein a plurality of bonding wires extend between the die pad and the ground bar.
8. A semiconductor package, comprising:
a die pad;
a semiconductor die mounted on the die pad;
a plurality of leads in a first horizontal plane disposed along peripheral edges of the die pad;
a first ground bar downset from the first horizontal plane to a second horizontal plane;
a second ground bar flush with and separated from the leads;
a first downset tie bar connecting the first ground bar to the die pad;
a second downset tie bar connecting the second ground bar with the first ground bar;
a plurality of first ground wires for conveying digital ground directly and electrically connected to the first ground bar;
a plurality of second ground wires for conveying analog ground directly and electrically connected to the second ground bar; and
a molding compound at least partially encapsulating the die pad, inner ends of the leads such that bottom surface of the die pad is exposed within the molding compound;
wherein a plurality of third bonding wires are provided to connect signal or power pads to the leads and a plurality of third bonding wires are provided to connect signal or power pads to the leads.
9. The semiconductor package according to claim 8 wherein a plurality of fourth bonding wires are provided to connect the semiconductor die with the die pad.
US13/248,045 2008-11-19 2011-09-29 Semiconductor package Abandoned US20120018862A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/248,045 US20120018862A1 (en) 2008-11-19 2011-09-29 Semiconductor package

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/273,559 US8058720B2 (en) 2008-11-19 2008-11-19 Semiconductor package
US13/248,045 US20120018862A1 (en) 2008-11-19 2011-09-29 Semiconductor package

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US12/273,559 Continuation US8058720B2 (en) 2008-11-19 2008-11-19 Semiconductor package

Publications (1)

Publication Number Publication Date
US20120018862A1 true US20120018862A1 (en) 2012-01-26

Family

ID=42171334

Family Applications (2)

Application Number Title Priority Date Filing Date
US12/273,559 Active US8058720B2 (en) 2008-11-19 2008-11-19 Semiconductor package
US13/248,045 Abandoned US20120018862A1 (en) 2008-11-19 2011-09-29 Semiconductor package

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US12/273,559 Active US8058720B2 (en) 2008-11-19 2008-11-19 Semiconductor package

Country Status (3)

Country Link
US (2) US8058720B2 (en)
CN (1) CN101740536B (en)
TW (1) TWI385775B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8999755B1 (en) * 2009-05-06 2015-04-07 Marvell International Ltd. Etched hybrid die package
CN104658986A (en) * 2013-11-15 2015-05-27 矽品精密工业股份有限公司 Semiconductor packages and lead frames

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7875963B1 (en) * 2008-11-21 2011-01-25 Amkor Technology, Inc. Semiconductor device including leadframe having power bars and increased I/O
JP5149854B2 (en) * 2009-03-31 2013-02-20 ルネサスエレクトロニクス株式会社 Semiconductor device
US8575742B1 (en) * 2009-04-06 2013-11-05 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including power bars
JP2010287733A (en) * 2009-06-11 2010-12-24 Elpida Memory Inc Semiconductor device
US8241965B2 (en) * 2009-10-01 2012-08-14 Stats Chippac Ltd. Integrated circuit packaging system with pad connection and method of manufacture thereof
JP6015963B2 (en) * 2011-12-22 2016-11-02 パナソニックＩｐマネジメント株式会社 Semiconductor package, manufacturing method thereof and mold
CN102522392B (en) * 2011-12-31 2014-11-05 天水华天科技股份有限公司 e/LQFP (low-profile quad flat package) planar packaging part with grounded ring and production method of e/LQFP planar packaging part with grounded ring
JP6296687B2 (en) * 2012-04-27 2018-03-20 キヤノン株式会社 Electronic components, electronic modules, and methods for manufacturing them.
JP2013243340A (en) * 2012-04-27 2013-12-05 Canon Inc Electronic component, mounting member, electronic apparatus, and manufacturing method of these
JP5885690B2 (en) 2012-04-27 2016-03-15 キヤノン株式会社 Electronic components and equipment
US10426035B2 (en) 2012-06-27 2019-09-24 Mediatek Inc. SGS or GSGSG pattern for signal transmitting channel, and PCB assembly, chip package using such SGS or GSGSG pattern
US9269653B2 (en) * 2012-06-27 2016-02-23 Mediatek Inc. SGS or GSGSG pattern for signal transmitting channel, and PCB assembly, chip package using such SGS or GSGSG pattern
CN103345374A (en) * 2013-07-09 2013-10-09 京东方科技集团股份有限公司 Multi-screen display device and method for eliminating multi-screen signal interference
US10804185B2 (en) 2015-12-31 2020-10-13 Texas Instruments Incorporated Integrated circuit chip with a vertical connector
JP6695156B2 (en) * 2016-02-02 2020-05-20 エイブリック株式会社 Resin-sealed semiconductor device
EP3285293B1 (en) * 2016-08-17 2019-04-10 EM Microelectronic-Marin SA Integrated circuit die having a split solder pad
JP7516980B2 (en) * 2020-08-24 2024-07-17 住友電気工業株式会社 Semiconductor Device
TWI892552B (en) * 2024-03-29 2025-08-01 瑞昱半導體股份有限公司 Packaged chip

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100298692B1 (en) * 1998-09-15 2001-10-27 마이클 디. 오브라이언 Lead frame structure for semiconductor package manufacturing
JP3062691B1 (en) * 1999-02-26 2000-07-12 株式会社三井ハイテック Semiconductor device
US7042068B2 (en) * 2000-04-27 2006-05-09 Amkor Technology, Inc. Leadframe and semiconductor package made using the leadframe
KR20020007875A (en) 2000-07-19 2002-01-29 마이클 디. 오브라이언 Leadframe for manufacturing semiconductor package
US6630373B2 (en) * 2002-02-26 2003-10-07 St Assembly Test Service Ltd. Ground plane for exposed package
US6627977B1 (en) * 2002-05-09 2003-09-30 Amkor Technology, Inc. Semiconductor package including isolated ring structure
US7064420B2 (en) * 2002-09-30 2006-06-20 St Assembly Test Services Ltd. Integrated circuit leadframe with ground plane
TWI250632B (en) * 2003-05-28 2006-03-01 Siliconware Precision Industries Co Ltd Ground-enhancing semiconductor package and lead frame
TWI245399B (en) * 2004-03-11 2005-12-11 Advanced Semiconductor Eng Leadframe with die pad
CN101211794A (en) * 2006-12-27 2008-07-02 联发科技股份有限公司 Method for packaging semiconductor element, method for manufacturing lead frame and semiconductor packaging product

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
English Machine Translation of KR 2002-0007875 (Korean version on IDS) retrieved on 11/17/11 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8999755B1 (en) * 2009-05-06 2015-04-07 Marvell International Ltd. Etched hybrid die package
CN104658986A (en) * 2013-11-15 2015-05-27 矽品精密工业股份有限公司 Semiconductor packages and lead frames

Also Published As

Publication number Publication date
TWI385775B (en) 2013-02-11
US8058720B2 (en) 2011-11-15
US20100123226A1 (en) 2010-05-20
CN101740536A (en) 2010-06-16
TW201021184A (en) 2010-06-01
CN101740536B (en) 2012-10-03

Similar Documents

Publication Publication Date Title
US8058720B2 (en) Semiconductor package
US7019389B2 (en) Lead frame and semiconductor package with the same
US8698291B2 (en) Packaged leadless semiconductor device
EP1913633B1 (en) Packaged integrated circuit with enhanced thermal dissipation
US6545347B2 (en) Enhanced leadless chip carrier
US7446397B2 (en) Leadless semiconductor package
US6853059B1 (en) Semiconductor package having improved adhesiveness and ground bonding
KR101555300B1 (en) A semiconductor power module package having an outer bonding region
JPH0621276A (en) Thermally reinforced semiconductor element and its manufacture
KR102231769B1 (en) Semiconductor package having exposed heat sink for high thermal conductivity and manufacturing method thereof
CN101803015A (en) Semiconductor chip package with bent outer leads
CN102576698A (en) Leadframe packages having enhanced ground-bond reliability
US6396129B1 (en) Leadframe with dot array of silver-plated regions on die pad for use in exposed-pad semiconductor package
US9685351B2 (en) Wire bond mold lock method and structure
US20080128741A1 (en) Leadframe and Semiconductor Package
US7102241B2 (en) Leadless semiconductor package
US7750444B2 (en) Lead-on-chip semiconductor package and leadframe for the package
US20060145312A1 (en) Dual flat non-leaded semiconductor package
US20240429137A1 (en) Dual leadframe semiconductor device and method therefor
US12125780B2 (en) Extendable inner lead for leaded package
JPH08115941A (en) Semiconductor device
US20090233403A1 (en) Dual flat non-leaded semiconductor package
KR19980044252A (en) Lead Frame Structure and Semiconductor Package Using the Same
KR20050046348A (en) Semiconductor package
KR20000072903A (en) Lead On Chip(LOC) package

Legal Events

Date Code Title Description
AS Assignment

Owner name: MEDIATEK INC., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHEN, NAN-JANG;WONG, YAU-WAI;REEL/FRAME:026986/0704

Effective date: 20081111

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION