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US20090294297A1 - Method of forming plating layer - Google Patents

Method of forming plating layer Download PDF

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Publication number
US20090294297A1
US20090294297A1 US12/243,067 US24306708A US2009294297A1 US 20090294297 A1 US20090294297 A1 US 20090294297A1 US 24306708 A US24306708 A US 24306708A US 2009294297 A1 US2009294297 A1 US 2009294297A1
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US
United States
Prior art keywords
layer
forming
plating
substrate
plating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/243,067
Inventor
Young Suk Kim
Yong Soo Oh
Byeung Gyu Chang
Won Hee Yoo
Sung Yeol Park
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Samsung Electro Mechanics Co Ltd
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Samsung Electro Mechanics Co Ltd
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Publication date
Application filed by Samsung Electro Mechanics Co Ltd filed Critical Samsung Electro Mechanics Co Ltd
Assigned to SAMSUNG ELECTRO-MECHANICS CO., LTD reassignment SAMSUNG ELECTRO-MECHANICS CO., LTD ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: OH, YOUNG SOO, PARK, SUNG YEOL, KIM, YOUNG SUK, YOO, WON HEE, CHANG, BYEUNG GYU
Publication of US20090294297A1 publication Critical patent/US20090294297A1/en
Abandoned legal-status Critical Current

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    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02Electroplating of selected surface areas
    • C25D5/022Electroplating of selected surface areas using masking means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10Electroplating with more than one layer of the same or of different metals
    • C25D5/12Electroplating with more than one layer of the same or of different metals at least one layer being of nickel or chromium
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0073Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces
    • H05K3/0076Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces characterised by the composition of the mask
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0104Properties and characteristics in general
    • H05K2201/0129Thermoplastic polymer, e.g. auto-adhesive layer; Shaping of thermoplastic polymer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1105Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating

Definitions

  • the present invention relates to a method of forming a plating layer, and more particularly, to a method of forming a plating layer which ensures a sufficient plating thickness of the plating layer and minimum chemical damage to a substrate, notably, a ceramic substrate, during a plating process.
  • a multilayer ceramic substrate is utilized as a part incorporating an active device such as a semiconductor integrated circuit (IC) chip and a passive device such as a capacitor, an inductor and a resistor, or a simple semiconductor IC package. More specifically, the multilayer ceramic substrate is widely used to implement various electronic parts such as a power amplifier (PA) module substrate, a radio frequency (RF) diode switch, a filter, a chip antenna and diverse package parts and a converged device.
  • PA power amplifier
  • RF radio frequency
  • an Ni plating layer and an Au plating layer are formed on a metal pattern printed on a surface of a ceramic sintered body by electroless plating and electroplating, respectively.
  • the Ni/Au plating layer is not sufficiently thick.
  • the Ni/Au plating layer is not uniform in thickness since current is hardly supplied to an entire area of the substrate uniformly. Accordingly, the external electrodes when bonded to a probe tip are degraded in bonding force while experiencing higher electrical resistance.
  • the ceramic substrate may be decolored or eroded, which subsequently leads to reduction in strength.
  • An aspect of the present invention provides a method of forming a plating layer in which a plating layer is formed with a sufficient thickness while a substrate, particularly a ceramic substrate is minimized in chemical damage during the plating process.
  • a method of forming a plating layer including: forming a seed layer on a substrate; forming a pattern layer on the seed layer, the pattern layer formed of a thermoplastic resin and including openings; forming a plating layer on portions of the seed layer corresponding to the openings; and removing the pattern layer.
  • the pattern layer may be formed of one material selected from a group consisting of polyethylene, polyvinylidene fluoride, liquid crystal polymer and a combination thereof.
  • the pattern layer has a thickness of 20 to 30 ⁇ m to ensure a sufficient thickness of the plating layer.
  • the removing the pattern layer may include heating the pattern layer.
  • the removing the pattern layer may include heating the pattern layer at a temperature of 200 to 300° C. for 2 to 3 hours.
  • the seed layer may include first and second layers, the first layer formed of one material selected from a group consisting of Ti, Cr, ZnO and a combination thereof, and the second layer formed on the first layer and containing Cu.
  • the first layer may have a thickness of 0.05 to 0.3 ⁇ m.
  • the second layer may have a thickness of 0.3 to 1 ⁇ m.
  • the forming a seed layer may include performing one of sputtering and E-beam evaporation.
  • the forming a plating layer may include performing electroplating, but the present invention is not specifically limited thereto.
  • the forming a seed layer on a substrate may include forming the seed layer on an entire top surface of the substrate.
  • the forming a plating layer may include forming a Cu layer, an Ni layer and an Au layer sequentially.
  • the substrate may be a ceramic substrate having an internal electrode and a conductive via therein, the internal electrode and the conductive via electrically connected to the plating layer.
  • FIGS. 1A to 1D are cross-sectional views illustrating a method of forming a plating layer according to an exemplary embodiment of the invention
  • FIG. 2 is a detailed view illustrating a seed layer shown in FIG. 1 ;
  • FIG. 3 illustrates a process which may be added to the embodiment shown in FIG. 1 according to an exemplary embodiment of the invention.
  • FIGS. 1A to 1D are cross-sectional views illustrating a method of forming a plating layer according to an exemplary embodiment of the invention.
  • a substrate 101 is provided and a seed layer 102 is formed on a top surface of the substrate 101 .
  • the substrate 101 may include a conductive via and an internal electrode formed therein.
  • the substrate 101 may adopt a ceramic substrate such as a low co-fired or high co-fired ceramic.
  • the present invention is not limited thereto, and any kind of substrate may be utilized as long as the substrate requires a plating layer as an external electrode.
  • the seed layer 102 serves as a seed for a plating layer which will be formed in a later process.
  • the seed layer 102 may be formed on an entire area of the top surface of the sintered substrate 101 not by a screen printing but by sputtering or E-beam deposition. As described above, the seed layer 102 is formed as a thin film on the entire top surface of the substrate 101 . Accordingly, as will be described later, the plating layer can be easily formed by electroplating.
  • FIG. 2 is a detailed cross-sectional view illustrating a seed layer shown in FIG. 1 .
  • the seed layer 102 is configured as a two-layer structure including first and second layers.
  • the first layer is a Ti layer 102 a and the second layer is a Cu layer 102 b .
  • the Ti layer 102 a serves to enhance adherence between the substrate 101 , e.g., made of ceramic and the plating layer.
  • the Ti layer 102 a may have a thickness ta ranging from 0.05 to 0.3 ⁇ m.
  • the first layer may be formed of Cr or ZnO in addition to Ti, or these materials may be used in combination.
  • the Cu layer 102 b functions as a substantial seed and considering this seed function, the Cu layer 102 b may have a thickness tb of about 0.3 to 1.0 ⁇ m. Meanwhile, although not illustrated, a metal pad layer made of e.g., Ag may be additionally formed between the seed layer 102 and the substrate 101 .
  • a pattern layer 103 is formed on the seed layer 102 .
  • the pattern layer 103 has openings O provided therein to serves as an area for forming the plating layer.
  • the pattern layer 103 is formed of a thermoplastic resin to be thermally removed. Accordingly, as will be described later, after forming the plating layer, the pattern layer 103 can be easily removed, with minimum damage to the substrate 101 and plating layer.
  • the pattern layer 103 may be formed of polyethylene, polyvinylidene fluoride (PVDF), and liquid crystal polymer (LCP).
  • the pattern layer 103 has a thickness t 1 determined by considering a thickness of a desired plating layer.
  • the present embodiment aims to form a thick plating layer by electroplating. Given this, the pattern layer 103 may have a thickness t 1 of 20 to 30 ⁇ m. Meanwhile, the pattern layer 103 may be formed by various methods for forming thermoplastic resin patterns, for example, by spin coating after a mask process.
  • a plating layer 104 is formed on portions of the seed layer 102 corresponding to the openings O.
  • the substrate having the seed layer 102 and the pattern layer 103 formed thereon is immersed in a plating bath containing a plating solution, and then electroplating is preformed to induce electrical chemical reaction.
  • the electroplating can be carried out since the seed layer 102 is provided as a thin film on the entire top surface of the substrate 101 .
  • the plating layer 104 can be formed on the portions of the pattern layer 103 corresponding to the openings by electroplating to have a great thickness. This allows for superior bonding between the substrate 101 and the plating layer 104 .
  • the plating layer 104 may be formed of a three-layer structure of Cu/Ni/Au even though configured differently according to a material for the seed layer 102 .
  • the pattern layer 103 is removed from the substrate 101 .
  • the pattern layer 103 is formed of a thermoplastic resin such as polyethylene, which can be easily removed by adequate heating.
  • the pattern layer 103 may be heated at 300 to 400° C. and for 2 to 3 hours to be removed.
  • the plating layer 104 may be heated while being covered by the ceramic substrate to undergo minimum damage.
  • the pattern layer 103 can be easily removed by heat, not by a chemical method. This allows the plating layer 104 and the substrate 101 to be chemically undamaged.
  • the pattern layer 103 if formed of a photosensitive material, needs to be removed using a strong acid or a strong base. This may chemically impair the plating layer 104 and the substrate 101 .
  • the pattern layer 103 is substantially free from such damage. Accordingly, adherence force between the plating layer 104 and the substrate 101 is enhanced. Also, another electrical device may be bonded to the plating layer 104 more strongly.
  • the seed layer 102 may be partially removed to have a shape identical to a shape of the plating layer 104 to obtain a desired electrode structure.
  • FIG. 3 illustrates a process which may be added to the embodiment of FIG. 1 according to an exemplary embodiment of the invention.
  • the seed layer 102 may be removed using an adequate mask by a known process in the art.
  • the inventors of the present invention conducted experiments for demonstrating superior effects of the present invention.
  • the plating layers formed by the conventional method and the method of the present invention will be compared.
  • a plating layer having a three-layer structure of Cu/Ni/Au was formed without employing a thermoplastic pattern. Meanwhile, a plating layer having a three-layer structure of Cu/Ni/Au was formed by the method of the present invention.
  • the Ni layer was formed by electroless plating and the Au layer was formed by electroplating.
  • both Ni and Au were formed by electroplating.
  • the Cu layer, Ni layer, and Au layer had an average thickness of 3.2 ⁇ m, 6.4 ⁇ m, and 0.69 ⁇ M, respectively.
  • the Cu layer, Ni layer, Au layer had an average thickness of 8.2 ⁇ m, 4.1 ⁇ m, and 2.1 ⁇ m, respectively.
  • the plating layer of the present invention can be formed with a greater thickness than the conventional plating layer and in addition is more uniform in thickness.
  • the plating layer formed according to the present invention when bonded to a probe tip, is significantly increased in bonding force. That is, a shear stress required for separating the plating layer from the probe tip bonded thereto was averaged about 36N/mm 2 in the conventional method, and was 82N/mm 2 in the present invention, which is at least twice higher than the shear stress of the present invention.
  • a plating layer can be formed with a sufficient thickness and with minimum chemical damage to a substrate, particularly, a ceramic substrate, during a plating process. Moreover, the plating layer formed by the method of forming the plating layer according to the invention can be more uniform in thickness.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Other Surface Treatments For Metallic Materials (AREA)

Abstract

There is provided a method of forming a plating layer, the method including: forming a seed layer on a substrate; forming a pattern layer on the seed layer, the pattern layer formed of a thermoplastic resin and including openings; forming a plating layer on portions of the seed layer corresponding to the openings; and removing the pattern layer. This method ensures that the plating layer is formed with a sufficient thickness and the substrate, particularly, a ceramic substrate suffers minimal chemical damage during a plating process. Moreover, the plating layer is formed with a more uniform thickness.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application claims the priority of Korean Patent Application No. 2008-0051807 filed on Jun. 2, 2008, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a method of forming a plating layer, and more particularly, to a method of forming a plating layer which ensures a sufficient plating thickness of the plating layer and minimum chemical damage to a substrate, notably, a ceramic substrate, during a plating process.
  • 2. Description of the Related Art
  • In general, a multilayer ceramic substrate is utilized as a part incorporating an active device such as a semiconductor integrated circuit (IC) chip and a passive device such as a capacitor, an inductor and a resistor, or a simple semiconductor IC package. More specifically, the multilayer ceramic substrate is widely used to implement various electronic parts such as a power amplifier (PA) module substrate, a radio frequency (RF) diode switch, a filter, a chip antenna and diverse package parts and a converged device.
  • Conventionally, to form external electrodes of this multilayer ceramic substrate, an Ni plating layer and an Au plating layer are formed on a metal pattern printed on a surface of a ceramic sintered body by electroless plating and electroplating, respectively. However, in a case where the external electrodes are formed by this method, the Ni/Au plating layer is not sufficiently thick. Besides, the Ni/Au plating layer is not uniform in thickness since current is hardly supplied to an entire area of the substrate uniformly. Accordingly, the external electrodes when bonded to a probe tip are degraded in bonding force while experiencing higher electrical resistance. Moreover, in a case where a plating solution permeates into the ceramic substrate during the plating process, the ceramic substrate may be decolored or eroded, which subsequently leads to reduction in strength.
  • These problems undermine reliability of the multilayer ceramic substrate. Thus, there has been a demand in the art for a method of ensuring the plating layer is formed with a uniform and sufficient thickness.
  • SUMMARY OF THE INVENTION
  • An aspect of the present invention provides a method of forming a plating layer in which a plating layer is formed with a sufficient thickness while a substrate, particularly a ceramic substrate is minimized in chemical damage during the plating process.
  • According to an aspect of the present invention, there is a method of forming a plating layer, the method including: forming a seed layer on a substrate; forming a pattern layer on the seed layer, the pattern layer formed of a thermoplastic resin and including openings; forming a plating layer on portions of the seed layer corresponding to the openings; and removing the pattern layer.
  • The pattern layer may be formed of one material selected from a group consisting of polyethylene, polyvinylidene fluoride, liquid crystal polymer and a combination thereof. The pattern layer has a thickness of 20 to 30 μm to ensure a sufficient thickness of the plating layer.
  • The removing the pattern layer may include heating the pattern layer. The removing the pattern layer may include heating the pattern layer at a temperature of 200 to 300° C. for 2 to 3 hours.
  • The seed layer may include first and second layers, the first layer formed of one material selected from a group consisting of Ti, Cr, ZnO and a combination thereof, and the second layer formed on the first layer and containing Cu. Here, the first layer may have a thickness of 0.05 to 0.3 μm. The second layer may have a thickness of 0.3 to 1 μm.
  • The forming a seed layer may include performing one of sputtering and E-beam evaporation.
  • The forming a plating layer may include performing electroplating, but the present invention is not specifically limited thereto.
  • The forming a seed layer on a substrate may include forming the seed layer on an entire top surface of the substrate.
  • The forming a plating layer may include forming a Cu layer, an Ni layer and an Au layer sequentially.
  • The substrate may be a ceramic substrate having an internal electrode and a conductive via therein, the internal electrode and the conductive via electrically connected to the plating layer.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above and other aspects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
  • FIGS. 1A to 1D are cross-sectional views illustrating a method of forming a plating layer according to an exemplary embodiment of the invention;
  • FIG. 2 is a detailed view illustrating a seed layer shown in FIG. 1; and
  • FIG. 3 illustrates a process which may be added to the embodiment shown in FIG. 1 according to an exemplary embodiment of the invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the shapes and dimensions may be exaggerated for clarity, and the same reference signs are used to designate the same or similar components throughout.
  • FIGS. 1A to 1D are cross-sectional views illustrating a method of forming a plating layer according to an exemplary embodiment of the invention.
  • First, as shown in FIG. 1A, a substrate 101 is provided and a seed layer 102 is formed on a top surface of the substrate 101. The substrate 101 may include a conductive via and an internal electrode formed therein. Particularly, the substrate 101 may adopt a ceramic substrate such as a low co-fired or high co-fired ceramic. However, the present invention is not limited thereto, and any kind of substrate may be utilized as long as the substrate requires a plating layer as an external electrode. The seed layer 102 serves as a seed for a plating layer which will be formed in a later process. In the present embodiment, the seed layer 102 may be formed on an entire area of the top surface of the sintered substrate 101 not by a screen printing but by sputtering or E-beam deposition. As described above, the seed layer 102 is formed as a thin film on the entire top surface of the substrate 101. Accordingly, as will be described later, the plating layer can be easily formed by electroplating.
  • FIG. 2 is a detailed cross-sectional view illustrating a seed layer shown in FIG. 1. Referring to FIG. 2, the seed layer 102 is configured as a two-layer structure including first and second layers. The first layer is a Ti layer 102 a and the second layer is a Cu layer 102 b. Here, the Ti layer 102 a serves to enhance adherence between the substrate 101, e.g., made of ceramic and the plating layer. The Ti layer 102 a may have a thickness ta ranging from 0.05 to 0.3 μm. However, alternatively, the first layer may be formed of Cr or ZnO in addition to Ti, or these materials may be used in combination. The Cu layer 102 b functions as a substantial seed and considering this seed function, the Cu layer 102 b may have a thickness tb of about 0.3 to 1.0 μm. Meanwhile, although not illustrated, a metal pad layer made of e.g., Ag may be additionally formed between the seed layer 102 and the substrate 101.
  • Afterwards, as shown in FIG. 1B, a pattern layer 103 is formed on the seed layer 102. Here, the pattern layer 103 has openings O provided therein to serves as an area for forming the plating layer. Particularly, in the present embodiment, the pattern layer 103 is formed of a thermoplastic resin to be thermally removed. Accordingly, as will be described later, after forming the plating layer, the pattern layer 103 can be easily removed, with minimum damage to the substrate 101 and plating layer. The pattern layer 103 may be formed of polyethylene, polyvinylidene fluoride (PVDF), and liquid crystal polymer (LCP).
  • The pattern layer 103 has a thickness t1 determined by considering a thickness of a desired plating layer. The present embodiment aims to form a thick plating layer by electroplating. Given this, the pattern layer 103 may have a thickness t1 of 20 to 30 μm. Meanwhile, the pattern layer 103 may be formed by various methods for forming thermoplastic resin patterns, for example, by spin coating after a mask process.
  • Thereafter, as shown in FIG. 1C, a plating layer 104 is formed on portions of the seed layer 102 corresponding to the openings O. Although not described in detail, to perform this plating process, the substrate having the seed layer 102 and the pattern layer 103 formed thereon is immersed in a plating bath containing a plating solution, and then electroplating is preformed to induce electrical chemical reaction. As described above, it is construed that the electroplating can be carried out since the seed layer 102 is provided as a thin film on the entire top surface of the substrate 101. In the present embodiment, the plating layer 104 can be formed on the portions of the pattern layer 103 corresponding to the openings by electroplating to have a great thickness. This allows for superior bonding between the substrate 101 and the plating layer 104. Here, the plating layer 104 may be formed of a three-layer structure of Cu/Ni/Au even though configured differently according to a material for the seed layer 102.
  • Next, as shown in FIG. 1D, the pattern layer 103 is removed from the substrate 101. As described above, the pattern layer 103 is formed of a thermoplastic resin such as polyethylene, which can be easily removed by adequate heating. Here, the pattern layer 103 may be heated at 300 to 400° C. and for 2 to 3 hours to be removed. Also, the plating layer 104 may be heated while being covered by the ceramic substrate to undergo minimum damage.
  • As described above, the pattern layer 103 can be easily removed by heat, not by a chemical method. This allows the plating layer 104 and the substrate 101 to be chemically undamaged. The pattern layer 103, if formed of a photosensitive material, needs to be removed using a strong acid or a strong base. This may chemically impair the plating layer 104 and the substrate 101. However, in the present embodiment, the pattern layer 103 is substantially free from such damage. Accordingly, adherence force between the plating layer 104 and the substrate 101 is enhanced. Also, another electrical device may be bonded to the plating layer 104 more strongly.
  • Meanwhile according to another exemplary embodiment of the invention, as shown in FIG. 3, the seed layer 102 may be partially removed to have a shape identical to a shape of the plating layer 104 to obtain a desired electrode structure. FIG. 3 illustrates a process which may be added to the embodiment of FIG. 1 according to an exemplary embodiment of the invention. Here, the seed layer 102 may be removed using an adequate mask by a known process in the art.
  • The inventors of the present invention conducted experiments for demonstrating superior effects of the present invention. Hereinafter, the plating layers formed by the conventional method and the method of the present invention will be compared.
  • First, by the conventional method, a plating layer having a three-layer structure of Cu/Ni/Au was formed without employing a thermoplastic pattern. Meanwhile, a plating layer having a three-layer structure of Cu/Ni/Au was formed by the method of the present invention.
  • Here, in the conventional method, the Ni layer was formed by electroless plating and the Au layer was formed by electroplating. In the present invention, both Ni and Au were formed by electroplating. As a result of comparing the thickness between the plating layers formed according to the conventional method and the method of the present invention, for the conventional plating layer, the Cu layer, Ni layer, and Au layer had an average thickness of 3.2 μm, 6.4 μm, and 0.69 μM, respectively. On the other hand, for the plating layer of the present invention, the Cu layer, Ni layer, Au layer had an average thickness of 8.2 μm, 4.1 μm, and 2.1 μm, respectively. As described above, the plating layer of the present invention can be formed with a greater thickness than the conventional plating layer and in addition is more uniform in thickness.
  • Then, adherence force of the conventional plating layer and the plating layer of the present invention was compared. The plating layer formed according to the present invention, when bonded to a probe tip, is significantly increased in bonding force. That is, a shear stress required for separating the plating layer from the probe tip bonded thereto was averaged about 36N/mm2 in the conventional method, and was 82N/mm2 in the present invention, which is at least twice higher than the shear stress of the present invention.
  • As set forth above, according to exemplary embodiments of the invention, a plating layer can be formed with a sufficient thickness and with minimum chemical damage to a substrate, particularly, a ceramic substrate, during a plating process. Moreover, the plating layer formed by the method of forming the plating layer according to the invention can be more uniform in thickness.
  • While the present invention has been shown and described in connection with the exemplary embodiments, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (13)

1. A method of forming a plating layer, the method comprising:
forming a seed layer on a substrate;
forming a pattern layer on the seed layer, the pattern layer formed of a thermoplastic resin and including openings;
forming a plating layer on portions of the seed layer corresponding to the openings; and
removing the pattern layer.
2. The method of claim 1, wherein the pattern layer is formed of one material selected from a group consisting of polyethylene, polyvinylidene fluoride, liquid crystal polymer and a combination thereof.
3. The method of claim 1, wherein the pattern layer has a thickness of 20 to 30 μm.
4. The method of claim 1, wherein the removing the pattern layer comprises heating the pattern layer.
5. The method of claim 4, wherein the removing the pattern layer comprises heating the pattern layer at a temperature of 200 to 300° C. for 2 to 3 hours.
6. The method of claim 1, wherein the seed layer comprises first and second layers, the first layer formed of one material selected from a group consisting of Ti, Cr, ZnO and a combination thereof, and the second layer formed on the first layer and containing Cu.
7. The method of claim 6, wherein the first layer has a thickness of 0.05 to 0.3 μm.
8. The method of claim 6, wherein the second layer has a thickness of 0.3 to 1 μm.
9. The method of claim 1, wherein the forming a seed layer comprises performing one of sputtering and E-beam evaporation.
10. The method of claim 1, wherein the forming a plating layer comprises performing electroplating.
11. The method of claim 10, wherein the forming a seed layer on a substrate comprises forming the seed layer on an entire top surface of the substrate.
12. The method of claim 1, wherein the forming a plating layer comprises forming a Cu layer, an Ni layer and an Au layer sequentially.
13. The method of claim 1, wherein the substrate is a ceramic substrate having an internal electrode and a conductive via therein, the internal electrode and the conductive via electrically connected to the plating layer.
US12/243,067 2008-06-02 2008-10-01 Method of forming plating layer Abandoned US20090294297A1 (en)

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CN105624749A (en) * 2016-03-28 2016-06-01 上海申和热磁电子有限公司 Method for surface metallization of ceramic substrate
CN106783554A (en) * 2016-12-13 2017-05-31 深圳顺络电子股份有限公司 The preparation method and electronic component of a kind of electronic component electrode
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