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US20080246099A1 - Low temperature poly oxide processes for high-k/metal gate flow - Google Patents

Low temperature poly oxide processes for high-k/metal gate flow Download PDF

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Publication number
US20080246099A1
US20080246099A1 US11/697,993 US69799307A US2008246099A1 US 20080246099 A1 US20080246099 A1 US 20080246099A1 US 69799307 A US69799307 A US 69799307A US 2008246099 A1 US2008246099 A1 US 2008246099A1
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integrated circuit
poly
oxidation
circuit device
oxide
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Ajith Varghese
James J. Chambers
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Texas Instruments Inc
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Publication of US20080246099A1 publication Critical patent/US20080246099A1/en
Priority to US12/400,253 priority patent/US7723173B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32105—Oxidation of silicon-containing layers
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3211—Nitridation of silicon-containing layers
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
    • H10D64/666—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum the conductor further comprising additional layers
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H10D64/668—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers the layer being a silicide, e.g. TiSi2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0184—Manufacturing their gate sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • the subject matter of this invention relates to methods of manufacturing an integrated circuit. More particularly, the subject matter of this invention relates to a method of manufacturing an integrated circuit that is protected from oxidation.
  • ICs integrated circuits
  • the thickness of the layers is increasingly being thinned, uniformity of layers is being improved, thickness of devices is improved and device dimensions (e.g., at sub micron levels) on semiconductor wafers are reduced.
  • Higher device packing densities requires a reduction of a thickness of gate oxide materials (e.g., SiO 2 ), a reduction of a width and spacing of interconnecting lines, a reduction of a spacing and diameter of contact holes, and a reduction of a surface geometry such as corners and edges of various features.
  • Reduction of the size of integrated circuit allows the integrated circuits to operate at higher frequencies.
  • a reduction of the size of integrated circuits allows more integrated circuits to be manufactured on a single wafer.
  • a typical process to create an integrated circuit requires forming several layers on a substrate.
  • MOS metal-oxide-semiconductor
  • a gate structure is created, which can be energized to establish an electric field within a semiconductor channel, by which current is enabled to flow between a source region and a drain region within the transistor.
  • the source and drain regions comprise a majority of p or n type materials that facilitate this conductance.
  • the p or n type materials are formed by adding dopants to targeted areas on either side of a channel region in a semiconductor substrate.
  • the gate structure is comprised of a gate dielectric and a contact or gate electrode.
  • the gate contact generally includes metal or doped polysilicon, and is formed over the gate dielectric which is itself formed over the channel region.
  • the gate dielectric is an insulator material, which prevents large currents from flowing from the gate electrode into the channel when a voltage is applied to the gate contact, while allowing an applied gate voltage to set up an electric field within the channel region in a controllable manner.
  • the size of the transistors and other electrical components on an integrated circuit is continually decreasing to improve device density.
  • certain properties of the materials utilized to form the transistors limit the size to which the transistors can be reduced.
  • properties of silicon dioxide which is commonly used to form the layer comprising the gate dielectric in transistors, can limit the degree to which the thickness of the gate dielectric can be reduced.
  • extremely thin silicon dioxide layers allow for significant gate leakage currents due to direct tunneling of charge carriers through the oxide. Thus, it has been found that operating parameters may change dramatically due to slight variations in gate dielectric thickness.
  • thin gate dielectric layers are known to provide poor diffusion barriers to impurities. Extremely thin silicon dioxide gate dielectric layers suffer from high boron penetration into the underlying channel region during doping of the source/drain regions.
  • Recent efforts at device scaling have focused on alternative dielectric materials that can be formed in a thicker layer than silicon dioxide layers and yet still produce the same field effect performance. These materials are often referred to as high-k materials because their dielectric constants are greater than that of silicon dioxide.
  • the relative performance of such high-k materials is often expressed as equivalent oxide thickness because the alternative material layer may be thicker, while providing the equivalent electrical effect of a much thinner layer of silicon dioxide. Accordingly, high-k dielectric materials can be utilized to form gate dielectrics, and the high-k materials facilitate a reduction in device dimensions while maintaining a consistency of desired device performance.
  • the alternative dielectric materials formed in a thicker layer make the stack susceptible to residual oxidation at the interface surfaces, particularly during poly-oxidation when the edges are exposed.
  • the susceptibility of the stack to residual oxidation eliminates the use of conventional high temperature poly oxidation process for high-k/metal gate devices.
  • FIG. 5 shows a conventional high-k/metal gate transistor and the areas susceptible to metal oxidation or oxidation at various interfaces of the high-k/metal gate stack.
  • an exemplary conventional high-k/metal gate transistor 500 is comprised of a PMOS region 510 , a NMOS region 520 , a channel 530 , a first gate stack 540 and a second gate stack 550 .
  • the first gate stack 540 is comprised of a poly-silicon layer 541 , a TaN layer 542 , a W layer 543 and a HfSiON layer 544
  • the second gate stack is comprised of a poly-silicon layer 551 , a TaN layer 552 , a WSi 2 layer 553 and a HfSiON layer 554 .
  • Areas susceptible for metal oxidation on the first gate stack 540 and the second gate stack 550 are shown respectively as susceptible area 560 and susceptible area 570 .
  • a low temp deposited oxide such as a poly-oxide.
  • the low temp deposited oxide is of a very low quality and is susceptible to pin hole issues. Pin holes make the underlying dielectric/metal gate stack susceptible to subsequent cleans and high temperature processes.
  • the present invention solves these and other problems of the prior art associated with issues of oxidation of metal or oxidation at various interfaces of high-k/metal gate stack.
  • a transistor including a stack of at least one of a high-k gate layer and a metal gate layer.
  • a poly-oxide coating is used over the stack to prevent oxidation of the at least one of the high-k layer and the metal gate layer.
  • the poly-oxide coating is formed from a poly-silicon coating over the stack.
  • an integrated circuit device including a feature that is susceptible to oxidation.
  • a poly-oxide coating is used over the feature susceptible to oxidation to protect the feature susceptible to oxidation from oxidizing.
  • the poly-oxide coating is formed from a poly-silicon coating over the stack.
  • a method of preventing oxidation within an integrated circuit device including the steps of forming the integrated circuit device, depositing a thin layer of a first material over the integrated circuit device, and converting the first material to a second material to prevent oxidation within the integrated circuit device.
  • FIG. 1 shows a transistor including layers after a first step of a process by which to obtain a high quality low temperature poly-oxide for a high-k/metal gate has been performed on the transistor, in accordance with various embodiments of the present teachings.
  • FIG. 2 shows a transistor including layers after a second step of a process by which to obtain a high quality low temperature poly-oxide for a high-k/metal gate is performed on the transistor, in accordance with various embodiments of the present teachings.
  • FIG. 3 shows an alternative transistor including layers after an alternative process by which to obtain a poly-oxide for a high-k/metal gate, in accordance with various embodiments of the present teachings.
  • FIG. 4 shows a process by which a transistor is protected from oxidation of metal or oxidation at various interfaces of a high-k/metal gate stack, in accordance with various embodiments of the present teachings.
  • FIG. 5 shows a conventional high-k/metal gate transistor and the areas susceptible to metal oxidation or oxidation at various interfaces of the high-k/metal gate stack.
  • FIG. 1 shows a transistor including layers after a first step of a process by which to obtain a high quality low-temperature poly-oxide for a high-k/metal gate has been performed on the transistor, in accordance with various embodiments of the present teachings.
  • an exemplary high-k/metal gate transistor 100 is constructed with a similar structure to that shown in the prior art of FIG. 5 .
  • a very thin layer of poly-silicon coating 110 is deposited on top of the high-k/metal gate stack after a gate etch clean is performed.
  • An exemplary thickness of the poly-silicon layer that is deposited on the high-k/metal gate stack is approximately 50 A.
  • FIG. 2 shows a transistor including layers after a second step of a process by which to obtain a high quality low temperature poly-oxide for a high-k/metal gate is performed on the transistor, in accordance with various embodiments of the present teachings.
  • the exemplary high-k/metal gate transistor 100 including the very thin layer of poly-silicon coating 110 is subjected to Ultra Violet O 3 low temperature, e.g., 25 degree C.-600 degree C., oxidation 200 .
  • the UV O 3 low temperature, e.g., 25 degree C.-600 degree C., oxidation 200 transforms the very thin layer of poly-silicon 110 into a very uniform good quality poly-oxide coating 210 all around the high-k/metal gate stack
  • the uniformity from the disclosed process produced is in the exemplary range of 15-25 A.
  • the very uniform good quality poly-oxide coating 210 produced with the UV O 3 low temperature oxidation 200 results in a protective coating for the high-k/metal gate stack.
  • the very uniform good quality poly-oxide coating 210 prevents areas susceptible to metal oxidation, such as those areas shown in Figure X in the prior art, from being oxidized.
  • the very uniform good quality poly-oxide coating 210 eliminates the oxidation of metal or oxidation at various interfaces of a high-k/metal gate stack associated with the prior art.
  • FIG. 3 shows an alternative transistor including layers after an alternative process by which to obtain a poly-oxide coating for a high-k/metal gate, in accordance with various embodiments of the present teachings.
  • an exemplary high-k/metal gate transistor 100 is constructed with a similar structure to that shown in the prior art of FIG. 5 .
  • the alternative process by which to obtain a poly-oxide coating for a high-k/metal gate of FIG. 3 begins with a same first step as disclosed in FIG. 1 .
  • plasma nitridation 300 is employed to form a very thin layer of SiON based poly-oxide coating 310 on top of the high-k/metal gate stack.
  • the very uniform good quality SiON based poly-oxide coating 310 produced with plasma nitridation e.g., decoupled plasma nitridation (DPN) or NH 3 annealing
  • the very uniform good quality SiON based poly-oxide coating 310 prevents areas susceptible to metal oxidation, such as those areas shown in FIG. 5 in the prior art, from being oxidized.
  • the very uniform good quality SiON based poly-oxide coating 310 eliminates the oxidation of metal or oxidation at various interfaces of a high-k/metal gate stack associated with the prior art.
  • FIGS. 1-3 disclose a transistor having a particular structure, the structure of the disclosed transistor is irrelevant to the present teachings. Any transistor that is susceptible to oxidation can benefit from the disclosed process of forming a poly-oxide coating to prevent oxidation.
  • FIG. 4 shows a process by which a transistor is protected from oxidation of metal or oxidation at various interfaces of a high-k/metal gate stack, in accordance with various embodiments of the present teachings.
  • the first step of the process 410 comprises formation of a transistor, as is disclosed within the prior art.
  • the second step of the process 420 includes formation of the very thin layer of poly-silicon coating on the high-k/metal gate stack.
  • the third set of the process 430 includes conversion of the very thin layer of poly-silicon coating on the high-k/metal gate stack to a poly-oxide protective coating.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

An integrated circuit device is disclosed as comprising a feature that is susceptible to oxidation. A poly-oxide coating is used over the feature susceptible to oxidation to protect the feature susceptible to oxidation from oxidizing. Various method can be used to form the poly-oxide coating include conversion of a ploy-silicon coating using UV O3 low temperature oxidation and plasma nitridation using either decoupled plasma nitridation or NH3 annealing.

Description

    FIELD OF THE INVENTION
  • The subject matter of this invention relates to methods of manufacturing an integrated circuit. More particularly, the subject matter of this invention relates to a method of manufacturing an integrated circuit that is protected from oxidation.
    • BACKGROUND OF THE INVENTION
  • Presently within the semiconductor industry, a trend exists to manufacture integrated circuits (ICs) with a greater number of layers and with higher device densities. To achieve these high densities, the thickness of the layers is increasingly being thinned, uniformity of layers is being improved, thickness of devices is improved and device dimensions (e.g., at sub micron levels) on semiconductor wafers are reduced. Higher device packing densities requires a reduction of a thickness of gate oxide materials (e.g., SiO2), a reduction of a width and spacing of interconnecting lines, a reduction of a spacing and diameter of contact holes, and a reduction of a surface geometry such as corners and edges of various features. Reduction of the size of integrated circuit allows the integrated circuits to operate at higher frequencies. Moreover, a reduction of the size of integrated circuits allows more integrated circuits to be manufactured on a single wafer.
  • At present, a typical process to create an integrated circuit requires forming several layers on a substrate. For a metal-oxide-semiconductor (MOS) transistor, for example, a gate structure is created, which can be energized to establish an electric field within a semiconductor channel, by which current is enabled to flow between a source region and a drain region within the transistor. The source and drain regions comprise a majority of p or n type materials that facilitate this conductance. The p or n type materials are formed by adding dopants to targeted areas on either side of a channel region in a semiconductor substrate. The gate structure is comprised of a gate dielectric and a contact or gate electrode. The gate contact generally includes metal or doped polysilicon, and is formed over the gate dielectric which is itself formed over the channel region. The gate dielectric is an insulator material, which prevents large currents from flowing from the gate electrode into the channel when a voltage is applied to the gate contact, while allowing an applied gate voltage to set up an electric field within the channel region in a controllable manner.
  • The size of the transistors and other electrical components on an integrated circuit is continually decreasing to improve device density. However, certain properties of the materials utilized to form the transistors limit the size to which the transistors can be reduced. By way of example, properties of silicon dioxide, which is commonly used to form the layer comprising the gate dielectric in transistors, can limit the degree to which the thickness of the gate dielectric can be reduced. For instance, extremely thin silicon dioxide layers allow for significant gate leakage currents due to direct tunneling of charge carriers through the oxide. Thus, it has been found that operating parameters may change dramatically due to slight variations in gate dielectric thickness.
  • Furthermore, thin gate dielectric layers are known to provide poor diffusion barriers to impurities. Extremely thin silicon dioxide gate dielectric layers suffer from high boron penetration into the underlying channel region during doping of the source/drain regions. Recent efforts at device scaling have focused on alternative dielectric materials that can be formed in a thicker layer than silicon dioxide layers and yet still produce the same field effect performance. These materials are often referred to as high-k materials because their dielectric constants are greater than that of silicon dioxide. The relative performance of such high-k materials is often expressed as equivalent oxide thickness because the alternative material layer may be thicker, while providing the equivalent electrical effect of a much thinner layer of silicon dioxide. Accordingly, high-k dielectric materials can be utilized to form gate dielectrics, and the high-k materials facilitate a reduction in device dimensions while maintaining a consistency of desired device performance.
  • The alternative dielectric materials formed in a thicker layer make the stack susceptible to residual oxidation at the interface surfaces, particularly during poly-oxidation when the edges are exposed. The susceptibility of the stack to residual oxidation eliminates the use of conventional high temperature poly oxidation process for high-k/metal gate devices.
  • FIG. 5 shows a conventional high-k/metal gate transistor and the areas susceptible to metal oxidation or oxidation at various interfaces of the high-k/metal gate stack.
  • In particular, an exemplary conventional high-k/metal gate transistor 500 is comprised of a PMOS region 510, a NMOS region 520, a channel 530, a first gate stack 540 and a second gate stack 550. The first gate stack 540 is comprised of a poly-silicon layer 541, a TaN layer 542, a W layer 543 and a HfSiON layer 544, The second gate stack is comprised of a poly-silicon layer 551, a TaN layer 552, a WSi2 layer 553 and a HfSiON layer 554.
  • Areas susceptible for metal oxidation on the first gate stack 540 and the second gate stack 550 are shown respectively as susceptible area 560 and susceptible area 570.
  • A solution that has been proposed to remedy the oxidation of metal or oxidation at various interfaces of the high-k/metal gate stack using a low temp deposited oxide, such as a poly-oxide. However, the low temp deposited oxide is of a very low quality and is susceptible to pin hole issues. Pin holes make the underlying dielectric/metal gate stack susceptible to subsequent cleans and high temperature processes.
  • Accordingly, the present invention solves these and other problems of the prior art associated with issues of oxidation of metal or oxidation at various interfaces of high-k/metal gate stack.
    • SUMMARY OF THE INVENTION
  • In accordance with the invention, a transistor is disclosed including a stack of at least one of a high-k gate layer and a metal gate layer. A poly-oxide coating is used over the stack to prevent oxidation of the at least one of the high-k layer and the metal gate layer. The poly-oxide coating is formed from a poly-silicon coating over the stack.
  • In accordance with the invention, an integrated circuit device is disclosed including a feature that is susceptible to oxidation. A poly-oxide coating is used over the feature susceptible to oxidation to protect the feature susceptible to oxidation from oxidizing. The poly-oxide coating is formed from a poly-silicon coating over the stack.
  • In accordance with the invention, a method of preventing oxidation within an integrated circuit device is disclosed as including the steps of forming the integrated circuit device, depositing a thin layer of a first material over the integrated circuit device, and converting the first material to a second material to prevent oxidation within the integrated circuit device.
  • Additional advantages of the embodiments will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The advantages will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
  • It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
  • The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 shows a transistor including layers after a first step of a process by which to obtain a high quality low temperature poly-oxide for a high-k/metal gate has been performed on the transistor, in accordance with various embodiments of the present teachings.
  • FIG. 2 shows a transistor including layers after a second step of a process by which to obtain a high quality low temperature poly-oxide for a high-k/metal gate is performed on the transistor, in accordance with various embodiments of the present teachings.
  • FIG. 3 shows an alternative transistor including layers after an alternative process by which to obtain a poly-oxide for a high-k/metal gate, in accordance with various embodiments of the present teachings.
  • FIG. 4 shows a process by which a transistor is protected from oxidation of metal or oxidation at various interfaces of a high-k/metal gate stack, in accordance with various embodiments of the present teachings.
  • FIG. 5 shows a conventional high-k/metal gate transistor and the areas susceptible to metal oxidation or oxidation at various interfaces of the high-k/metal gate stack.
    •  DESCRIPTION OF THE EMBODIMENTS
  • Reference will now be made in detail to the present embodiments, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
  • Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Moreover, all ranges disclosed herein are to be understood to encompass any and all sub-ranges subsumed therein. For example, a range of “less than 10” can include any and all sub-ranges between (and including) the minimum value of zero and the maximum value of 10, that is, any and all sub-ranges having a minimum value of equal to or greater than zero and a maximum value of equal to or less than 10, e.g., 1 to 5.
  • FIG. 1 shows a transistor including layers after a first step of a process by which to obtain a high quality low-temperature poly-oxide for a high-k/metal gate has been performed on the transistor, in accordance with various embodiments of the present teachings.
  • In particular, an exemplary high-k/metal gate transistor 100 is constructed with a similar structure to that shown in the prior art of FIG. 5. However, to prevent oxidation of metal or oxidation at various interfaces of a high-k/metal gate stack a very thin layer of poly-silicon coating 110 is deposited on top of the high-k/metal gate stack after a gate etch clean is performed. An exemplary thickness of the poly-silicon layer that is deposited on the high-k/metal gate stack is approximately 50 A.
  • FIG. 2 shows a transistor including layers after a second step of a process by which to obtain a high quality low temperature poly-oxide for a high-k/metal gate is performed on the transistor, in accordance with various embodiments of the present teachings.
  • In particular, the exemplary high-k/metal gate transistor 100 including the very thin layer of poly-silicon coating 110, shown in FIG. 1, is subjected to Ultra Violet O3 low temperature, e.g., 25 degree C.-600 degree C., oxidation 200. The UV O3 low temperature, e.g., 25 degree C.-600 degree C., oxidation 200 transforms the very thin layer of poly-silicon 110 into a very uniform good quality poly-oxide coating 210 all around the high-k/metal gate stack The uniformity from the disclosed process produced is in the exemplary range of 15-25 A.
  • Thus, the very uniform good quality poly-oxide coating 210 produced with the UV O3 low temperature oxidation 200 results in a protective coating for the high-k/metal gate stack. The very uniform good quality poly-oxide coating 210 prevents areas susceptible to metal oxidation, such as those areas shown in Figure X in the prior art, from being oxidized. The very uniform good quality poly-oxide coating 210 eliminates the oxidation of metal or oxidation at various interfaces of a high-k/metal gate stack associated with the prior art.
  • FIG. 3 shows an alternative transistor including layers after an alternative process by which to obtain a poly-oxide coating for a high-k/metal gate, in accordance with various embodiments of the present teachings.
  • In particular, an exemplary high-k/metal gate transistor 100 is constructed with a similar structure to that shown in the prior art of FIG. 5. The alternative process by which to obtain a poly-oxide coating for a high-k/metal gate of FIG. 3 begins with a same first step as disclosed in FIG. 1. However, instead of subjecting the very thin layer of poly-silicon coating to UV oxidation, e.g., UV O3 low temperature oxidation, as disclosed in FIG. 2, plasma nitridation 300 is employed to form a very thin layer of SiON based poly-oxide coating 310 on top of the high-k/metal gate stack.
  • Thus, the very uniform good quality SiON based poly-oxide coating 310 produced with plasma nitridation, e.g., decoupled plasma nitridation (DPN) or NH3 annealing, results in a protective coating for the high-k/metal gate stack similar to the protective coating produced by process described for FIGS. 1 and 2. The very uniform good quality SiON based poly-oxide coating 310 prevents areas susceptible to metal oxidation, such as those areas shown in FIG. 5 in the prior art, from being oxidized. The very uniform good quality SiON based poly-oxide coating 310 eliminates the oxidation of metal or oxidation at various interfaces of a high-k/metal gate stack associated with the prior art.
  • Although FIGS. 1-3 disclose a transistor having a particular structure, the structure of the disclosed transistor is irrelevant to the present teachings. Any transistor that is susceptible to oxidation can benefit from the disclosed process of forming a poly-oxide coating to prevent oxidation.
  • FIG. 4 shows a process by which a transistor is protected from oxidation of metal or oxidation at various interfaces of a high-k/metal gate stack, in accordance with various embodiments of the present teachings.
  • The first step of the process 410 comprises formation of a transistor, as is disclosed within the prior art.
  • The second step of the process 420 includes formation of the very thin layer of poly-silicon coating on the high-k/metal gate stack.
  • The third set of the process 430 includes conversion of the very thin layer of poly-silicon coating on the high-k/metal gate stack to a poly-oxide protective coating.
  • While the teachings has been illustrated with respect to preventing oxidation within a gate stack of a transistor, the principles disclosed herein can be applied to any integrated circuit that is susceptible to oxidation. Moreover, while particular processes are disclosed herein to produce a poly-oxide coating over an integrated circuit device, the principles disclosed herein apply to any process that converts a first coating into a second protective coating over an integrated circuit device.
  • While the invention has been illustrated with respect to one or more implementations, alterations and/or modifications can be made to the illustrated examples without departing from the spirit and scope of the appended claims. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular function. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term “comprising.”
  • Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.

Claims (27)

1. A transistor, comprising:
a stack comprising at least one of a high-k gate layer and a metal gate layer; and
a coating comprising one of poly-oxide and a silicon oxynitride (SiON) based poly-oxide over the stack to prevent oxidation of the at least one of the high-k layer and the metal gate layer, wherein the coating has a thickness uniformity in the range of 15-25 angstroms (A).
2. The transistor of claim 1, wherein:
the transistor is a metal-oxide-semiconductor transistor.
3. (canceled)
4. (canceled)
5. (canceled)
6. (canceled)
7. The transistor of claim 1, wherein:
the coating is a poly-oxide.
8. An integrated circuit device, comprising:
a feature susceptible to oxidation; and
a coating over the feature susceptible to oxidation to protect the feature susceptible to oxidation from oxidizing, the coating comprising one of poly-oxide and a silicon oxynitride (SiON) based poly-oxide, and further comprising poly-silicon, wherein the coating coats the feature.
9. The integrated circuit device according to claim 8, wherein:
the integrated circuit device is a transistor.
10. The integrated circuit device according to claim 8, wherein:
the transistor is comprised of a high-k gate stack.
11. The integrated circuit device according to claim 8, wherein:
The integrated circuit is a metal-oxide-semiconductor transistor.
12. (canceled)
13. (canceled)
14. (canceled)
15. (canceled)
16. The integrated circuit device according to claim 8, wherein:
the coating comprises is a SiON based poly-oxide and poly-silicon.
17. A method of preventing oxidation within an integrated circuit device, comprising:
forming the integrated circuit device;
depositing a thin layer of a first material over the integrated circuit device; and
converting the first material to a second material to prevent oxidation within the integrated circuit device.
18. The method of preventing oxidation within an integrated circuit device according to claim 17, wherein:
the step of converting is performed using UV oxidation.
19. The method of preventing oxidation within an integrated circuit device according to claim 17, wherein:
the method of preventing oxidation is performed on a transistor.
20. The method of preventing oxidation within an integrated circuit device according to claim 19, wherein:
the transistor is comprised of a high-k gate stack.
21. The method of preventing oxidation within an integrated circuit device according to claim 17, wherein:
the first material is poly-silicon.
22. The method of preventing oxidation within an integrated circuit device according to claim 17, wherein:
the second material is poly-oxide.
23. The method of preventing oxidation within an integrated circuit device according to claim 22, wherein:
the poly-oxide coating is formed through ultra violet O3 oxidation.
24. The method of preventing oxidation within an integrated circuit device according to claim 22, wherein:
the poly-oxide coating is formed using decoupled plasma nitridation.
25. The method of preventing oxidation within an integrated circuit device according to claim 22, wherein:
the poly-oxide coating is formed using NH3 annealing.
26. The integrated circuit device according to claim 8, wherein:
the coating comprises poly-oxide and poly-silicon.
27. The integrated circuit device according to claim 8, wherein the coating is a partially converted coating.
US11/697,993 2007-04-09 2007-04-09 Low temperature poly oxide processes for high-k/metal gate flow Abandoned US20080246099A1 (en)

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