US20080237682A1

US20080237682A1 - Semiconductor memory with conductive carbon

Info

Publication number: US20080237682A1
Application number: US12/076,928
Authority: US
Inventors: Kuo-Ching Chiang
Original assignee: Individual
Current assignee: Individual
Priority date: 2007-03-26
Filing date: 2008-03-25
Publication date: 2008-10-02
Also published as: TW200840050A; TWI423441B; US20100328566A1; US8519455B2; US20120199892A1; US8362490B2

Abstract

A non-volatile memory capable of storing binary information on a semiconductor substrate comprising: a dual gate structure formed over the semiconductor substrate, wherein the dual gate structure including a gate dielectric layer formed over the semiconductor substrate, and first and second gates formed over the gate dielectric layer, an isolation layer formed between the first and second gates; a conductive carbon material with nano-scale formed under the gate dielectric layer; and a doped regions formed adjacent to the conductive carbon material.

Description

The present invention relates to a semiconductor device, and more specifically, to novel device structure with conductive carbon.

BACKGROUND OF THE INVENTION

The EEPROM is widely used in the field of semiconductor industry and has been advanced to the field of Ultra Large Scale Integrated (ULSI) technologies. The fabrication of the nonvolatile memories also follows the trend of the reduction of the size of a device and the higher speed of operation. The nonvolatile memories include various types of devices. Different types of devices have been developed for specific applications requirements in each of these segments. Flash memory is one of the segments of nonvolatile memory devices. The device includes a floating gate to storage charges and an element for electrically placing charge in and removing the charges from the floating gate. Typically, the high-density nonvolatile memories can be applied as the mass storage of portable handy terminals, solid-state camera and PC cards. It is because that the nonvolatile memories exhibit many advantages, such as fast access time, low power dissipation, and robustness. The data program method of a non-volatile memory device includes a method using Fowler-Nordheim (FN) tunneling or a method using hot electron injection. In FN tunneling, a high voltage is applied to a control gate to induce a high electric field in a tunnel oxide layer, and electrons of a semiconductor substrate pass the tunnel oxide layer and are injected into a floating gate. During the mode of erasing, the bias may apply on the source to discharge the electron from the floating gate to the source of a memory device.
The formation of nonvolatile memories toward the trends of low supply power and fast access, because these requirements are necessary for the application of the mobile computing system. Flash memory needs the charges to be hold in the floating gate for a long period of time. Therefore, the dielectric that is used for insulating the floating gate needs to be high quality in insulation and good durability in writing.
As known in the art, the tunneling effect is a basic technology in charging or discharging. In order to attain high tunneling efficiency, the thickness of the dielectric between the floating gate and substrate have to be scaled down due to the supply voltage is reduced. The memory cell consists of a source region, a drain region, a floating gate (FG), a control gate (CG) and insulation films. A plurality of sectors are arranged in the two-dimensional manner on a semiconductor substrate of the flash memory. When writing a new data or rewriting a data stored in the flash memory, the stored data in memory cells are erased on the sector basis immediately before the writing. The device is called flash due to the data is erased sector by sector.
However, when the device is scaled down into nanometer range, the carriers characteristics is unlikely to be controlled due to the optical and quantum effects are significantly than ever.

SUMMARY OF THE INVENTION

The object of the present invention is to disclose a flash device with multi-bits cell capable of storing multi binary information bits. The further object of the present invention is to provide the structure with conductive carbon to improve the operation speed and scaled down the device.
A non-volatile memory capable of storing binary information on a semiconductor substrate comprising: a dual gate structure formed over the semiconductor substrate, wherein the dual gate structure including a gate dielectric layer formed over the semiconductor substrate, and first and second gates formed over the gate dielectric layer, an isolation layer formed between the first and second gates; a conductive carbon material with nano-scale formed under the gate dielectric layer; and a doped regions formed adjacent to the conductive carbon material.
The dual gate structure is a stacked configuration or a split gate configuration. Field oxide structure is formed between the dual gate structure. The gate dielectric layer is high dielectric constant material. The gate dielectric layer includes (SiO₂), (HfO₂), (ZrO₂), (TiO₂), (HfTiO), (HfAIO), (La₂O₃) or (LaAIO). The conductive carbon includes nano carbon tube. The memory further comprises suicide material formed over the doped regions. The silicide material includes TiSi₂, CoSi₂or NiSi.
A non-volatile memory capable of storing binary information on a semiconductor substrate comprising: a dual gate structure formed over the semiconductor substrate, wherein the dual gate structure including a gate dielectric layer formed over the semiconductor substrate, and first and second gates formed over the gate dielectric layer, an isolation L-shape structure formed between the first and second gates, wherein a vertical portion of the L-shape structure attached on sidewall of the first gate, and a lateral portion where tunneling will be occurred is formed over the substrate; spacers formed on the L-shape structure to act as a second gate; a conductive carbon material with nano-scale formed under the gate dielectric layer; and a doped regions formed adjacent to the conductive carbon material.
The present invention also discloses a memory comprising: pluralities of bit lines formed over a semiconductor substrate; pluralities of word lines formed over the semiconductor substrate and perpendicular to the pluralities of bit lines forming with intercrossing areas and non-intercrossing areas; at least one conductive carbon located at one of the non-intercrossing areas to define digital status. The memory further comprises gate dielectric layer under the pluralities of word lines. The gate dielectric layer includes (SiO₂), (HfO₂), (ZrO₂), (TiO₂), (HfTiO), (HfAIO), (La₂O₃) or (LaAIO). The conductive carbon includes nano carbon tube.
The spacers represent a first binary status by injecting and storing electrical charge in the spacers or to represent a second binary status by not injecting electrical charge into the spacer. A first and a second fringing field induced channels are under the first and the second spacers, wherein the first and the second fringing field induced channels are located between the main gate-induced channel. The first and the second doped regions sit adjacent to the first and the second fringing field induced channels, respectively. The fringing field induced channels are referred to the hot carrier injection channel under the spacers.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a cross sectional view of a semiconductor wafer illustrating the memory according to the present invention.

FIG. 2 is a cross sectional view of a semiconductor wafer illustrating the memory according to the present invention.

FIG. 3 is a cross sectional view of a semiconductor wafer illustrating the memory according to the present invention.

FIG. 4 is a cross sectional view of a semiconductor wafer illustrating the memory according to the present invention.

FIG. 5 is a top view of a semiconductor wafer illustrating the memory according to the present invention.

FIG. 6 is a cross sectional view of a semiconductor wafer illustrating the memory according to the present invention.

FIG. 7 is a cross sectional view of a semiconductor wafer illustrating the semiconductor device according to the present invention.

FIG. 8 is a cross sectional view of a semiconductor wafer illustrating the display module according to the present invention.

FIG. 9 is a cross sectional view of a semiconductor wafer illustrating the memory according to the present invention.

FIG. 10 is a cross sectional view of a semiconductor wafer illustrating the memory according to the present invention.

FIG. 11 is a cross sectional view of a semiconductor wafer illustrating the memory according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention proposes a novel method to fabricate a memory. In the method, the operation speed for storing data can be increased by the cell structure. The detail description will be seen as follows. A semiconductor substrate is provided for the present invention. In a preferred embodiment, as shown in the FIG. 1, a single crystal silicon substrate 20 crystallographic orientation is provided. The substrate 20 includes a pattern of active areas comprising separated doped region such as the source/drain regions. A thin dielectric layer 22 is formed on the substrate 20 to act as gate dielectric layer. Typically, the dielectric layer 22 can be grown in oxygen ambient at a temperature of about 700 to 1100 degrees centigrade. Other method, such as chemical vapor deposition, can also form the oxide. Subsequently, a conductive layer 24 is formed on the oxide 22 to act the floating gate. The conductive layer 24 may be formed of doped polysilicon, in-situ doped polysilicon. For an embodiment, the doped polysilicon layer 20 is doped by phosphorus using a PH₃source. An isolation layer 26 is conformally formed on the substrate 20 and the gate structure. The material for forming the isolation layer 26 can be nitride, oxide (SiO₂) or (HfO₂). (ZrO₂)), (TiO₂), (HfTiO), (HfAIO), (La₂O₃), (LaAIO). One suitable method for the oxide layer includes thermal oxidation and deposition by CVD. For example, Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhance Chemical Vapor Deposition (PECVD), High Density Plasma Chemical Vapor Deposition (HDPCVD). The control gate 28 is formed on the isolation layer. A photo-resist pattern is formed on the stacked layers, followed by etching the layers by using the photo-resist pattern as etching mask, thereby forming the gate structure on the silicon substrate 20.
Next, the stacked gate is used as mask to perform the ion implantation for forming the source/drain 30 adjacent to the gate, as shown in FIG. 1. FIG. 2 is similar structure to the last embodiment. The structure in FIG. 2 is called split-gate structure to distinguish the stacked gate. The control gate shifts from the floating gate with a distance and overlaps a part of the floating gate. It should be noted that the spacers may be formed on the sidewall of the gate structure and the dosage type and profile may be changed, such as the structure may have the LDD, halo-implant, or pocket implantation. Another embodiment is shown. Most of the structure is similar to FIG. 1. An oxidation is performed to the floating gate to oxide the upper surface of the floating gate to form thick oxide 29, thereby forming peak at the corner to increase the erasing speed.
At least one conductive carbon 32, for instance nano-cabon tube (CNT) 32 is located under the gate dielectric 22 of the dual-gates structure. Namely, the conductive carbon 32 connects the S/D 30. The CNT may be formed with at least one to fifty layers structure. The diameters of the CNT maybe 1-2 nanometers and the length is 10-100 nano-meters or shorter. The S/D 30 can be formed by deposition, sputter instead of implantation in order to form the CNT. Alternatively, the CNT 22 maybe keeps a distance with the oxide 22. The embodiment may be includes spacers such as FIG. 10.
The formation of CNT is to heat the organic compound having carbon to generate the carbon atoms. One example is to input the reaction gas such as CH₄to the reaction chamber, and the carbon atoms will be separated from the gas when the reaction gas contacts the high temperature substrate. The carbon will be growth. Another method is to drive the C—H compound with CH₄through the nanometers substrate. The conductive carbon has the characteristics of semiconductor property to improve the performance of the device and scaled down the size. During the operation, the carrier of the memory will flow through the tube. The method of forming the CNT may refer to the articles . . . .
FIG. 3 is another embodiment that is multi-bits memory, a control gate 28 controls the carrier trapping structures 25. The carrier trapping structures are used to define the digital zero and one. The carrier trapping structure 25 is isolated from the sidewall of the control gate by the isolation layer 26. A dielectric layer 28 is conformally formed over the isolation layer 26, followed by isotropically etching the layer, thereby forming the spaces 28 to create the carrier trapping structure 25. The anisotropic etching includes RIE, plasma etching. Next, the S/D is formed 30. Similarly, the CNT 32 is formed prior art to form the control gate and the CNT connects the S/D 30. The source and drain is formed by performing an ion implantation to dope ions into the substrate 201 using the gate structure 203 a and sidewall spacers 206 a as a mask. Silicide process may be used on the S/D 30 in each embodiment of the present invention. The material for the silicide maybe TiSi₇, CoSi₂NiSi. A typical silicide process is introduced on the exposed surface of the silicon substrate on the source and drain regions to reduce the resistance. The gate structure 203 a is used as the control gate and the nitride spacers 25 acting as carrier trapping structure.
A sectional view of a two-bit nonvolatile memory cell in accordance with the present invention is shown in FIG. 3. The memory cell includes a substrate 201 having two buried PN junctions, one is the left junction and the other is the right junction. CNT Channels are located between the two junctions during operation. Above the main channel is oxide. On top of the oxide layer is a control gate. L-shape structure 25 is formed on the sidewall of the gate structure. The vertical portion of the L-shape structure 25 is attached on the side wall of the gate, and the lateral portion where tunneling will be occurred is formed on the substrate. Spacer 26 is used for charge trapping and is preferably comprised of silicon nitride. The hot electrons are trapped as they are injected into the Spacer 26.
The memory cell is capable of storing two bits of data, a right bit and a left bit. The two bit memory cell is a symmetrical device. The left junction serves as the source terminal and the right junction serves as the drain terminal for the right bit programming. Similarly, for the left bit programming, the right junction serves as the source terminal and the left junction serves as the drain terminal. The operating mode of the present invention for the right bit is to offer a bias Vgp is applied on the suicide over the gate structure for writing, the source node has 1 nA-1 mA current Isp. Channel hot carrier current is generated in the substrate 20 under the spacer 25 between the gate structure and the drain. The channel hot carrier current will injects into the spacer 25 via the lateral portion of the L-shape structure adjacent to the drain side due to the source, drain keep a distance from the channel under the gate. Electrons are trapped in the portion of nitride spacer near but above and self-aligned with the drain region because the strongest electric field forms there. The carriers are therefore stored in the nitride spacer 25 that functions as the floating gate of the nonvolatile memory. The nitride spacer 25 on the drain side is defined as “digital one”, while the spacer without carrier therein on the drain side is referred to “digital zero”. Hence, a set of memory unit “XY” is written as “X1” or “X0”. It should be understood that the source and drain terminals for the second bit are reversed compared to the source and drain terminals for the first bit. Therefore, the data status can be programmed or defined as “00”, “01”, “10” or “11” by applying the drain-write voltage Vdp and source current Isp depending on the right bit cell or left bit cell. If the two-bits are desired to be programmed as “11”, the drain-write voltage Vdp and source current Isp are introduced on the left bit and right bit, respectively. The cell is operated based upon “forward program and reverse read” scheme. The read current in the channel is reverse compared to the one of programming. The cell shows totally different channel sections, source/drain and SiN spacer arrangement. One of the key features is that the source/drain regions keep a distance to the channel under the gate. Under such arrangement, the present invention is capable of storing 4-bits information rather than two bits. Similarly, the digital data can be erased. In FIG. 11, the carrier trapping structure 27 is under the control gate 28, and it is consisted by ONO or ON.
FIG. 4 illustrates CNT 32 located between the S/D of a memory. The drain 30 of the memory connects to a structure with conductive/isolation/conductive to store carriers. For example, the memory has a trench formed within the substrate. The conductive/isolation/conductive structure is formed within the trench from outer to inner portion. A first conductive layer 34 is connected to the drain 30. A CNT 32 is located between the drain and source to improve the operation speed. The isolation could be oxide, NO, ONO.
FIG. 5 is the ROM of the present invention. The ROM includes bit lines 52 arranged on the substrate 50, the bit lins 52 are typically formed by ion implantation, for instance, buried bit lines. Word lines (gates) 54 are formed over the substrate and vertically cross the bit lines 52 to construct a checkerboard configuration. The word lines 54 are perpendicular to the bit lines 52. At least one conductive carbon (such as CNT) is located a portions of the non-intercrossing area of the bit lines 52 and word lines 54 to act as the semiconductor area. The cross sectional view is shown in FIG. 6. It includes two kinds of devices on the substrate 50. Oxide layer 58 is under the gate 54 and a liner layer 60 may be formed along the gate structure. Spacers 62 is formed by the well-known manner on the gate 54. Conductive carbon such as CNT 32 is formed in one kind of the devices. Another one has no the CNT. Current will be generated along the CNT between the S/D. On the contrary, there is no current in another device. Therefore, the digital status can be determined by the configuration. The present invention provides a nano-scale ROM.
FIG. 7 illustrates an oxide 72, gate 74 are formed over the substrate. The gate structure includes spacer 76 on the side walls and doped regions 78 are formed in the substrate adjacent to the gate. The substrate includes an isolation region 71 that is formed by STI or FOX. A photo-diode implantation region 80 is formed in the substrate and connected to the doped regions 78 to receive photo. Conductive carbon, such as CNT 32 is formed under the gate and between the source and drain of the doped regions 78 to act the channel. The dosage of the ion implantation region of the photo-diode 80 is about 1E12-1E14/cm², the energy of the implantation is about 50-180 keV. The surface of the doped region 80 can be formed with dosage about 1E15-1E16/cm², the energy of the implantation is about 5-40 keV to prevent dark current. The above dosage, energy and doping type can be modified. Pluralities of isolation layers 82, 84, 86 are laminated over the conductive pattern 88, 90. A lens 92 is formed over the isolation layer to guide the incident line into the photo-diode region 80. The present invention may speed up the operation speed and prevent dark current.
Another embodiment is illustrated in FIG. 8, which includes a unit having a first (rear) polarizer 100, a first transparent (such as glass) substrate 102 and a first transparent electrode 104. A TFT is formed over the first transparent electrode 104. LC (liquid crystals) 108 is formed over the TFT 104. A second (front) transparent electrode 110 is formed over the LC 108 and a second (front) transparent substrate 112 and color filter 114 are subsequently formed over the LC 108. A protection glass 116 and second (front) polarizer 118 are formed over the color filter 114. The TFT 106 is formed over the substrate 10 and the gate 12 of the TFT is patterned and isolation layer 14 is formed over the gate 12. CNT 16 is configured over the isolation 14 and aligned to the gate 12. S/D 18 substantially covers the terminals of the CNT 16 and coupled to the S/D. Alternatively, the first and/or second transparent electrodes are formed by conductive carbon (such as CNT) or conductive polymer.
As will be understood by persons skilled in the art, the foregoing preferred embodiment of the present invention is illustrative of the present invention rather than limiting the present invention. Having described the invention in connection with a preferred embodiment, modification will now suggest itself to those skilled in the art. Thus, the invention is not to be limited to this embodiment, but rather the invention is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structures. While the preferred embodiment of the invention has been illustrated and described, it will be appreciated that various changes can be made therein without departing from the spirit and scope of the invention.

Claims

1. A non-volatile memory capable of storing binary information on a semiconductor substrate comprising:

a dual gate structure formed over said semiconductor substrate, wherein said dual gate structure including a gate dielectric layer formed over said semiconductor substrate, and first and second gates formed over said gate dielectric layer, an isolation layer formed between said first and second gates;

a conductive carbon material with nano-scale formed under said gate dielectric layer; and

a doped regions formed adjacent to said conductive carbon material.

2. The memory of claim 1, wherein said dual gate structure is a stacked configuration.

3. The memory of claim 1, wherein said dual gate structure is a split gate configuration.

4. The memory of claim 3, wherein a field oxide structure formed between said dual gate structure.

5. The memory of claim 1, wherein said gate dielectric layer is high dielectric constant material.

6. The memory of claim 5, wherein said gate dielectric layer includes (SiO₂), (HfO₂), (ZrO₂), (TiO₂), (HfTiO), (HfAIO), (La₂O₃) or (LaAIO).

7. The memory of claim 1, wherein said conductive carbon includes nano carbon tube.

8. The memory of claim 1, further comprising silicide material formed over said doped regions.

9. The memory of claim 8, wherein said silicide material includes TiSi₂, CoSi₂or NiSi.

10. A non-volatile memory capable of storing binary information on a semiconductor substrate comprising:

a dual gate structure formed over said semiconductor substrate, wherein said dual gate structure including a gate dielectric layer formed over said semiconductor substrate, and first and second gates formed over said gate dielectric layer, an isolation L-shape structure formed between said first and second gates, wherein a vertical portion of said L-shape structure attached on sidewall of said first gate, and a lateral portion where tunneling will be occurred is formed over said substrate; spacers formed on said L-shape structure to act as a second gate;

a doped regions formed adjacent to said conductive carbon material.

11. The memory of claim 10, wherein said gate dielectric layer is high dielectric constant material.

12. The memory of claim 11, wherein said gate dielectric layer includes (SiO₂), (HfO₂), (ZrO₂), (TiO₂), (HfTiO), (HfAIO) ‘ (La₂O₃) or (LaAIO).

13. The memory of claim 11, wherein said conductive carbon includes nano carbon tube.

14. A memory comprising:

pluralities of bit lines formed over a semiconductor substrate;

pluralities of word lines formed over said semiconductor substrate and perpendicular to said pluralities of bit lines forming with intercrossing areas and non-intercrossing areas;

at least one conductive carbon located at one of said non-intercrossing areas to define digital status.

15. The memory of claim 14, wherein further comprising gate dielectric layer under said pluralities of word lines.

16. The memory of claim 15, wherein said gate dielectric layer includes (SiO₂), (HfO₂), (ZrO₂), (TiO₂), (HfTiO), (HfAIO) ‘ (La₂O₃) or (LaAIO).

17. The memory of claim 14, wherein said conductive carbon includes nano carbon tube.