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US20080191324A1 - Chip package structure and method of fabricating the same - Google Patents

Chip package structure and method of fabricating the same Download PDF

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Publication number
US20080191324A1
US20080191324A1 US11/734,252 US73425207A US2008191324A1 US 20080191324 A1 US20080191324 A1 US 20080191324A1 US 73425207 A US73425207 A US 73425207A US 2008191324 A1 US2008191324 A1 US 2008191324A1
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United States
Prior art keywords
package structure
chip package
chip
leads
die pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/734,252
Inventor
Yong-Chao Qiao
Yan-Yi Wu
Jie-Hung Chiou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chipmos Technologies Inc
Original Assignee
Chipmos Technologies Bermuda Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipmos Technologies Bermuda Ltd filed Critical Chipmos Technologies Bermuda Ltd
Assigned to CHIPMOS TECHNOLOGIES (BERMUDA) LTD. reassignment CHIPMOS TECHNOLOGIES (BERMUDA) LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHIOU, JIE-HUNG, QIAO, Yong-chao, WU, Yan-yi
Publication of US20080191324A1 publication Critical patent/US20080191324A1/en
Priority to US12/423,811 priority Critical patent/US7741149B2/en
Abandoned legal-status Critical Current

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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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Definitions

  • the present invention relates to a chip package structure. More particularly, the present invention relates to a chip package structure with a lead frame.
  • IC integrated circuit
  • a wafer has an active surface, which generally refers to the surface including active devices.
  • a plurality of bonding pads is further disposed on the active surface of the wafer, such that the chip formed by sawing the wafer may be externally electrically connected to a carrier through the bonding pads.
  • the carrier is, for example, a lead frame or a package substrate.
  • the chip can be connected to the carrier by wire bonding or by flip chip bonding, such that the bonding pads on the chip are electrically connected to contacts of the carrier, thereby forming a chip package structure.
  • FIG. 1 is a schematic top view of a conventional chip package.
  • FIG. 2 is a schematic cross-sectional view showing the conventional chip package of FIG. 1 .
  • FIGS. 1 and 2 are schematic perspective diagrams seen through a molding compound 140 . Only dotted lines are adopted in FIGS. 1 and 2 for showing the profile of the molding compound 140 .
  • the chip package 100 includes a lead frame 110 , a chip 120 , a plurality of first bonding wires 130 , a plurality of second bonding wires 132 , a plurality of third bonding wires 134 , and the molding compound 140 .
  • the lead frame 110 includes a die pad 121 , a plurality of inner leads 114 , and a plurality of bus bars 116 .
  • the inner leads 114 are disposed at the periphery of the die pad 112 .
  • the bus bars 116 are disposed between the die pad 112 and the inner leads 114 .
  • the chip 120 includes an active surface 122 and a back surface 124 which are opposite to each other.
  • the chip 120 is disposed on the die pad 112 , and the back surface 124 of the chip 120 faces the die pad 112 .
  • the chip 120 includes a plurality of ground contacts 126 and a plurality of non-ground contacts 128 having a plurality of power contacts and a plurality of signal contacts.
  • the ground contacts 126 and the non-ground contacts 128 are both disposed on the active surface 122 .
  • the first bonding wires 130 electrically connect the ground contacts 126 to the bus bars 116 .
  • the second bonding wires 132 electrically connect the bus bars 116 to ground leads of the inner leads 114 .
  • the third bonding wires 134 electrically connect the rest of the inner leads 114 to the corresponding second contacts 128 , respectively.
  • the molding compound 140 encapsulates the die pad 112 , the inner leads 114 , the bus bars 116 , the chip 120 , the first bonding wires 130 , the second bonding wires 132 and the third bonding wires 134 .
  • the conventional chip package structure 100 utilizes a patterned lead frame in the packaging process.
  • the lead frame 110 includes one die pad 112 , a plurality of the inner leads 114 and a plurality of the bus bars 116 .
  • masks required in the photolithography process of patterning the lead frame are rather expensive, thereby increasing additional manufacturing costs of the lead frame.
  • the present invention is directed to a chip package structure and a method of fabricating the same, so as to reduce the packaging costs arisen from directly employing patterned lead frames in a conventional chip packaging process.
  • a metal thin plate is used in the present invention, and a die pad, a bus bar and leads of the lead frame are formed on the metal thin plate through performing an etching step during the packaging process, which is helpful to save the production costs of the chip package structure.
  • a lower encapsulant having a concave portion is used as an etching mask in the etching process to replace the conventional photomask.
  • the present invention provides a method of fabricating a chip package structure.
  • the method includes the following steps. First, a metal thin plate including an upper surface and a lower surface is provided. The upper surface of the metal thin plate has a first protrusion part, a second protrusion part, and a plurality of third protrusion parts. The second protrusion part is sandwiched between the first protrusion part and the third protrusion parts. The first, the second, and the third protrusion parts are connected to one another. Next, a chip is provided. The chip has an active surface, a back surface, and a plurality of chip bonding pads disposed on the active surface. Thereafter, the back surface of the chip is adhered to the first protrusion part.
  • first bonding wires and a plurality of second bonding wires are formed.
  • the first bonding wires respectively connect the chip bonding pads and the second protrusion part
  • the second bonding wires respectively connect the second protrusion part and the third protrusion parts.
  • an upper encapsulant is formed. The upper encapsulant encapsulates the upper surface of the metal thin plate, the chip, the first bonding wires and the second bonding wires.
  • an etching mask is formed on the lower surface of the metal thin plate, so as to expose the connections among the first, the second, and the third protrusion parts.
  • the metal thin plate is etched to an extent that the first, the second, and the third protrusion parts are electrically insulated, such that the first protrusion part constructs a die pad, the second protrusion part forms a bus bar, and the third protrusion parts frame a plurality of leads.
  • the method of fabricating the chip package structure further includes forming a lower encapsulant filled among the die pad, the bus bar and the leads after the step of etching the metal thin plate is implemented.
  • the lower encapsulant is coplanar with the etching mask.
  • the lower encapsulant further encapsulates the etching mask.
  • the method of fabricating the chip package structure further includes removing the etching mask and then forming the lower encapsulant after the step of etching the metal thin plate is implemented.
  • the metal thin plate is a copper foil.
  • the first bonding wires and the second bonding wires are formed through a wire bonding technique.
  • the etching mask is a patterned photoresist layer or a patterned solder mask layer.
  • one of the first protrusion part, the second protrusion part and the third protrusion parts or a combination thereof has a down-set design.
  • the present invention further provides a chip package structure including a chip, a lead frame, a plurality of first bonding wires, a plurality of second bonding wires, an upper encapsulant, and a first lower encapsulant, and a second lower encapsulant.
  • the chip has an active surface, a back surface, and a plurality of chip bonding pads disposed on the active surface.
  • the lead frame having an upper surface and a lower surface corresponding to the upper surface includes a die pad, a plurality of leads and at least a bus bar.
  • the back surface of the chip is adhered to the die pad.
  • the leads surround the die pad.
  • the bus bar is disposed between the die pad and the leads.
  • the first bonding wires are connected to the chip bonding pads and to the bus bar, respectively, while the second bonding wires are connected to the bus bar and to the leads, respectively.
  • the upper encapsulant encapsulates the upper surface of the lead frame, the chip, the first bonding wires and the second bonding wires.
  • the chip package structure further includes an etching mask disposed on the lower surface of the lead frame.
  • the chip package structure further includes a lower encapsulant filled among the die pad, the bus bar and the leads.
  • the lower encapsulant further encapsulates the etching mask in the chip package structure.
  • the chip package structure further includes an etching mask disposed on the lower surface of the bus bar and the lower surface of the leads.
  • the chip package structure further includes a lower encapsulant filled among the die pad, the bus bar and the leads, and the lower surface of the die pad is exposed.
  • the chip package structure further includes an etching mask disposed on the lower surface of the die pad and the lower surface of the bus bar.
  • the chip package structure further includes a lower encapsulant filled among the die pad, the bus bar and the leads, and the lower surface of the leads is exposed.
  • the chip package structure further includes an etching mask disposed on the lower surface of the bus bar.
  • the chip package structure further includes a lower encapsulant filled among the die pad, the bus bar and the leads, and the lower surface of the die pad and the lower surface of the leads are exposed.
  • the chip package structure further includes a lower encapsulant filled among the die pad, the bus bar and the leads, and the lower surface of the lead frame is encapsulated.
  • one of the die pad, the chip and the leads or a combination thereof has a down-set design.
  • the method of fabricating the chip package structure disclosed in the present invention includes disposing the chip on the metal thin plate at first and forming the necessary bonding wires and the molding compound on the chip and on the metal thin plate. Finally, a portion of the metal thin plate is etched, so as to form the die pad, the bus bar and the leads of the lead frame.
  • FIG. 1 is a schematic top view of a conventional chip package.
  • FIG. 2 is a schematic cross-sectional view of the conventional chip package of FIG. 1 .
  • FIGS. 3A through 3G are schematic cross-sectional views depicting a process of fabricating a chip package structure according to one embodiment of the present invention.
  • FIG. 4 is a schematic cross-sectional view of a chip package structure according to another embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view of a chip package structure according to still another embodiment of the present invention.
  • FIG. 6 is a schematic cross-sectional view depicting a chip package structure according to a second embodiment of the present invention.
  • FIG. 7 is a schematic cross-sectional view of a chip package structure according to a third embodiment of the present invention.
  • FIG. 8 is a schematic cross-sectional view of a chip package structure according to yet still another embodiment of the present invention.
  • FIGS. 3A through 3G are schematic cross-sectional views showing a process of fabricating a chip package structure according to a first embodiment of the present invention.
  • a metal thin plate 210 having an upper surface 210 a and a lower surface 210 b opposite to each other is provided.
  • a plurality of concave portions 218 is formed on the metal thin plate 210 , so as to divide the upper surface 210 a into a first protrusion part 212 , a second protrusion part 214 , and a plurality of third protrusion parts 216 .
  • the second protrusion part 214 is disposed outside the first protrusion part 212
  • the third protrusion parts 216 are disposed outside the second protrusion part 214 .
  • the first protrusion part 212 , the second protrusion part 214 and the third protrusion parts 216 are connected to one another.
  • the first protrusion part 212 , the second protrusion part 214 and the third protrusion parts 216 are respectively shaped as a die pad, a bus bar and leads, and thereby the die pad, the bus bar and the leads of the lead frame can be further constructed in subsequent processes.
  • the metal thin plate 210 may be made of a copper foil.
  • a chip 220 having an active surface 220 a , a back surface 220 b , and a plurality of chip bonding pads 222 is provided.
  • the active surface 220 a is opposite to the back surface 220 b
  • the chip bonding pads 222 are disposed on the active surface 220 a .
  • the back surface 220 b of the chip 220 is adhered to the first protrusion part 212 through utilizing an ultraviolet curing glue or a thermal curing glue.
  • first bonding wires 230 and a plurality of second bonding wires 240 are formed.
  • first bonding wires 230 respectively connect the chip bonding pads 222 and the second protrusion part 214
  • second bonding wires 240 respectively connect the second protrusion part 214 and the third protrusion parts 216 .
  • the first bonding wires 230 and the second bonding wires 240 may be formed through a wire bonding technique.
  • an upper encapsulant 250 is formed.
  • the upper encapsulant 250 encapsulates the upper surface 210 a of the metal thin plate 210 , the chip 220 , the first bonding wires 230 and the second bonding wires 240 .
  • an etching mask 270 is formed on the lower surface 210 b of the metal thin plate 210 .
  • the etching mask 270 exposing the connections among the first protrusion part 212 , the second protrusion part 214 , and the third protrusion parts 216 may be a patterned photoresist layer or a patterned solder mask layer.
  • the metal thin plate 210 is etched to an extent that the first protrusion part 212 , the second protrusion part 214 , and the third protrusion parts 216 are electrically insulated, such that the first protrusion part 212 constructs a die pad 212 ′ of a lead frame 210 ′, the second protrusion part 214 forms a bus bar 214 ′, and the third protrusion parts 216 form a plurality of leads 216 ′.
  • the process of fabricating the chip package structure 200 is completed.
  • a lower encapsulant 260 is filled among the die pad 212 ′, the bus bar 214 ′ and the leads 216 ′.
  • the lower encapsulant 260 is coplanar with the etching mask 270 .
  • FIG. 4 is a schematic cross-sectional view of a chip package structure according to another embodiment of the present invention.
  • a lower encapsulant 360 of a chip package structure 300 not only fills a die pad 212 ′, a bus bar 214 ′ and a plurality of leads 216 ′, but also encapsulates a lower surface 210 b of a metal thin plate 210 and an etching mask 270 .
  • FIG. 5 is a schematic cross-sectional view of a chip package structure according to still another embodiment of the present invention.
  • an etching mask 270 may be firstly removed after the step of etching a metal thin plate 210 is implemented.
  • a lower encapsulant 460 is then formed and encapsulates a lower surface 210 b of the metal thin plate 210 .
  • the method of removing the etching mask 270 includes, for example, dissolving the etching mask 270 with use of an organic solvent.
  • FIG. 6 is a schematic cross-sectional view of a chip package structure according to a second embodiment of the present invention. It should be noted that the same or similar reference numbers used in the second embodiment and in the first embodiment represent the same or the like elements, and the second embodiment is approximately identical to the first embodiment. The difference between the two embodiments will be described hereinafter, and the similarities therebetween are omitted.
  • a second protrusion part 514 of a metal thin plate 510 has a down-set design in a chip package structure 500 . That is to say, an upper surface 510 a of the second protrusion part 514 is lower than the upper surface 510 a of a first protrusion part 212 and the upper surface 510 a of a plurality of third protrusion parts 216 .
  • the lead frame 514 ′ After a lead frame 510 ′ of the metal thin plate 510 is formed, and the first protrusion part 212 , the second protrusion part 214 and the third protrusion parts 216 form a die pad 212 ′, a bus bar 514 ′ and a plurality of leads 216 ′, respectively, the lead frame 514 ′ then has the down-set design, thereby optimizing mold-flow balance. Moreover, people skilled in the art may also enable the die pad 212 ′ or the leads 216 ′ to have the down-set design, or allow a combination of any two of the die pad 212 ′, the bus bar 514 ′ and the leads 216 ′ to have the down-set design, which is not limited in the present invention.
  • FIG. 7 is a schematic cross-sectional view of a chip package structure according to a third embodiment of the present invention. It should be noted that the same or similar reference numbers used in the third embodiment and in the first embodiment represent the same or the like elements, and the third embodiment is approximately identical to the first embodiment. The difference between the two embodiments is described hereinafter, and the similarities therebetween are omitted.
  • a thickness of a die pad 612 ′ exceeds the thicknesses of a bus bar 214 ′ and of a plurality of leads 216 ′ in a lead frame 610 ′ of a chip package structure 600 .
  • an upper surface 210 a of the die pad 612 ′ is coplanar with the upper surface 210 a of the bus bar 214 ′ and the upper surface 210 a of the leads 216 ′.
  • an etching mask 270 on a lower surface 610 b of the die pad 612 ′ is removed, such that the lower surface 610 b of the die pad 612 ′ is directly contacted to the external world, which effectively improves the heat dissipation efficiency of the chip package structure 600 .
  • FIG. 8 is a schematic cross-sectional view of a chip package structure according to yet still another embodiment of the present invention.
  • an etching mask 270 and a lower encapsulant 260 expose a lower surface 710 b of a plurality of leads 716 ′.
  • the chip package structure 700 may be applied to a package structure having no leads, such as a quad flat no-lead (QFN) package structure.
  • QFN quad flat no-lead
  • etching mask and the lower encapsulant may also enable the etching mask and the lower encapsulant to expose the lower surface of the other parts of the lead frame.
  • the lower surface of the leads and the lower surface of the die pad are simultaneously exposed by the etching mask and the lower encapsulant, which is not limited in the present invention.
  • the present invention provides a method of fabricating a brand new chip package structure.
  • the method includes the steps of providing the metal thin plate that has the first protrusion part, the second protrusion part and the third protrusion parts.
  • the chip is then disposed on the metal thin plate, and the bonding wires are formed to electrically connect the chip to the second protrusion part and connect the second protrusion part to the third protrusion parts.
  • the upper encapsulant is formed on the upper surface and the lower surface of the metal thin plate, respectively.
  • the etching mask is formed on the lower surface of the metal think plate and exposes the connections among the first, the second, and the third protrusion parts.
  • the metal thin plate is etched, such that the first protrusion part, the second protrusion part and the third protrusion parts form the die pad, the bus bar and the leads of the lead frame, respectively.
  • the method disclosed in the present invention is implemented by disposing the chip on the metal thin plate, forming the necessary bonding wires and the molding compound, and etching a portion of the metal thin plate so as to form the die pad, the bus bar and the leads of the lead frame.
  • the metal thin plate in the present invention the die pad, the bus bar and the leads are formed on the metal thin plate through performing the etching step during the packaging process, which is conducive to saving the production costs of the chip package structure and to reducing the packaging costs arisen from directly employing the patterned lead frame in the conventional chip packaging process.
  • one of the die pad, the bus bar and the leads or the combination of any two of the die pad, the bus bar and the leads may have the down-set design, so as to optimize mold-flow balance.
  • the lower surface of the die pad can be exposed by the etching mask and by the lower encapsulant, which effectively improves the heat dissipation efficiency of the chip package structure.
  • the lower surface of the leads can also be exposed by the etching mask and by the lower encapsulant, such that the chip package structure of the present invention can be applied to the package structure having no leads.

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  • Microelectronics & Electronic Packaging (AREA)
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Abstract

A method of fabricating a chip package structure includes the steps of providing a metal thin plate having a first protrusion part, a second protrusion part and a plurality of third protrusion parts. A chip is then disposed on the metal thin plate and a plurality of bonding wires is formed to electrically connect the chip to the second protrusion part and connect the second protrusion part to the third protrusion parts. Next, an upper encapsulant and a lower encapsulant are formed on an upper surface and a lower surface of the metal thin plate, respectively. Thereafter, an etching mask is formed on the lower surface and exposes the connections among the protrusion parts. Finally, the metal thin plate is etched, such that the first protrusion part, the second protrusion part and the third protrusion parts form a die pad, a bus bar and leads of a lead frame, respectively.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application claims the priority benefit of P.R.C. application serial no. 200710005145.0, filed Feb. 8, 2007. All disclosure of the P.R.C. application is incorporated herein by reference.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a chip package structure. More particularly, the present invention relates to a chip package structure with a lead frame.
  • 2. Description of Related Art
  • The production of integrated circuit (IC) devices is mainly divided into three stages including IC design, IC process and IC package.
  • During the IC process, a chip is manufactured by the steps of wafer fabrication, IC formation, wafer sawing and so on. A wafer has an active surface, which generally refers to the surface including active devices. After the IC inside the wafer is completely formed, a plurality of bonding pads is further disposed on the active surface of the wafer, such that the chip formed by sawing the wafer may be externally electrically connected to a carrier through the bonding pads. The carrier is, for example, a lead frame or a package substrate. The chip can be connected to the carrier by wire bonding or by flip chip bonding, such that the bonding pads on the chip are electrically connected to contacts of the carrier, thereby forming a chip package structure.
  • FIG. 1 is a schematic top view of a conventional chip package. FIG. 2 is a schematic cross-sectional view showing the conventional chip package of FIG. 1. For the convenience of illustration, please refer to FIGS. 1 and 2 which are schematic perspective diagrams seen through a molding compound 140. Only dotted lines are adopted in FIGS. 1 and 2 for showing the profile of the molding compound 140. The chip package 100 includes a lead frame 110, a chip 120, a plurality of first bonding wires 130, a plurality of second bonding wires 132, a plurality of third bonding wires 134, and the molding compound 140. The lead frame 110 includes a die pad 121, a plurality of inner leads 114, and a plurality of bus bars 116. The inner leads 114 are disposed at the periphery of the die pad 112. The bus bars 116 are disposed between the die pad 112 and the inner leads 114.
  • The chip 120 includes an active surface 122 and a back surface 124 which are opposite to each other. The chip 120 is disposed on the die pad 112, and the back surface 124 of the chip 120 faces the die pad 112. The chip 120 includes a plurality of ground contacts 126 and a plurality of non-ground contacts 128 having a plurality of power contacts and a plurality of signal contacts. The ground contacts 126 and the non-ground contacts 128 are both disposed on the active surface 122.
  • The first bonding wires 130 electrically connect the ground contacts 126 to the bus bars 116. The second bonding wires 132 electrically connect the bus bars 116 to ground leads of the inner leads 114. And the third bonding wires 134 electrically connect the rest of the inner leads 114 to the corresponding second contacts 128, respectively. The molding compound 140 encapsulates the die pad 112, the inner leads 114, the bus bars 116, the chip 120, the first bonding wires 130, the second bonding wires 132 and the third bonding wires 134.
  • It should be noted that the conventional chip package structure 100 utilizes a patterned lead frame in the packaging process. The lead frame 110 includes one die pad 112, a plurality of the inner leads 114 and a plurality of the bus bars 116. However, masks required in the photolithography process of patterning the lead frame are rather expensive, thereby increasing additional manufacturing costs of the lead frame.
    • SUMMARY OF THE INVENTION
  • The present invention is directed to a chip package structure and a method of fabricating the same, so as to reduce the packaging costs arisen from directly employing patterned lead frames in a conventional chip packaging process. Specifically, a metal thin plate is used in the present invention, and a die pad, a bus bar and leads of the lead frame are formed on the metal thin plate through performing an etching step during the packaging process, which is helpful to save the production costs of the chip package structure.
  • On the other hand, in the present invention, a lower encapsulant having a concave portion is used as an etching mask in the etching process to replace the conventional photomask. Thereby, the costs of the photomasks are significantly reduced, and the packaging costs are further decreased.
  • To resolve the foregoing issues, the present invention provides a method of fabricating a chip package structure. The method includes the following steps. First, a metal thin plate including an upper surface and a lower surface is provided. The upper surface of the metal thin plate has a first protrusion part, a second protrusion part, and a plurality of third protrusion parts. The second protrusion part is sandwiched between the first protrusion part and the third protrusion parts. The first, the second, and the third protrusion parts are connected to one another. Next, a chip is provided. The chip has an active surface, a back surface, and a plurality of chip bonding pads disposed on the active surface. Thereafter, the back surface of the chip is adhered to the first protrusion part. After that, a plurality of first bonding wires and a plurality of second bonding wires are formed. Here, the first bonding wires respectively connect the chip bonding pads and the second protrusion part, and the second bonding wires respectively connect the second protrusion part and the third protrusion parts. Afterwards, an upper encapsulant is formed. The upper encapsulant encapsulates the upper surface of the metal thin plate, the chip, the first bonding wires and the second bonding wires. Next, an etching mask is formed on the lower surface of the metal thin plate, so as to expose the connections among the first, the second, and the third protrusion parts. Eternally, the metal thin plate is etched to an extent that the first, the second, and the third protrusion parts are electrically insulated, such that the first protrusion part constructs a die pad, the second protrusion part forms a bus bar, and the third protrusion parts frame a plurality of leads.
  • According to one embodiment of the present invention, the method of fabricating the chip package structure further includes forming a lower encapsulant filled among the die pad, the bus bar and the leads after the step of etching the metal thin plate is implemented.
  • According to one embodiment of the present invention, the lower encapsulant is coplanar with the etching mask.
  • According to one embodiment of the present invention, the lower encapsulant further encapsulates the etching mask.
  • According to one embodiment of the present invention, the method of fabricating the chip package structure further includes removing the etching mask and then forming the lower encapsulant after the step of etching the metal thin plate is implemented.
  • According to one embodiment of the present invention, the metal thin plate is a copper foil.
  • According to one embodiment of the present invention, the first bonding wires and the second bonding wires are formed through a wire bonding technique.
  • According to one embodiment of the present invention, the etching mask is a patterned photoresist layer or a patterned solder mask layer.
  • According to one embodiment of the present invention, one of the first protrusion part, the second protrusion part and the third protrusion parts or a combination thereof has a down-set design.
  • The present invention further provides a chip package structure including a chip, a lead frame, a plurality of first bonding wires, a plurality of second bonding wires, an upper encapsulant, and a first lower encapsulant, and a second lower encapsulant. The chip has an active surface, a back surface, and a plurality of chip bonding pads disposed on the active surface. The lead frame having an upper surface and a lower surface corresponding to the upper surface includes a die pad, a plurality of leads and at least a bus bar. The back surface of the chip is adhered to the die pad. The leads surround the die pad. The bus bar is disposed between the die pad and the leads. The first bonding wires are connected to the chip bonding pads and to the bus bar, respectively, while the second bonding wires are connected to the bus bar and to the leads, respectively. The upper encapsulant encapsulates the upper surface of the lead frame, the chip, the first bonding wires and the second bonding wires.
  • According to one embodiment of the present invention, the chip package structure further includes an etching mask disposed on the lower surface of the lead frame.
  • According to one embodiment of the present invention, the chip package structure further includes a lower encapsulant filled among the die pad, the bus bar and the leads.
  • According to one embodiment of the present invention, the lower encapsulant further encapsulates the etching mask in the chip package structure.
  • According to one embodiment of the present invention, the chip package structure further includes an etching mask disposed on the lower surface of the bus bar and the lower surface of the leads.
  • According to one embodiment of the present invention, the chip package structure further includes a lower encapsulant filled among the die pad, the bus bar and the leads, and the lower surface of the die pad is exposed.
  • According to one embodiment of the present invention, the chip package structure further includes an etching mask disposed on the lower surface of the die pad and the lower surface of the bus bar.
  • According to one embodiment of the present invention, the chip package structure further includes a lower encapsulant filled among the die pad, the bus bar and the leads, and the lower surface of the leads is exposed.
  • According to one embodiment of the present invention, the chip package structure further includes an etching mask disposed on the lower surface of the bus bar.
  • According to one embodiment of the present invention, the chip package structure further includes a lower encapsulant filled among the die pad, the bus bar and the leads, and the lower surface of the die pad and the lower surface of the leads are exposed.
  • According to one embodiment of the present invention, the chip package structure further includes a lower encapsulant filled among the die pad, the bus bar and the leads, and the lower surface of the lead frame is encapsulated.
  • According to one embodiment of the present invention, one of the die pad, the chip and the leads or a combination thereof has a down-set design.
  • The method of fabricating the chip package structure disclosed in the present invention includes disposing the chip on the metal thin plate at first and forming the necessary bonding wires and the molding compound on the chip and on the metal thin plate. Finally, a portion of the metal thin plate is etched, so as to form the die pad, the bus bar and the leads of the lead frame.
  • In order to make the aforementioned and other objects, features and advantages of the present invention more comprehensible, several embodiments accompanied with figures are described in detail below.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic top view of a conventional chip package.
  • FIG. 2 is a schematic cross-sectional view of the conventional chip package of FIG. 1.
  • FIGS. 3A through 3G are schematic cross-sectional views depicting a process of fabricating a chip package structure according to one embodiment of the present invention.
  • FIG. 4 is a schematic cross-sectional view of a chip package structure according to another embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view of a chip package structure according to still another embodiment of the present invention.
  • FIG. 6 is a schematic cross-sectional view depicting a chip package structure according to a second embodiment of the present invention.
  • FIG. 7 is a schematic cross-sectional view of a chip package structure according to a third embodiment of the present invention.
  • FIG. 8 is a schematic cross-sectional view of a chip package structure according to yet still another embodiment of the present invention.
    •  DESCRIPTION OF EMBODIMENTS
  • FIGS. 3A through 3G are schematic cross-sectional views showing a process of fabricating a chip package structure according to a first embodiment of the present invention. First, referring to FIG. 3A, a metal thin plate 210 having an upper surface 210 a and a lower surface 210 b opposite to each other is provided. A plurality of concave portions 218 is formed on the metal thin plate 210, so as to divide the upper surface 210 a into a first protrusion part 212, a second protrusion part 214, and a plurality of third protrusion parts 216. The second protrusion part 214 is disposed outside the first protrusion part 212, and the third protrusion parts 216 are disposed outside the second protrusion part 214. The first protrusion part 212, the second protrusion part 214 and the third protrusion parts 216 are connected to one another. Moreover, the first protrusion part 212, the second protrusion part 214 and the third protrusion parts 216 are respectively shaped as a die pad, a bus bar and leads, and thereby the die pad, the bus bar and the leads of the lead frame can be further constructed in subsequent processes. According to the present embodiment, the metal thin plate 210 may be made of a copper foil.
  • Next, referring to FIG. 3B, a chip 220 having an active surface 220 a, a back surface 220 b, and a plurality of chip bonding pads 222 is provided. Here, the active surface 220 a is opposite to the back surface 220 b, and the chip bonding pads 222 are disposed on the active surface 220 a. Thereafter, the back surface 220 b of the chip 220 is adhered to the first protrusion part 212 through utilizing an ultraviolet curing glue or a thermal curing glue.
  • After that, referring to FIG. 3C, a plurality of first bonding wires 230 and a plurality of second bonding wires 240 are formed. Here, the first bonding wires 230 respectively connect the chip bonding pads 222 and the second protrusion part 214, and the second bonding wires 240 respectively connect the second protrusion part 214 and the third protrusion parts 216. The first bonding wires 230 and the second bonding wires 240 may be formed through a wire bonding technique.
  • Afterwards, as indicated in FIG. 3D, an upper encapsulant 250 is formed. The upper encapsulant 250 encapsulates the upper surface 210 a of the metal thin plate 210, the chip 220, the first bonding wires 230 and the second bonding wires 240.
  • Then, referring to FIG. 3E, an etching mask 270 is formed on the lower surface 210 b of the metal thin plate 210. The etching mask 270 exposing the connections among the first protrusion part 212, the second protrusion part 214, and the third protrusion parts 216 may be a patterned photoresist layer or a patterned solder mask layer.
  • Next, with reference to FIG. 3F, the metal thin plate 210 is etched to an extent that the first protrusion part 212, the second protrusion part 214, and the third protrusion parts 216 are electrically insulated, such that the first protrusion part 212 constructs a die pad 212′ of a lead frame 210′, the second protrusion part 214 forms a bus bar 214′, and the third protrusion parts 216 form a plurality of leads 216′. Thus far, the process of fabricating the chip package structure 200 is completed.
  • Referring to FIG. 3G, to prevent the die pad 212′, the bus bar 214′ and the leads 216′ from being oxidized due to exposure to the air, a lower encapsulant 260 is filled among the die pad 212′, the bus bar 214′ and the leads 216′. Here, the lower encapsulant 260 is coplanar with the etching mask 270.
  • Besides, the lower encapsulant 260 can be arranged in other manners, which is not limited in the present invention. FIG. 4 is a schematic cross-sectional view of a chip package structure according to another embodiment of the present invention. Referring to FIG. 4, in the present embodiment, a lower encapsulant 360 of a chip package structure 300 not only fills a die pad 212′, a bus bar 214′ and a plurality of leads 216′, but also encapsulates a lower surface 210 b of a metal thin plate 210 and an etching mask 270.
  • FIG. 5 is a schematic cross-sectional view of a chip package structure according to still another embodiment of the present invention. Referring to FIG. 5, during the fabrication of a chip package structure 400, an etching mask 270 may be firstly removed after the step of etching a metal thin plate 210 is implemented. A lower encapsulant 460 is then formed and encapsulates a lower surface 210 b of the metal thin plate 210. Here, the method of removing the etching mask 270 includes, for example, dissolving the etching mask 270 with use of an organic solvent.
    • Second Embodiment
  • FIG. 6 is a schematic cross-sectional view of a chip package structure according to a second embodiment of the present invention. It should be noted that the same or similar reference numbers used in the second embodiment and in the first embodiment represent the same or the like elements, and the second embodiment is approximately identical to the first embodiment. The difference between the two embodiments will be described hereinafter, and the similarities therebetween are omitted.
  • Referring to FIG. 6, the difference between the second embodiment and the first embodiment lies in that a second protrusion part 514 of a metal thin plate 510 has a down-set design in a chip package structure 500. That is to say, an upper surface 510 a of the second protrusion part 514 is lower than the upper surface 510 a of a first protrusion part 212 and the upper surface 510 a of a plurality of third protrusion parts 216. After a lead frame 510′ of the metal thin plate 510 is formed, and the first protrusion part 212, the second protrusion part 214 and the third protrusion parts 216 form a die pad 212′, a bus bar 514′ and a plurality of leads 216′, respectively, the lead frame 514′ then has the down-set design, thereby optimizing mold-flow balance. Moreover, people skilled in the art may also enable the die pad 212′ or the leads 216′ to have the down-set design, or allow a combination of any two of the die pad 212′, the bus bar 514′ and the leads 216′ to have the down-set design, which is not limited in the present invention.
    • Third Embodiment
  • FIG. 7 is a schematic cross-sectional view of a chip package structure according to a third embodiment of the present invention. It should be noted that the same or similar reference numbers used in the third embodiment and in the first embodiment represent the same or the like elements, and the third embodiment is approximately identical to the first embodiment. The difference between the two embodiments is described hereinafter, and the similarities therebetween are omitted.
  • Please refer to FIG. 7. The difference between the third embodiment and the first embodiment lies in that a thickness of a die pad 612′ exceeds the thicknesses of a bus bar 214′ and of a plurality of leads 216′ in a lead frame 610′ of a chip package structure 600. And an upper surface 210 a of the die pad 612′ is coplanar with the upper surface 210 a of the bus bar 214′ and the upper surface 210 a of the leads 216′. After the fabrication of the chip package structure 600 is basically completed, an etching mask 270 on a lower surface 610 b of the die pad 612′ is removed, such that the lower surface 610 b of the die pad 612′ is directly contacted to the external world, which effectively improves the heat dissipation efficiency of the chip package structure 600.
  • Besides, the etching mask and a lower encapsulant may expose the lower surface of the leads as well. FIG. 8 is a schematic cross-sectional view of a chip package structure according to yet still another embodiment of the present invention. Referring to FIG. 8, in a lead frame 710′ of a chip package structure 700, an etching mask 270 and a lower encapsulant 260 expose a lower surface 710 b of a plurality of leads 716′. Thereby, the chip package structure 700 may be applied to a package structure having no leads, such as a quad flat no-lead (QFN) package structure. Aside from the above, people skilled in the art may also enable the etching mask and the lower encapsulant to expose the lower surface of the other parts of the lead frame. For example, the lower surface of the leads and the lower surface of the die pad are simultaneously exposed by the etching mask and the lower encapsulant, which is not limited in the present invention.
  • In view of the foregoing, the present invention provides a method of fabricating a brand new chip package structure. The method includes the steps of providing the metal thin plate that has the first protrusion part, the second protrusion part and the third protrusion parts. The chip is then disposed on the metal thin plate, and the bonding wires are formed to electrically connect the chip to the second protrusion part and connect the second protrusion part to the third protrusion parts. Next, the upper encapsulant is formed on the upper surface and the lower surface of the metal thin plate, respectively. Thereafter, the etching mask is formed on the lower surface of the metal think plate and exposes the connections among the first, the second, and the third protrusion parts. Finally, the metal thin plate is etched, such that the first protrusion part, the second protrusion part and the third protrusion parts form the die pad, the bus bar and the leads of the lead frame, respectively.
  • In comparison with the conventional method of fabricating the chip package structure with direct use of the patterned lead frame as the carrier, the method disclosed in the present invention is implemented by disposing the chip on the metal thin plate, forming the necessary bonding wires and the molding compound, and etching a portion of the metal thin plate so as to form the die pad, the bus bar and the leads of the lead frame. With use of the metal thin plate in the present invention, the die pad, the bus bar and the leads are formed on the metal thin plate through performing the etching step during the packaging process, which is conducive to saving the production costs of the chip package structure and to reducing the packaging costs arisen from directly employing the patterned lead frame in the conventional chip packaging process.
  • In addition, in the chip package structure disclosed in the present invention, one of the die pad, the bus bar and the leads or the combination of any two of the die pad, the bus bar and the leads may have the down-set design, so as to optimize mold-flow balance. Moreover, in the chip package structure disclosed in the present invention, the lower surface of the die pad can be exposed by the etching mask and by the lower encapsulant, which effectively improves the heat dissipation efficiency of the chip package structure. Furthermore, the lower surface of the leads can also be exposed by the etching mask and by the lower encapsulant, such that the chip package structure of the present invention can be applied to the package structure having no leads.
  • It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Claims (21)

What is claimed is:
1. A method of fabricating a chip package structure, comprising:
providing a metal thin plate comprising an upper surface and a lower surface, wherein the upper surface of the metal thin plate has a first protrusion part, a second protrusion part, and a plurality of third protrusion parts, the second protrusion part being sandwiched between the first protrusion part and the third protrusion parts, the first, the second, and the third protrusion parts being connected to one another;
providing a chip having an active surface, a back surface, and a plurality of chip bonding pads disposed on the active surface;
adhering the back surface of the chip to the first protrusion part;
forming a plurality of first bonding wires and a plurality of second bonding wires, wherein the first bonding wires respectively connect the chip bonding pads and the second protrusion part, and the second bonding wires respectively connect the second protrusion part and the third protrusion parts;
forming an upper encapsulant encapsulating the upper surface of the metal thin plate, the chip, the first bonding wires and the second bonding wires;
forming an etching mask on the lower surface to expose the connections among the first, the second, and the third protrusion parts; and
etching the metal thin plate to an extent that the first, the second, and the third protrusion parts are electrically insulated, such that the first protrusion part constructs a die pad, the second protrusion part forms a bus bar, and the third protrusion parts form a plurality of leads.
2. The method of fabricating the chip package structure of claim 1, further comprising forming a lower encapsulant filled among the die pad, the bus bar and the leads after the step of etching the metal thin plate is implemented.
3. The method of fabricating the chip package structure of claim 2, wherein the lower encapsulant is coplanar with the etching mask.
4. The method of fabricating the chip package structure of claim 2, wherein the lower encapsulant further encapsulates the etching mask.
5. The method of fabricating the chip package structure of claim 2, further comprising removing the etching mask and then forming the lower encapsulant after the step of etching the metal thin plate is implemented.
6. The method of fabricating the chip package structure of claim 1, wherein the metal thin plate is a copper foil.
7. The method of fabricating the chip package structure of claim 1, wherein the first bonding wires and the second bonding wires are formed through a wire bonding technique.
8. The method of fabricating the chip package structure of claim 1, wherein the etching mask is a patterned photoresist layer or a patterned solder mask layer.
9. The method of fabricating the chip package structure of claim 1, wherein one of the first protrusion part, the second protrusion part and the third protrusion parts or a combination thereof has a down-set design.
10. A chip package structure, comprising:
a chip having an active surface, a back surface, and a plurality of chip bonding pads disposed on the active surface;
a lead frame having an upper surface and a lower surface corresponding to the upper surface, the lead frame comprising:
a die pad to which the back surface of the chip is adhered;
a plurality of leads surrounding the die pad; and
at least a bus bar disposed between the die pad and the leads;
a plurality of first bonding wires connected to the chip bonding pads and to the bus bar, respectively;
a plurality of second bonding wires connected to the bus bar and to the leads, respectively; and
an upper encapsulant encapsulating the upper surface of the lead frame, the chip, the first bonding wires and the second bonding wires.
11. The chip package structure of claim 10, further comprising an etching mask disposed on the lower surface of the lead frame.
12. The chip package structure of claim 11, further comprising a lower encapsulant filled among the die pad, the bus bar and the leads.
13. The chip package structure of claim 12, wherein the lower encapsulant further encapsulates the etching mask.
14. The chip package structure of claim 10, further comprising an etching mask disposed on the lower surface of the bus bar and the lower surface of the leads.
15. The chip package structure of claim 14, further comprising a lower encapsulant filled among the die pad, the bus bar and the leads, so as to expose the lower surface of the die pad.
16. The chip package structure of claim 10, further comprising an etching mask disposed on the lower surface of the die pad and the lower surface of the bus bar.
17. The chip package structure of claim 16, further comprising a lower encapsulant filled among the die pad, the bus bar and the leads, so as to expose the lower surface of the leads.
18. The chip package structure of claim 10, further comprising an etching mask disposed on the lower surface of the bus bar.
19. The chip package structure of claim 18, further comprising a lower encapsulant filled among the die pad, the bus bar and the leads, so as to expose the lower surface of the die pad and the lower surface of the leads.
20. The chip package structure of claim 10, further comprising a lower encapsulant filled among the die pad, the bus bar and the leads, so as to encapsulate the lower surface of the lead frame.
21. The chip package structure of claim 10, wherein one of the bus bar, the die pad and the leads or a combination thereof has a down-set design.
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Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090127684A1 (en) * 2007-11-21 2009-05-21 Chipmos Technologies Inc. Leadframe for leadless package
US20090127682A1 (en) * 2007-11-16 2009-05-21 Advanced Semiconductor Engineering, Inc. Chip package structure and method of fabricating the same
US20100207260A1 (en) * 2007-07-18 2010-08-19 Mediatek Inc. Quad flat package with exposed common electrode bars
CN101958302A (en) * 2010-09-04 2011-01-26 江苏长电科技股份有限公司 Double-sided graphics chip flip-chip single-chip packaging structure and packaging method
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US20130277815A1 (en) * 2012-04-19 2013-10-24 Amkor Technology, Inc. Method of forming a thin substrate chip scale package device and structure
US9252089B2 (en) * 2014-04-17 2016-02-02 Infineon Technologies Ag Universal lead frame for flat no-leads packages
US20160293523A1 (en) * 2015-03-31 2016-10-06 Stmicroelectronics, Inc. Semiconductor device including conductive clip with flexible leads and related methods
US20170301626A1 (en) * 2014-08-26 2017-10-19 Advanced Semiconductor Engineering, Inc. Embedded component package structure and method of manufacturing the same
US9922919B2 (en) 2015-03-20 2018-03-20 Amkor Technology, Inc. Electronic package structure having insulated substrate with lands and conductive patterns
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US20200091028A1 (en) * 2018-09-18 2020-03-19 Korea Electronics Technology Institute Semiconductor package using high power and high frequency and method of manufacturing same

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100539054C (en) * 2007-03-13 2009-09-09 百慕达南茂科技股份有限公司 Chip-packaging structure and preparation method thereof
CN101937886B (en) * 2009-06-30 2012-06-27 国碁电子(中山)有限公司 Thin chip package structure and method
CN102324411A (en) * 2011-09-13 2012-01-18 江苏长电科技股份有限公司 A Novel Baseless Island Prefilled Molded Lead Frame Structure
CN102324412B (en) * 2011-09-13 2013-03-06 江苏长电科技股份有限公司 Island-free lead frame structure prefilled with plastic encapsulating material, plated firstly and etched later and production method thereof
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US9105620B1 (en) 2012-12-27 2015-08-11 Stats Chippac Ltd. Integrated circuit packaging system with routable traces and method of manufacture thereof
US9620480B1 (en) 2013-06-28 2017-04-11 STATS ChipPAC Pte. Ltd Integrated circuit packaging system with unplated leadframe and method of manufacture thereof
US9177897B1 (en) 2013-06-28 2015-11-03 Stats Chippac Ltd. Integrated circuit packaging system with trace protection layer and method of manufacture thereof
US9190349B1 (en) 2013-06-28 2015-11-17 Stats Chippac Ltd. Integrated circuit packaging system with leadframe and method of manufacture thereof
US9607933B2 (en) * 2014-02-07 2017-03-28 Dawning Leading Technology Inc. Lead frame structure for quad flat no-lead package, quad flat no-lead package and method for forming the lead frame structure
TWI566358B (en) * 2014-11-28 2017-01-11 矽品精密工業股份有限公司 Leadframe structure and semiconductor package thereof
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CN116960001A (en) * 2023-09-12 2023-10-27 深圳市信展通电子股份有限公司 High-density arrangement semiconductor packaging method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070052076A1 (en) * 2002-04-29 2007-03-08 Ramos Mary J Partially Patterned Lead Frames and Methods of Making and Using the Same in Semiconductor Packaging
US7446400B2 (en) * 2006-07-05 2008-11-04 Chipmos Technologies, Inc. Chip package structure and fabricating method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6989294B1 (en) * 1998-06-10 2006-01-24 Asat, Ltd. Leadless plastic chip carrier with etch back pad singulation

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070052076A1 (en) * 2002-04-29 2007-03-08 Ramos Mary J Partially Patterned Lead Frames and Methods of Making and Using the Same in Semiconductor Packaging
US7446400B2 (en) * 2006-07-05 2008-11-04 Chipmos Technologies, Inc. Chip package structure and fabricating method thereof

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100207260A1 (en) * 2007-07-18 2010-08-19 Mediatek Inc. Quad flat package with exposed common electrode bars
US8283757B2 (en) * 2007-07-18 2012-10-09 Mediatek Inc. Quad flat package with exposed common electrode bars
US20090127682A1 (en) * 2007-11-16 2009-05-21 Advanced Semiconductor Engineering, Inc. Chip package structure and method of fabricating the same
US20090127684A1 (en) * 2007-11-21 2009-05-21 Chipmos Technologies Inc. Leadframe for leadless package
CN101958302A (en) * 2010-09-04 2011-01-26 江苏长电科技股份有限公司 Double-sided graphics chip flip-chip single-chip packaging structure and packaging method
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US20130277815A1 (en) * 2012-04-19 2013-10-24 Amkor Technology, Inc. Method of forming a thin substrate chip scale package device and structure
US9129975B2 (en) * 2012-04-19 2015-09-08 Amkor Technology, Inc. Method of forming a thin substrate chip scale package device and structure
US20150332991A1 (en) * 2012-04-19 2015-11-19 Amkor Technology, Inc. Method of forming a thin substrate chip scale package device and structure
US9252089B2 (en) * 2014-04-17 2016-02-02 Infineon Technologies Ag Universal lead frame for flat no-leads packages
US20170301626A1 (en) * 2014-08-26 2017-10-19 Advanced Semiconductor Engineering, Inc. Embedded component package structure and method of manufacturing the same
US10276507B2 (en) * 2014-08-26 2019-04-30 Advanced Semiconductor Engineering, Inc. Embedded component package structure and method of manufacturing the same
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US10910298B2 (en) 2015-03-20 2021-02-02 Amkor Technology Singapore Holding Pte. Ltd. Method of forming a molded substrate electronic package and structure
US11961794B2 (en) 2015-03-20 2024-04-16 Amikor Technology Singapore Holding Pte. Ltd. Method of forming a molded substrate electronic package and structure
US20160293523A1 (en) * 2015-03-31 2016-10-06 Stmicroelectronics, Inc. Semiconductor device including conductive clip with flexible leads and related methods
US9818675B2 (en) * 2015-03-31 2017-11-14 Stmicroelectronics, Inc. Semiconductor device including conductive clip with flexible leads and related methods
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US11088053B2 (en) 2019-07-19 2021-08-10 Guangdong Chippacking Technology Co., Ltd. Encapsulation structure with high density, multiple sided and exposed leads and method for manufacturing the same

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