[go: up one dir, main page]

US20080122082A1 - Semiconductor device and semiconductor package containing the same - Google Patents

Semiconductor device and semiconductor package containing the same Download PDF

Info

Publication number
US20080122082A1
US20080122082A1 US11/939,734 US93973407A US2008122082A1 US 20080122082 A1 US20080122082 A1 US 20080122082A1 US 93973407 A US93973407 A US 93973407A US 2008122082 A1 US2008122082 A1 US 2008122082A1
Authority
US
United States
Prior art keywords
bump electrode
semiconductor device
electrode
electrode pad
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/939,734
Inventor
Hiroshi Yamamoto
Eiji Takeichi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lapis Semiconductor Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Assigned to OKI ELECTRIC INDUSTRY CO., LTD. reassignment OKI ELECTRIC INDUSTRY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TAKEICHI, EIJI, YAMAMOTO, HIROSHI
Publication of US20080122082A1 publication Critical patent/US20080122082A1/en
Assigned to OKI SEMICONDUCTOR CO., LTD. reassignment OKI SEMICONDUCTOR CO., LTD. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: OKI ELECTRIC INDUSTRY CO., LTD.
Priority to US14/164,298 priority Critical patent/US9196580B2/en
Assigned to Lapis Semiconductor Co., Ltd. reassignment Lapis Semiconductor Co., Ltd. CHANGE OF NAME Assignors: OKI SEMICONDUCTOR CO., LTD
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05669—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01002—Helium [He]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • the present invention relates to a semiconductor device having bump electrode as an external terminal, implemented with TCP (Tape Carrier Package) or COF (Chip On Film) technologies. More particularly, the present invention relates to an LCD (Liquid Crystal Display) driver package provided with a plurality of narrow-pitch bump electrodes.
  • TCP Transmission Carrier Package
  • COF Chip On Film
  • TAB Tepe Automated Bonding
  • a bump electrode is formed as an external terminal, and the semiconductor chip is bonded to a film carrier with Inner-Lead Bonding (ILB).
  • the film carrier has a long tape-like shape, on which repetitive wiring patterns are formed.
  • the film carrier has device holes, each of which exposes an inner lead, and outer leads, and is automatically conveyed for each device hole.
  • the semiconductor chip is aligned with a given position of the device hole, and the bump electrode thereof is bonded to the inner lead on the film carrier using a technology such as a thermal compression bonding process. Subsequently, the outer leads are bonded to key points on the semiconductor chip.
  • FIGS. 1A and 1B are a plan view and a cross-sectional view, respectively, of a conventional semiconductor device, showing a structure around a bump electrode thereof.
  • a semiconductor device 12 includes a semiconductor chip 11 and an electrode pad 22 .
  • the semiconductor chip 11 further includes a plurality of wiring layers (not shown diagrammatically) that are insulated from each other with inter-layer insulating films.
  • the electrode pad 22 is provided as a part of the wirings at the uppermost layer.
  • a passivation film 24 having an opening, which is smaller in size than the bump electrode 14 , which is to be explained hereinafter, is provided on the electrode pad 22 .
  • An under-bump metal 23 is formed on the passivation film 24 , and connected to the electrode pad 22 through the opening thereof.
  • the bump electrode 14 is connected to the electrode pad 22 via the under-bump metal 23 .
  • An inner lead 18 of a film carrier is connected to the bump electrode 14 by a thermal compression bonding process.
  • the electrode pad 22 is kept larger in dimension than the bump electrode 14 . Therefore, the bump electrode 14 completely overlaps with the electrode pad 22 .
  • Japanese Patent Number 2919488 discloses a technology related to the present invention.
  • the electrode pad has come to occupy a large portion of the chip footprint, leading to reduced competitiveness in cost.
  • the electrode pad 22 had to be larger in size than the bump electrode 14 to ensure the flatness of the passivation film 24 .
  • an object of the present invention is to provide a semiconductor device and a semiconductor package for reducing the size of the semiconductor device without sacrificing the flatness of the passivation film, by utilizing the area under the bump electrode more effectively.
  • a semiconductor device having an electrode pad as a part of an uppermost wiring layer, includes a passivation film, which is formed on the electrode pad to have an opening therein; and a bump electrode for external connection, which is formed on the passivation film and is electrically connected to the electrode pad through the opening of the passivation film.
  • the electrode pad is formed so as to be smaller in size than the bump electrode.
  • a part of the uppermost wiring layer is formed under the bump electrode.
  • the “uppermost wiring layer” herein means the single wiring layer itself. If there are a plurality of wiring layers, which are insulated from each other with inter-layer insulating films, the uppermost wiring layer means the wiring layer formed on the uppermost layer among those wiring layers.
  • a semiconductor package having the semiconductor device according to the first aspect of the present invention, is fabricated using a film carrier having a plurality of leads, which are held on an insulating film, and an end of each of the leads are connected to the bump electrode as an inner lead.
  • an internal wiring can be arranged in an area where an electrode pad was conventionally formed, so that the chip size can be reduced.
  • the passivation film can be kept flat by certain formations of the internal wirings. Therefore, it is possible to prevent the manufacturing process from becoming complicated and the manufacturing cost from increasing, without providing a special design such as arranging dummy wirings under the bump electrode.
  • the passivation film is kept flat, the flatness of the bump electrode itself is improved, further improving the connection with the inner lead, which is connected with the bump electrode using a technology such as a thermal compression bonding process. Furthermore, it is possible to prevent a formation of a gap between the passivation film and the bump electrode, therefore, to reduce the risk of short circuit caused by a foreign substance getting into the gap.
  • FIGS. 1A and 1B are a plan view and a cross-sectional view, respectively, of a conventional semiconductor device, showing a structure around a bump electrode thereof;
  • FIG. 2 is a side view of a semiconductor package related to the present invention.
  • FIGS. 3A and 3B are a plan view and a cross-sectional view, respectively, of a semiconductor device according to a first embodiment of the present invention, showing a structure around a bump electrode thereof;
  • FIG. 4 is a plan view of the semiconductor device according to the first embodiment of the present invention, showing the structure around the bump electrode and the layout of the electrode pad and wirings provided under the bump electrode;
  • FIG. 5 is a plan view of the semiconductor device according to a second embodiment of the present invention, showing a structure around a bump electrode and a layout of an electrode pad and wirings provided under the bump electrode;
  • FIG. 6 is a plan view of the semiconductor device according to a third embodiment of the present invention, showing a structure around a bump electrode and a layout of an electrode pad and wirings provided under the bump electrode.
  • FIG. 2 is a side view of a semiconductor package related to the present invention.
  • a semiconductor package 100 includes a semiconductor device 112 , a plurality of leads 118 , and a resin member 120 .
  • the semiconductor device 112 is provided with a semiconductor chip 111 and electrode pads 122 .
  • the semiconductor chip 111 further includes a plurality of wiring layers that are insulated from each other with inter-layer insulating films.
  • the electrode pads 122 are provided as a part of the wirings on the uppermost wiring layer.
  • the leads 118 are held on an insulating film 116 .
  • the resin member 120 is provided to protect the surface of the semiconductor device 112 and the inner lead 118 .
  • the semiconductor package having such structure is manufactured with a film carrier provided with the inner leads 118 to be connected with bump electrodes 114 .
  • An example of the semiconductor chip 111 is an LCD driver chip.
  • Some LCD driver chips are provided as a semiconductor integrated circuit (IC) having a plurality of semiconductor elements, and have a shape of a rectangle, whose side having the semiconductor IC is five or more times longer than other sides thereof.
  • the semiconductor IC in the LCD driver chip includes an inputting circuit, a memory such as Random Access Memory (RAM), a logic circuit, and an output circuit, and is configured so that each element operates in cooperation with the others.
  • the logic circuit is formed with gate array, for example, and functions as a data processor.
  • the output circuit includes a latch circuit, and is provided to output signals.
  • the semiconductor chip 111 also includes a plurality of narrow-pitched bump electrodes that correspond to the input circuit and output circuit thereof. Especially for output circuit, the bump electrodes 114 are provided in a narrower-pitched array in a greater number.
  • the film carrier ( 116 , 118 ) includes a plurality of leads 118 that are held on the insulating film 116 .
  • the film carrier also has a series of device holes, each of which exposes the leads 118 as an inner lead.
  • Each of the inner leads 118 is connected to each of the bump electrodes 114 provided on the semiconductor device 112 .
  • a known TAB technology is used for the connection between the inner lead 118 and the bump electrode 114 .
  • the film carrier ( 116 , 118 ) is conveyed for each device hole, and the semiconductor device 112 is aligned with a given position of the device hole.
  • a set of the bump electrodes 114 and the inner leads 118 are bonded simultaneously with a bonding tool, using a technology such as a thermal compression bonding process.
  • the resin member 120 is formed to cover the edge of the semiconductor 112 and the inner lead 118 , including the nearby insulating film 116 .
  • An example of the insulating film 116 is a polyimide film, and the thickness thereof should be equal or less than 100 ⁇ m, for example, in a range between 70 and 80 ⁇ m.
  • the thickness of the leads 118 of insulting film 116 should be equal to or less than 30 ⁇ m, for example, in a range between 10 and 20 ⁇ m.
  • FIGS. 3A and 3B are a plan view and a cross-sectional view, respectively, of the semiconductor device 112 according to the first embodiment of the present invention, showing a structure around a bump electrode thereof.
  • FIG. 4 is a plan view of the semiconductor device 112 according to the first embodiment of the present invention, showing the structure around the bump electrode and the layout of the electrode pad and wirings provided under the bump electrode.
  • the semiconductor 112 includes a passivation film 124 ; and a bump electrode 114 for external connection.
  • the passivation film 124 is formed over the electrode pad 122 , and has an opening.
  • the bump electrode 114 is formed on the passivation film 124 , and is electrically connected to the electrode pad 122 through the opening of the passivation film 124 .
  • Parts 130 of the wirings of the uppermost layer in the semiconductor chip 111 are provided under the bump electrode 114 .
  • the passivation film 124 has an opening, which is smaller in size than the bump electrode 114 , and is provided with an under-bump metal 123 , which is connected to the electrode pad 122 through the opening thereof.
  • the bump electrode 114 is connected to the electrode pad 122 via the under-bump metal 123 .
  • the inner lead 118 which is held on the film carrier, is connected onto the bump electrode 114 by a thermal compression bonding process.
  • the under-bump metal 123 may be made of a material such as nickel, Ti/Pt, or TiW/Au.
  • the passivation film 124 may be made of a material such as oxidized film, nitride film, or polyimide. It is also possible to form a wafer coating over the passivation film 124 , using a material such as polyimide.
  • the electrode pad 122 may be made of a material such as Al, Al—Si, Al—Si—Cu, or Cu.
  • the bump electrode 118 may be made of a material such as gold, silver, copper, nickel, or solder.
  • the bumper electrode 114 may have a rectangle form, having the dimensions of 20 ⁇ m ⁇ 60 ⁇ m to 50 ⁇ m ⁇ 100 ⁇ m, for example. Distance between each bump should be equal to or greater than 10 ⁇ m, and bump pitch should be in a range from 30 to 60 ⁇ m.
  • the electrode pad 122 and the passivation film 124 are at first formed on a semiconductor substrate. Then, a barrier metal 123 , made of TiW/Au laminate structure, is formed over the electrode pad 122 and the passivation film 124 . Resist (not shown diagrammatically) is applied over the barrier metal 123 to form a resist pattern. The resist pattern is provided so as to have an opening at a given position on top of the electrode pad 122 . Subsequently, gold plating is formed, following the resist pattern made using electrolytic plating. The resist pattern is then removed and excessive barrier metal 123 is removed from the passivation film 124 by etching, using the gold-plated shapes on the electrode pad 122 as a mask.
  • TEOS tetra-ethyl-ortho-silicate, tetraethoxysilane
  • BPSG boron-phosphorus-silicate-glass
  • PSG film or SOG film may be used for the inter-layer insulating film.
  • the inter-layer insulating film can be formed with a thickness of 10000 ⁇ , using techniques such as CVD, sputtering, plasma-CVD, or coating.
  • the electrode pad 122 is formed to be smaller in size than the bump electrode 114 . Because the smaller the size of the electrode pad 122 becomes, the greater the space available for wirings gets. With that, the internal wirings 130 can be provided under the bump electrode 114 on uppermost layer of the semiconductor chip 111 . Because the internal wirings 130 are present, the passivation film 124 is kept flat. Furthermore, the flatness of the passivation film 124 is improved by arranging the internal wirings 130 regularly. Therefore, it is possible to prevent the manufacturing process from becoming complicated and the manufacturing cost from increasing, without providing a special design such as arranging dummy wirings under the bump electrode 114 .
  • strips of the internal wirings 130 are arranged in a parallel fashion; however, the shape and direction thereof may be modified accordingly, depending on a function or other limitations of the semiconductor chip.
  • FIG. 5 is a plan view of the semiconductor device according to a second embodiment of the present invention, showing a structure around a bump electrode 214 and a layout of an electrode pad 222 and wirings 230 , 232 provided under the bump electrode 214 .
  • the electrode pad 222 is not positioned directly below the bump electrode 214 , but is positioned toward the edge.
  • the wiring 230 is laid across the electrode pad 222 . Because the electrode pad 222 is positioned toward the edge, a large space under the bump electrode 214 becomes available, so that a thick power wiring 232 is formed in this space.
  • the second embodiment of the present invention by arranging a thick wiring 232 under the passivation film 224 , the flatness of the passivation film 224 is further improved.
  • FIG. 6 is a plan view of the semiconductor device according to a third embodiment of the present invention, showing a structure around a bump electrode 314 and a layout of an electrode pad 322 and wiring 330 provided under the bump electrode 314 .
  • the electrode pad 322 is not positioned directly below the bump electrode 314 , but is positioned toward the edge.
  • the wiring 330 is laid across the electrode pad 322 .
  • the example according to the third embodiment of the present invention may be used when a passivation film 324 is not required to be highly flat upon forming the bump electrode 314 .
  • the present invention is explained herein using the above preferred embodiments; however, these preferred embodiments are not intended to limit the scope of the present invention.
  • the present invention may be modified in design within the scope of the technical concepts disclosed in the appended claims.
  • a bump electrode having a shape of a circle, an ellipsoid, or a triangle may also be used.
  • the number of wiring layers does not affect the advantages of the present invention.
  • the present invention may be applied not only to the LCD driver chip, but also to other various semiconductor devices that uses a bump electrode.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

According to the present invention, a semiconductor device, having an electrode pad as a part of wirings on the uppermost layer thereof, includes a passivation film and a bump electrode for external connection. The passivation film is formed on the electrode pad, and the bump electrode is formed on the passivation film and electrically connected to the electrode pad. The electrode pad is formed so as to be smaller in size than the bump electrode, and a part of the wiring on the uppermost layer are formed under the bump electrode. In this manner, it is possible to utilize the area under the bump electrode effectively without sacrificing flatness of the passivation film. As a result, the semiconductor device and the semiconductor package can be made smaller.

Description

    CROSS REFERENCE TO RELATED APPLICATION
  • This application claims the priority of Application No. 2006-319417, filed Nov. 28, 2006 in Japan, the subject matter of which is incorporated herein by reference.
    • TECHNICAL FIELD OF THE INVENTION
  • The present invention relates to a semiconductor device having bump electrode as an external terminal, implemented with TCP (Tape Carrier Package) or COF (Chip On Film) technologies. More particularly, the present invention relates to an LCD (Liquid Crystal Display) driver package provided with a plurality of narrow-pitch bump electrodes.
    • BACKGROUND OF THE INVENTION
  • Upon assembling a product using the TCP implementation, a technology called TAB (Tape Automated Bonding) is used. On a main surface of a semiconductor chip, a bump electrode is formed as an external terminal, and the semiconductor chip is bonded to a film carrier with Inner-Lead Bonding (ILB). The film carrier has a long tape-like shape, on which repetitive wiring patterns are formed. The film carrier has device holes, each of which exposes an inner lead, and outer leads, and is automatically conveyed for each device hole. The semiconductor chip is aligned with a given position of the device hole, and the bump electrode thereof is bonded to the inner lead on the film carrier using a technology such as a thermal compression bonding process. Subsequently, the outer leads are bonded to key points on the semiconductor chip.
  • FIGS. 1A and 1B are a plan view and a cross-sectional view, respectively, of a conventional semiconductor device, showing a structure around a bump electrode thereof. A semiconductor device 12 includes a semiconductor chip 11 and an electrode pad 22. The semiconductor chip 11 further includes a plurality of wiring layers (not shown diagrammatically) that are insulated from each other with inter-layer insulating films. The electrode pad 22 is provided as a part of the wirings at the uppermost layer. A passivation film 24, having an opening, which is smaller in size than the bump electrode 14, which is to be explained hereinafter, is provided on the electrode pad 22. An under-bump metal 23 is formed on the passivation film 24, and connected to the electrode pad 22 through the opening thereof. The bump electrode 14 is connected to the electrode pad 22 via the under-bump metal 23. An inner lead 18 of a film carrier is connected to the bump electrode 14 by a thermal compression bonding process.
  • To keep the passivation film 24 flat, the electrode pad 22 is kept larger in dimension than the bump electrode 14. Therefore, the bump electrode 14 completely overlaps with the electrode pad 22.
  • Japanese Patent Number 2919488 discloses a technology related to the present invention.
  • Recently, as the miniaturization of the semiconductor chip has progressed, the electrode pad has come to occupy a large portion of the chip footprint, leading to reduced competitiveness in cost. However, it has been difficult to reduce the size of the bump electrode itself while ensuring a sufficient area for contact thereof with the inner lead.
  • In the conventional semiconductor device as shown in FIG. 1, the electrode pad 22 had to be larger in size than the bump electrode 14 to ensure the flatness of the passivation film 24. Thus, it has not been possible to utilize the area under the bump electrode 14, and, in turn, to reduce the size the semiconductor device itself.
    • OBJECTS OF THE INVENTION
  • The present invention is developed to solve the above-described problem. In other words, an object of the present invention is to provide a semiconductor device and a semiconductor package for reducing the size of the semiconductor device without sacrificing the flatness of the passivation film, by utilizing the area under the bump electrode more effectively.
  • Additional objects, advantages and novel features of the present invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
    • SUMMARY OF THE INVENTION
  • According to a first aspect of the present invention, a semiconductor device, having an electrode pad as a part of an uppermost wiring layer, includes a passivation film, which is formed on the electrode pad to have an opening therein; and a bump electrode for external connection, which is formed on the passivation film and is electrically connected to the electrode pad through the opening of the passivation film. The electrode pad is formed so as to be smaller in size than the bump electrode. A part of the uppermost wiring layer is formed under the bump electrode.
  • If there is only one wiring layer, the “uppermost wiring layer” herein means the single wiring layer itself. If there are a plurality of wiring layers, which are insulated from each other with inter-layer insulating films, the uppermost wiring layer means the wiring layer formed on the uppermost layer among those wiring layers.
  • According to a second aspect of the present invention, a semiconductor package, having the semiconductor device according to the first aspect of the present invention, is fabricated using a film carrier having a plurality of leads, which are held on an insulating film, and an end of each of the leads are connected to the bump electrode as an inner lead.
  • According to the present invention, an internal wiring can be arranged in an area where an electrode pad was conventionally formed, so that the chip size can be reduced. At the same time, the passivation film can be kept flat by certain formations of the internal wirings. Therefore, it is possible to prevent the manufacturing process from becoming complicated and the manufacturing cost from increasing, without providing a special design such as arranging dummy wirings under the bump electrode.
  • Because the passivation film is kept flat, the flatness of the bump electrode itself is improved, further improving the connection with the inner lead, which is connected with the bump electrode using a technology such as a thermal compression bonding process. Furthermore, it is possible to prevent a formation of a gap between the passivation film and the bump electrode, therefore, to reduce the risk of short circuit caused by a foreign substance getting into the gap.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1A and 1B are a plan view and a cross-sectional view, respectively, of a conventional semiconductor device, showing a structure around a bump electrode thereof;
  • FIG. 2 is a side view of a semiconductor package related to the present invention.
  • FIGS. 3A and 3B are a plan view and a cross-sectional view, respectively, of a semiconductor device according to a first embodiment of the present invention, showing a structure around a bump electrode thereof;
  • FIG. 4 is a plan view of the semiconductor device according to the first embodiment of the present invention, showing the structure around the bump electrode and the layout of the electrode pad and wirings provided under the bump electrode;
  • FIG. 5 is a plan view of the semiconductor device according to a second embodiment of the present invention, showing a structure around a bump electrode and a layout of an electrode pad and wirings provided under the bump electrode; and
  • FIG. 6 is a plan view of the semiconductor device according to a third embodiment of the present invention, showing a structure around a bump electrode and a layout of an electrode pad and wirings provided under the bump electrode.
    •  DESCRIPTIONS OF REFERENCE NUMERALS
    • 100 semiconductor package
    • 112 semiconductor device
    • 114, 214, 314 bump electrode
    • 118 inner lead
    • 116 insulating film
    • 120 resin member
    • 122, 222, 322 electrode pad
    • 123 under-bump metal
    • 124, 224, 324 passivation film
    • 130, 230, 330 internal wiring
    • 232 power wiring
    DETAILED DISCLOSURE OF THE INVENTION
  • In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part thereof, and in which is shown by way of illustration specifically preferred embodiments in which the inventions may be practiced. These preferred embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other changes may be made without departing from the spirit and scope of the present inventions. The following detailed description is, therefore, not to be taken in a limiting sense, and scope of the present invention is defined only by the appended claims.
  • FIG. 2 is a side view of a semiconductor package related to the present invention. A semiconductor package 100 includes a semiconductor device 112, a plurality of leads 118, and a resin member 120. The semiconductor device 112 is provided with a semiconductor chip 111 and electrode pads 122. The semiconductor chip 111 further includes a plurality of wiring layers that are insulated from each other with inter-layer insulating films. The electrode pads 122 are provided as a part of the wirings on the uppermost wiring layer. The leads 118 are held on an insulating film 116. The resin member 120 is provided to protect the surface of the semiconductor device 112 and the inner lead 118. The semiconductor package having such structure is manufactured with a film carrier provided with the inner leads 118 to be connected with bump electrodes 114.
  • An example of the semiconductor chip 111 is an LCD driver chip. Some LCD driver chips are provided as a semiconductor integrated circuit (IC) having a plurality of semiconductor elements, and have a shape of a rectangle, whose side having the semiconductor IC is five or more times longer than other sides thereof. The semiconductor IC in the LCD driver chip, not shown diagrammatically, includes an inputting circuit, a memory such as Random Access Memory (RAM), a logic circuit, and an output circuit, and is configured so that each element operates in cooperation with the others. The logic circuit is formed with gate array, for example, and functions as a data processor. The output circuit includes a latch circuit, and is provided to output signals. The semiconductor chip 111 also includes a plurality of narrow-pitched bump electrodes that correspond to the input circuit and output circuit thereof. Especially for output circuit, the bump electrodes 114 are provided in a narrower-pitched array in a greater number.
  • The film carrier (116, 118) includes a plurality of leads 118 that are held on the insulating film 116. The film carrier also has a series of device holes, each of which exposes the leads 118 as an inner lead. Each of the inner leads 118 is connected to each of the bump electrodes 114 provided on the semiconductor device 112. A known TAB technology is used for the connection between the inner lead 118 and the bump electrode 114. In other words, the film carrier (116, 118) is conveyed for each device hole, and the semiconductor device 112 is aligned with a given position of the device hole. Subsequently, a set of the bump electrodes 114 and the inner leads 118 are bonded simultaneously with a bonding tool, using a technology such as a thermal compression bonding process. Then, the resin member 120 is formed to cover the edge of the semiconductor 112 and the inner lead 118, including the nearby insulating film 116.
  • An example of the insulating film 116 is a polyimide film, and the thickness thereof should be equal or less than 100 μm, for example, in a range between 70 and 80 μm. The thickness of the leads 118 of insulting film 116 should be equal to or less than 30 μm, for example, in a range between 10 and 20 μm.
  • FIGS. 3A and 3B are a plan view and a cross-sectional view, respectively, of the semiconductor device 112 according to the first embodiment of the present invention, showing a structure around a bump electrode thereof. FIG. 4 is a plan view of the semiconductor device 112 according to the first embodiment of the present invention, showing the structure around the bump electrode and the layout of the electrode pad and wirings provided under the bump electrode. The semiconductor 112 includes a passivation film 124; and a bump electrode 114 for external connection. The passivation film 124 is formed over the electrode pad 122, and has an opening. The bump electrode 114 is formed on the passivation film 124, and is electrically connected to the electrode pad 122 through the opening of the passivation film 124. Parts 130 of the wirings of the uppermost layer in the semiconductor chip 111 are provided under the bump electrode 114.
  • The passivation film 124 has an opening, which is smaller in size than the bump electrode 114, and is provided with an under-bump metal 123, which is connected to the electrode pad 122 through the opening thereof. The bump electrode 114 is connected to the electrode pad 122 via the under-bump metal 123. The inner lead 118, which is held on the film carrier, is connected onto the bump electrode 114 by a thermal compression bonding process.
  • The under-bump metal 123 may be made of a material such as nickel, Ti/Pt, or TiW/Au. The passivation film 124 may be made of a material such as oxidized film, nitride film, or polyimide. It is also possible to form a wafer coating over the passivation film 124, using a material such as polyimide. The electrode pad 122 may be made of a material such as Al, Al—Si, Al—Si—Cu, or Cu.
  • The bump electrode 118 may be made of a material such as gold, silver, copper, nickel, or solder. The bumper electrode 114 may have a rectangle form, having the dimensions of 20 μm×60 μm to 50 μm×100 μm, for example. Distance between each bump should be equal to or greater than 10 μm, and bump pitch should be in a range from 30 to 60 μm.
  • To manufacture the bump electrode 114 made of gold, for example, the electrode pad 122 and the passivation film 124 are at first formed on a semiconductor substrate. Then, a barrier metal 123, made of TiW/Au laminate structure, is formed over the electrode pad 122 and the passivation film 124. Resist (not shown diagrammatically) is applied over the barrier metal 123 to form a resist pattern. The resist pattern is provided so as to have an opening at a given position on top of the electrode pad 122. Subsequently, gold plating is formed, following the resist pattern made using electrolytic plating. The resist pattern is then removed and excessive barrier metal 123 is removed from the passivation film 124 by etching, using the gold-plated shapes on the electrode pad 122 as a mask.
  • For embedding and flattening the multi-layer wiring of the semiconductor chip 111, TEOS (tetra-ethyl-ortho-silicate, tetraethoxysilane) film, or BPSG (boron-phosphorus-silicate-glass) film, PSG film or SOG film may be used for the inter-layer insulating film. The inter-layer insulating film can be formed with a thickness of 10000 Å, using techniques such as CVD, sputtering, plasma-CVD, or coating.
  • According to the first embodiment of the present invention, the electrode pad 122 is formed to be smaller in size than the bump electrode 114. Because the smaller the size of the electrode pad 122 becomes, the greater the space available for wirings gets. With that, the internal wirings 130 can be provided under the bump electrode 114 on uppermost layer of the semiconductor chip 111. Because the internal wirings 130 are present, the passivation film 124 is kept flat. Furthermore, the flatness of the passivation film 124 is improved by arranging the internal wirings 130 regularly. Therefore, it is possible to prevent the manufacturing process from becoming complicated and the manufacturing cost from increasing, without providing a special design such as arranging dummy wirings under the bump electrode 114.
  • According to the first embodiment of the present invention, strips of the internal wirings 130 are arranged in a parallel fashion; however, the shape and direction thereof may be modified accordingly, depending on a function or other limitations of the semiconductor chip.
  • FIG. 5 is a plan view of the semiconductor device according to a second embodiment of the present invention, showing a structure around a bump electrode 214 and a layout of an electrode pad 222 and wirings 230, 232 provided under the bump electrode 214. According to the second embodiment of the present invention, the electrode pad 222 is not positioned directly below the bump electrode 214, but is positioned toward the edge. The wiring 230 is laid across the electrode pad 222. Because the electrode pad 222 is positioned toward the edge, a large space under the bump electrode 214 becomes available, so that a thick power wiring 232 is formed in this space. According to the second embodiment of the present invention, by arranging a thick wiring 232 under the passivation film 224, the flatness of the passivation film 224 is further improved.
  • FIG. 6 is a plan view of the semiconductor device according to a third embodiment of the present invention, showing a structure around a bump electrode 314 and a layout of an electrode pad 322 and wiring 330 provided under the bump electrode 314. In this embodiment of the present invention, the electrode pad 322 is not positioned directly below the bump electrode 314, but is positioned toward the edge. The wiring 330 is laid across the electrode pad 322. The example according to the third embodiment of the present invention may be used when a passivation film 324 is not required to be highly flat upon forming the bump electrode 314.
  • The present invention is explained herein using the above preferred embodiments; however, these preferred embodiments are not intended to limit the scope of the present invention. The present invention may be modified in design within the scope of the technical concepts disclosed in the appended claims. For example, instead of the rectangle electrode, a bump electrode having a shape of a circle, an ellipsoid, or a triangle may also be used. The number of wiring layers does not affect the advantages of the present invention. Furthermore, the present invention may be applied not only to the LCD driver chip, but also to other various semiconductor devices that uses a bump electrode.

Claims (8)

1. A semiconductor device, having an electrode pad as a part of an uppermost wiring layer, comprising:
a passivation film, which is formed on the electrode pad to have an opening therein; and
a bump electrode for external connection, which is formed on the passivation film and is electrically connected to the electrode pad through the opening of the passivation film, wherein
the electrode pad is formed so as to be smaller in size than the bump electrode; and
a part of the uppermost wiring layer is formed under the bump electrode.
2. The semiconductor device according to claim 1, wherein
the semiconductor device is a LCD driver chip.
3. The semiconductor device according to claim 1, wherein
the part of the uppermost wiring layer formed under the bump electrode is a power wiring.
4. The semiconductor device according to claim 2, wherein
the part of the uppermost wiring layer formed under the bump electrode is a power wiring.
5. A semiconductor package, having the semiconductor device according to claim 1, wherein
the semiconductor package is fabricated using a film carrier having a plurality of leads, which are held on an insulating film, and an end of each of the leads are connected to the bump electrode as an inner lead.
6. The semiconductor package according to claim 5, wherein
the inner lead and the bump electrode are connected by a thermal compression bonding process.
7. The semiconductor package according to claim 5 further comprising:
a resin member which protects the semiconductor device and the inner lead.
8. The semiconductor package according to claim 6 further comprising:
a resin member which protects the semiconductor device and the inner lead.
US11/939,734 2006-11-28 2007-11-14 Semiconductor device and semiconductor package containing the same Abandoned US20080122082A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/164,298 US9196580B2 (en) 2006-11-28 2014-01-27 Semiconductor device and semiconductor package containing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006319417A JP4293563B2 (en) 2006-11-28 2006-11-28 Semiconductor device and semiconductor package
JP2006-319417 2006-11-28

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US14/164,298 Division US9196580B2 (en) 2006-11-28 2014-01-27 Semiconductor device and semiconductor package containing the same

Publications (1)

Publication Number Publication Date
US20080122082A1 true US20080122082A1 (en) 2008-05-29

Family

ID=39462817

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/939,734 Abandoned US20080122082A1 (en) 2006-11-28 2007-11-14 Semiconductor device and semiconductor package containing the same
US14/164,298 Active US9196580B2 (en) 2006-11-28 2014-01-27 Semiconductor device and semiconductor package containing the same

Family Applications After (1)

Application Number Title Priority Date Filing Date
US14/164,298 Active US9196580B2 (en) 2006-11-28 2014-01-27 Semiconductor device and semiconductor package containing the same

Country Status (3)

Country Link
US (2) US20080122082A1 (en)
JP (1) JP4293563B2 (en)
CN (1) CN101192581B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110156248A1 (en) * 2009-12-25 2011-06-30 Fujitsu Semiconductor Limited Semiconductor device and method for manufacturing the same
CN110828392A (en) * 2018-08-07 2020-02-21 三星电子株式会社 Semiconductor device and semiconductor package including the same

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8508043B2 (en) * 2011-11-16 2013-08-13 International Business Machines Corporation Metal pad structure for thickness enhancement of polymer used in electrical interconnection of semiconductor die to semiconductor chip package substrate with solder bump
JP6054612B2 (en) 2012-03-06 2016-12-27 ラピスセミコンダクタ株式会社 Semiconductor integrated device
CN106449575B (en) * 2015-08-07 2020-07-24 晶宏半导体股份有限公司 Bump structure of semiconductor device
KR102843099B1 (en) * 2019-07-12 2025-08-06 삼성디스플레이 주식회사 Display device and method of manufacturing for display device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5744859A (en) * 1995-02-28 1998-04-28 Texas Instruments Incorporated Semiconductor device
US5989940A (en) * 1994-05-26 1999-11-23 Nec Corporation Semiconductor device capable of accomplishing a high moisture proof
US6084291A (en) * 1997-05-26 2000-07-04 Seiko Epson Corporation Tape carrier for TAB, integrated circuit device, a method of making the same, and an electronic device
US6118180A (en) * 1997-11-03 2000-09-12 Lsi Logic Corporation Semiconductor die metal layout for flip chip packaging
US20060057834A1 (en) * 2002-11-15 2006-03-16 Sharp Kabushiki Kaisha Semiconductor device and fabrication process thereof

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63318742A (en) 1987-06-22 1988-12-27 Hitachi Ltd Semiconductor integrated circuit device and its manufacturing method
US5220199A (en) * 1988-09-13 1993-06-15 Hitachi, Ltd. Semiconductor integrated circuit device in which a semiconductor chip is mounted with solder bumps for mounting to a wiring substrate
JP2919488B2 (en) 1989-07-05 1999-07-12 株式会社日立製作所 Semiconductor integrated circuit device
JP2002198374A (en) 2000-10-16 2002-07-12 Sharp Corp Semiconductor device and method of manufacturing the same
JP2006041328A (en) 2004-07-29 2006-02-09 Seiko Epson Corp Semiconductor device and manufacturing method thereof, package for LCD driver

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5989940A (en) * 1994-05-26 1999-11-23 Nec Corporation Semiconductor device capable of accomplishing a high moisture proof
US5744859A (en) * 1995-02-28 1998-04-28 Texas Instruments Incorporated Semiconductor device
US6084291A (en) * 1997-05-26 2000-07-04 Seiko Epson Corporation Tape carrier for TAB, integrated circuit device, a method of making the same, and an electronic device
US6118180A (en) * 1997-11-03 2000-09-12 Lsi Logic Corporation Semiconductor die metal layout for flip chip packaging
US20060057834A1 (en) * 2002-11-15 2006-03-16 Sharp Kabushiki Kaisha Semiconductor device and fabrication process thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110156248A1 (en) * 2009-12-25 2011-06-30 Fujitsu Semiconductor Limited Semiconductor device and method for manufacturing the same
US8952538B2 (en) 2009-12-25 2015-02-10 Fujitsu Semiconductor Limited Semiconductor device and method for manufacturing the same
US9893029B2 (en) 2009-12-25 2018-02-13 Socionext Inc. Semiconductor device and method for manufacturing the same
US11004817B2 (en) 2009-12-25 2021-05-11 Socionext Inc. Semiconductor device and method for manufacturing the same
CN110828392A (en) * 2018-08-07 2020-02-21 三星电子株式会社 Semiconductor device and semiconductor package including the same
US11158589B2 (en) * 2018-08-07 2021-10-26 Samsung Electronics Co., Ltd Semiconductor device and semiconductor package comprising the same

Also Published As

Publication number Publication date
CN101192581B (en) 2012-07-04
US9196580B2 (en) 2015-11-24
JP4293563B2 (en) 2009-07-08
US20140138820A1 (en) 2014-05-22
JP2008135486A (en) 2008-06-12
CN101192581A (en) 2008-06-04

Similar Documents

Publication Publication Date Title
US10957719B2 (en) Semiconductor device and a method of manufacturing the same
JP4094656B2 (en) Semiconductor device
US9196580B2 (en) Semiconductor device and semiconductor package containing the same
US7538442B2 (en) Semiconductor chip and semiconductor device
JP4357862B2 (en) Semiconductor device
JP4585564B2 (en) Semiconductor device
JP5259674B2 (en) Semiconductor device
JP2007311633A (en) Semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
AS Assignment

Owner name: OKI ELECTRIC INDUSTRY CO., LTD., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YAMAMOTO, HIROSHI;TAKEICHI, EIJI;REEL/FRAME:020115/0546;SIGNING DATES FROM 20071029 TO 20071031

AS Assignment

Owner name: OKI SEMICONDUCTOR CO., LTD., JAPAN

Free format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;REEL/FRAME:022162/0669

Effective date: 20081001

Owner name: OKI SEMICONDUCTOR CO., LTD.,JAPAN

Free format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;REEL/FRAME:022162/0669

Effective date: 20081001

AS Assignment

Owner name: LAPIS SEMICONDUCTOR CO., LTD., JAPAN

Free format text: CHANGE OF NAME;ASSIGNOR:OKI SEMICONDUCTOR CO., LTD;REEL/FRAME:032495/0483

Effective date: 20111003

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION