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US20070256761A1 - Alloy compositions and techniques for reducing intermetallic compound thickness and oxidation of metals and alloys - Google Patents

Alloy compositions and techniques for reducing intermetallic compound thickness and oxidation of metals and alloys Download PDF

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Publication number
US20070256761A1
US20070256761A1 US11/745,784 US74578407A US2007256761A1 US 20070256761 A1 US20070256761 A1 US 20070256761A1 US 74578407 A US74578407 A US 74578407A US 2007256761 A1 US2007256761 A1 US 2007256761A1
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Prior art keywords
alloy
indium
metal
weight
germanium
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US11/745,784
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Hong-Sik Hwang
Ning-Cheng Lee
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Indium Corp of America Inc
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Indium Corp of America Inc
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Priority to US11/745,784 priority Critical patent/US20070256761A1/en
Assigned to INDIUM CORPORATION OF AMERICA reassignment INDIUM CORPORATION OF AMERICA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HWANG, HONG-SIK, LEE, NING-CHENG
Publication of US20070256761A1 publication Critical patent/US20070256761A1/en
Priority to US13/099,135 priority patent/US20110273847A1/en
Abandoned legal-status Critical Current

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    • CCHEMISTRY; METALLURGY
    • C22METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22CALLOYS
    • C22C28/00Alloys based on a metal not provided for in groups C22C5/00 - C22C27/00
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24Selection of soldering or welding materials proper
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    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3733Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon having a heterogeneous or anisotropic structure, e.g. powder or fibres in a matrix, wire mesh, porous structures
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Definitions

  • the present disclosure relates generally to electrical and thermal conduction and, more particularly, alloy compositions and techniques for reducing intermetallic compound (IMC) thickness and oxidation of metals and alloys.
  • IMC intermetallic compound
  • solder joints should give sufficient reliability during service.
  • Solder joint reliability largely relies on IMC growth that is caused by time and heat generated during service.
  • thicker IMC causes reliability problems due to brittleness of IMC, formation of Kirkendall voiding, and/or depletion of metal layer(s) upon which solder is applied, especially, when the metal layer(s) is thin such as in under bump metallization (UBM).
  • UBM under bump metallization
  • TIM thermal interface materials
  • thermal solders are very attractive because they have high thermal conductivities.
  • Soldered TIM's have similar problems as solder joints in that IMC growth causing reliability problems may occur as devices run at elevated temperatures.
  • Low melting point metals including liquid metals, are also useful as thermally conductive materials due to good conformity of the low melting point metals with contacting surfaces, good metallic phase continuity of the low melting point metals at service temperatures, and the formation of good thermally conductive pathways or chains of the low melting point metals at service temperatures.
  • the use of low melting point metals is limited in some specific applications due to rapid oxidation and high reactivity.
  • TIM's such as polymer solder hybrids (PSH)
  • PSH polymer solder hybrids
  • a polymer matrix acts as an adhesive on a surface of a die or package and solder filler serves as a thermal conductor.
  • low melting point metals have been attempted as thermal conductive fillers or as a part of conductive fillers in PSH's.
  • low melting point metals including liquid metals, oxidize very quickly and form loosely aggregated solids, which easily delaminate at interfaces. As a result, using this type of TIM is very challenging.
  • the alloy compositions may be realized as a composition of alloy or mixture consisting essentially of from about 90% to about 99.999% by weight indium and from about 0.001% to about 10% by weight germanium and unavoidable impurities.
  • the alloy compositions may be realized as a composition of alloy or mixture consisting essentially of from about 90% to about 99.999% by weight indium and from about 0.001% to about 10% by weight of one or more of germanium, manganese, phosphorus, and titanium.
  • the alloy compositions may be realized as a composition of alloy consisting essentially of from about 90% to about 99.999% by weight gallium and from about 0.001% to about 10% by weight germanium and unavoidable impurities.
  • the alloy compositions may be realized as a composition of alloy consisting essentially of from about 90% to about 99.999% by weight gallium and from about 0.001% to about 10% by weight of one or more of germanium, manganese, phosphorus, and titanium.
  • the alloy compositions may be realized as a composition of alloy consisting essentially of gallium-indium alloy, gallium-indium-tin alloy, gallium-indium-tin-zinc alloy, cadmium, cadmium alloys, indium-lead alloy, indium-lead-silver alloy, mercury, mercury alloys, bismuth-tin alloy, indium-tin-bismuth alloy, and mixtures thereof containing from about 0.001% to about 10% by weight of one or more of germanium, manganese, phosphorus, and titanium and unavoidable impurities.
  • the alloy compositions may take the form of a metallurgical interconnect material, a thermal interface material, a thermally conductive filler, or a thermally conductive medium.
  • the thermal interface material may comprise one or more of a phase change material, a thermally conductive gel, a thermally conductive tape, and a thermal grease.
  • the techniques may be realized as a method of incorporating from about 0.001% to about 10% by weight of one or more dopants including one or more of germanium, manganese, phosphorus, and titanium in a metal or metal alloy comprising from about 90% to about 99.999% by weight gallium or indium, wherein the method comprises mixing the one or more dopants into the metal or metal alloy as a solution with heat. The mixture may be quickly cooled to get finer dopant or intermetallic particles that diffuse faster than larger particles.
  • the techniques may be realized as a method of incorporating from about 0.001% to about 10% by weight of one or more dopants including one or more of germanium, manganese, phosphorus, and titanium in a metal or metal alloy comprising from about 90% to about 99.999% by weight gallium or indium, wherein the method comprises mixing the one or more dopants as particulates into a molten metal or metal alloy, and cooling the molten metal or metal alloy with the one or more dopant particulates to form a metal or metal alloy composite.
  • the techniques may be realized as a method of incorporating from about 0.001% to about 10% by weight of one or more dopants including one or more of germanium, manganese, phosphorus, and titanium in a metal or metal alloy comprising from about 90% to about 99.999% by weight gallium or indium, wherein the method comprises mixing the one or more dopants into a solid form of the metal or metal alloy by mechanical force.
  • the techniques may be realized as a method of incorporating from about 0.001% to about 10% by weight of one or more dopants including one or more of germanium, manganese, phosphorus, and titanium in a metal or metal alloy comprising from about 90% to about 99.999% by weight gallium or indium, wherein the method comprises mixing the one or more dopants as particulates into a metal or metal alloy powder to form a metal or metal alloy powder mixture.
  • the techniques may be realized as a method of incorporating from about 0.001% to about 10% by weight of one or more dopants including one or more of germanium, manganese, phosphorus, and titanium in a metal or metal alloy comprising from about 90% to about 99.999% by weight gallium or indium, wherein the method comprises putting the one or more dopants as particulates in an interconnecting substrate with the metal or metal alloy, wherein the interconnecting substrate may include at least one of a pad on circuit board, a heat spreader, a heat sink, and a back side of component.
  • FIG. 1 is a table of IMC thickness and Nickel (Ni) layer consumption of aged pure Indium (In) and 2% Germanium (Ge)/Indium (In) samples in accordance with an embodiment of the present disclosure.
  • FIG. 2 shows a scanning electron microscopy (SEM) picture, magnified ⁇ 1000, of a pure Indium (In) sample on a Nickel (Ni)/Gold (Au) substrate aged for 1000 hrs at 150° C. in accordance with an embodiment of the present disclosure.
  • SEM scanning electron microscopy
  • FIG. 3 shows a scanning electron microscopy (SEM) picture, magnified ⁇ 1000, of a 2% Germanium (Ge)/Indium (In) sample on a Nickel (Ni)/Gold (Au) substrate aged for 1000 hrs at 150° C. in accordance with an embodiment of the present disclosure.
  • FIG. 4 shows a scanning electron microscopy (SEM) picture, magnified ⁇ 3000, of a 2% Germanium (Ge)/Indium (In) sample on a Nickel (Ni)/Gold (Au) substrate aged for 1000 hrs at 150° C. in accordance with an embodiment of the present disclosure.
  • FIG. 5 is a table of IMC compositions of aged pure Indium (In) and 2% Germanium (Ge)/Indium (In) samples in accordance with an embodiment of the present disclosure.
  • FIG. 6 shows a graph of oxide formed in a 85° C./85% relative humidity chamber for pure Gallium (Ga) and 0.05% and 0.1% Germanium (Ge)-doped Gallium (Ga) in accordance with an embodiment of the present disclosure.
  • FIG. 7 shows a graph of oxide formed in a 85° C./85% relative humidity chamber for 0.5%, 1%, 2%, and 5% Germanium (Ge)-doped Gallium (Ga) in accordance with an embodiment of the present disclosure.
  • FIG. 8 shows a graph of oxide formed in a 85° C./85% relative humidity chamber for 0.0001% and 0.0005% Germanium (Ge)-doped Gallium (Ga) in accordance with an embodiment of the present disclosure.
  • FIG. 9 shows a graph of oxide formed in a 85° C./85% relative humidity chamber for Gallium (Ga)/Indium (In) alloys with and without 0.5% Germanium (Ge) in accordance with an embodiment of the present disclosure.
  • FIG. 10 shows a graph of oxide formed in a 85° C./85% relative humidity chamber for Indium (In)/Bismuth (Bi) alloys with and without 0.5% Germanium (Ge) in accordance with an embodiment of the present disclosure.
  • FIG. 11 shows a graph of oxide formed in a 85° C./85% relative humidity chamber for Gallium (Ga) alloys containing 0.5% Phosphorus (P), 0.5% Titanium (Ti), 0.5% Manganese (Mn), and no dopants in accordance with an embodiment of the present disclosure.
  • FIG. 12 is a table of relative peak intensity of Germanium (Ge) to Gallium (Ga) with different laser power for 2% Germanium (Ge)/Gallium (Ga) in accordance with an embodiment of the present disclosure.
  • FIG. 13 shows a graph of ICP-MS spectrum of 2% Germanium (Ge)/Gallium (Ga) for 15% laser power in accordance with an embodiment of the present disclosure.
  • FIG. 14 shows a graph of ICP-MS spectrum of 2% Germanium (Ge)/Gallium (Ga) for 25% laser power in accordance with an embodiment of the present disclosure.
  • FIG. 15 shows a mounting configuration wherein a metallurgical bond is formed between a pad of an electronic component and a pad of a substrate through an interconnecting material, such as solder, in accordance with an embodiment of the present disclosure.
  • FIG. 16 shows an application of a TIM in an electronic assembly in accordance with an embodiment of the present disclosure.
  • FIG. 17 shows a simplified example of a first TIM in the form of a phase change material, a thermally conductive gel, a thermally conductive tape, or a thermal grease that comprises a polymeric matrix filled with a thermally conductive filler between an IHS and an electronic component in accordance with an embodiment of the present disclosure.
  • FIG. 18 shows an example wherein a first TIM is a PSH where a thermally conductive filler stays as a liquid at service temperature and a polymeric matrix gives mechanical adhesion between an IHS and an electronic component in accordance with an embodiment of the present disclosure.
  • FIG. 19 shows an example wherein TIM material may be placed directly between an IHS and an electronic component without a polymeric matrix in accordance with an embodiment of the present disclosure.
  • Alloy compositions and techniques for reducing IMC thickness and oxidation of metals and alloys in accordance with embodiments of the present disclosure are described. Such alloy compositions and techniques were discovered through experimental testing. For example, in order to solve problems of solder joint reliability, an IMC growth test was used to reveal a technique for preventing IMC growth of interconnect material such as solder and TIM in accordance with an embodiment of the present disclosure. That is, significant, unprecedented effects were observed when IMC growths of 2% (wt) Germanium (Ge)/Indium (In) and pure Indium (In) on an electrolytic Nickel (Ni)/Gold (Au) substrate after aging in a 150° C. oven for 1000 hours.
  • IMC thickness and Nickel (Ni) layer consumption of samples were measured after aging the samples.
  • total IMC thickness of pure Indium (In) was about 18.8-19.6 microns while the IMC thickness of 2% Germanium (Ge)/Indium (In) was about 2.0-3.4 microns.
  • the original thickness of Nickel (Ni) layer of the substrate was 5.3 microns and the Nickel (Ni) layer consumption of samples with pure Indium (In) and 2% Germanium (Ge)/Indium (In) were determined as 45.3-49.1% and 3.8-7.5%, respectively.
  • FIG. 2 and 3 show scanning electron microscopy (SEM) pictures of a pure Indium (In) sample and a 2% Germanium (Ge)/Indium (In) sample, respectively, on an electrolytic Nickel (Ni)/Gold (Au) substrate after aging in a 150° C. oven for 1000 hours.
  • SEM scanning electron microscopy
  • EDS energy dispersive spectrometry
  • the composition of the IMC in the pure Indium (In) sample was determined to be (Ni, Au) 28 In 72
  • the composition of the first IMC layer (i.e., closest to solder) of the 2% Germanium (Ge)/Indium (In) sample was determined to be 54% Indium (In), 32% Nickel (Ni), 13% Germanium (Ge), and 1% Gold (Au).
  • the actual composition of the first IMC layer of the 2% Germanium (Ge)/Indium (In) sample may not be precisely accurate because the first IMC layer of the 2% Germanium (Ge)/Indium (In) sample was thinner than the measurement resolution.
  • materials in areas other than the first IMC layer of the 2% Germanium (Ge)/Indium (In) sample may be included in the composition of the first IMC layer of the 2% Germanium (Ge)/Indium (In) sample.
  • the second IMC layer of the 2% Germanium (Ge)/Indium (In) sample was thicker than the first IMC layer of the 2% Germanium (Ge)/Indium (In) sample and thus it was possible to determine the exact composition of the second IMC layer of the 2% Germanium (Ge)/Indium (In) sample as (Ni, In, Au) 50 Ge 50 .
  • the composition of third IMC layer of the 2% Germanium (Ge)/Indium (In) sample was same as the composition of the IMC in the pure Indium (In) sample.
  • Germanium (Ge) reacts with Nickel (Ni) in the early stages of aging to form Germanium (Ge)-rich IMC layers and that these Germanium (Ge)-rich IMC layers protect the Nickel (Ni) layer from reaction with solder. It is also believed that when a certain IMC layer forms a dense and stable layer that can block inter-diffusion between solder and a substrate material, thinner total IMC and less consumption of the substrate material such as for UBM is observed. Thus, it is further believed that formation of such a protective IMC layer results in better reliability. From the discussion above, it may be concluded that the thin layer(s) of Germanium (Ge)-rich IMC plays a role as diffusion barrier to slow down solder diffusion to substrate.
  • the amount of oxide was determined by measuring the height of the oxide part (volume) formed on top of the metals.
  • the amount of oxide for the pure Gallium (Ga) sample increased rapidly and showed about 90% oxide in 10 days.
  • the samples of Gallium (Ga) containing small amounts of Germanium (Ge) showed much slower oxidation rates. Indeed, the 99.95% Gallium (Ga)/0.05% Germanium (Ge) and 99.9% Gallium (Ga)/0.1% Germanium (Ge) samples didn't show a significant amount of oxide until after 80 days in the 85° C./85% relative humidity chamber (see FIG. 6 ).
  • Germanium (Ge) 0.0001% Germanium (Ge)/Gallium (Ga) and 0.0005% Germanium (Ge)/Gallium (Ga) were tested. As shown in FIG. 8 , only a slight effect was observed for these alloys.
  • Gallium (Ga)/Indium (In) is a eutectic alloy and thus may also be a good thermal interface material.
  • the anti-oxidation effect of Germanium (Ge) on such an alloy would therefore be of interest in view of the above findings. Therefore, the oxidation rate of a 78.6% Gallium (Ga)/21.4% Indium (In) alloy was compared with a 0.5% Germanium (Ge)/78.2% Gallium (Ga)/21.3% Indium (In) alloy.
  • the Germanium (Ge)-containing Gallium (Ga)/Indium (In) alloy showed a much more stable oxidation property.
  • Bismuth (Bi)/Indium (In) is also a eutectic alloy and thus may also be a good thermal interface material.
  • the anti-oxidation effect of Germanium (Ge) on such an alloy would therefore be of interest in view of the above findings. Therefore, the oxidation rate of a 66.7% Indium (In)/33.3% Bismuth (Bi) alloy was compared with a 0.5% Germanium (Ge)/66.4% Indium (In)/33.1% Bismuth (Bi) alloy.
  • FIG. 10 only a slight anti-oxidation effect was observed for the Germanium (Ge)-containing Indium (In)/Bismuth (Bi) alloy.
  • the anti-oxidation effect of other dopants on Gallium (Ga) would be of interest in view of the above findings. Therefore, the oxidation rate of 0.5% Phosphorus (P)/Gallium (Ga), 0.5% Titanium (Ti)/Gallium (Ga), and 0.5% Manganese (Mn)/Gallium (Ga) were compared with pure Gallium (Ga). As shown in FIG. 11 , some anti-oxidation effect was observed for the Phosphorus (P), Titanium (Ti), and Manganese (Mn)-doped Gallium (Ga), but not as much as Germanium (Ge)-doped Gallium (Ga).
  • Germanium (Ge) to protect Gallium (Ga) from oxidation was investigated. It was assumed that a thin Germanium (Ge)-containing protective layer was formed and that this layer protected further reaction of Gallium (Ga) with oxygen.
  • a laser ablation ICP-MS method was used to verify this mechanism.
  • the laser ablation ICP-MS method is widely used for surface composition analysis. During this method a high energy laser ablates a small area of the surface of a sample. The ablated material is then transferred into an ICP-MS analysis chamber. The higher the laser intensity, the deeper the ablation.
  • FIG. 15 there is shown a mounting configuration wherein a metallurgical bond is formed between a pad 2 of an electronic component 1 and a pad 4 of a substrate 5 through an interconnecting material 3 , such as solder, in accordance with an embodiment of the present disclosure.
  • IMC layers build up between the solder interconnecting material 3 and the component pad 2 and/or the substrate pad 4 .
  • the compositions described herein may reduce IMC growth between the solder interconnecting material 3 and the component pad 2 and/or the substrate pad 4 to increase reliability of the electronic component 1 .
  • the electronic assembly comprises a substrate 5 connected to an electronic component 1 through interconnecting material 10 .
  • An integrated heat spreader (IHS) 8 is attached to a top side of the electronic component 1 using a first TIM 9 to dissipate heat generated from the electronic component 1 .
  • the IHS 8 is also connected to a heat sink 6 by a second TIM 7 for further dissipation of heat.
  • One of the most effective materials for the first TIM 9 and the second TIM 7 is a thermal solder such as indium, indium alloys, gallium-indium alloy, gallium-indium-tin alloy, gallium-indium-tin-zinc alloy, indium-lead alloy, indium-lead-silver alloy, bismuth-tin alloy, and indium-tin-bismuth alloy.
  • the compositions described herein may reduce IMC growth between the electronic component 1 and the IHS 8 and/or between the IHS 8 and the heat sink 6 to increase reliability.
  • the first TIM 9 in the form of a phase change material, a thermally conductive gel, a thermally conductive tape, or a thermal grease that comprises a polymeric matrix 12 filled with a thermally conductive filler 11 between the IHS 8 and the electronic component 1 in accordance with an embodiment of the present disclosure.
  • the conductive filler 11 may include indium, indium alloys, gallium, gallium-indium alloy, gallium-indium-tin alloy, gallium-indium-tin-zinc alloy, cadmium, cadmium alloys, indium-lead alloy, indium-lead-silver alloy, mercury, mercury alloys, bismuth-tin alloy, and indium-tin-bismuth alloy.
  • the compositions described herein may improve oxidation properties and reduce reactivity of the thermally conductive filler 11 .
  • the first TIM 9 is a PSH where a thermally conductive filler 13 stays as a liquid at service temperature and the polymeric matrix 12 gives mechanical adhesion between the IHS 8 and the electronic component 1 in accordance with an embodiment of the present disclosure.
  • the thermally conductive filler 13 may include indium, gallium, gallium-indium alloy, gallium-indium-tin alloy, gallium-indium-tin-zinc alloy, cadmium, cadmium alloys, indium-lead alloy, indium-lead-silver alloy, mercury, mercury alloys, bismuth-tin alloy, and indium-tin-bismuth alloy.
  • the compositions described herein may improve oxidation properties and reduce reactivity of the thermally conductive filler 13 .
  • TIM material 15 may be placed directly between the IHS 8 and the electronic component 1 without the polymeric matrix 12 in accordance with an embodiment of the present disclosure.
  • the TIM material 15 may be liquid metal such as gallium or low melting point metals or alloys.
  • a confiner 14 may be used to prevent the TIM material 15 in liquid form from leaking out from between the IHS 8 and the electronic component 1 .
  • the compositions described herein may improve oxidation properties and reduce reactivity of the TIM material 15 .

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Abstract

Alloy compositions and techniques for reducing IMC thickness and oxidation of metals and alloys are disclosed. In one particular exemplary embodiment, the alloy compositions may be realized as a composition of alloy or mixture consisting essentially of from about 90% to about 99.999% by weight indium and from about 0.001% to about 10% by weight germanium and unavoidable impurities. In another particular exemplary embodiment, the alloy compositions may be realized as a composition of alloy consisting essentially of from about 90% to about 99.999% by weight gallium and from about 0.001% to about 10% by weight germanium and unavoidable impurities.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This patent application claims priority to U.S. Provisional Patent Application No. 60/746,710, filed May 8, 2006, which is hereby incorporated by reference herein in its entirety.
  • FIELD OF THE DISCLOSURE
  • The present disclosure relates generally to electrical and thermal conduction and, more particularly, alloy compositions and techniques for reducing intermetallic compound (IMC) thickness and oxidation of metals and alloys.
  • BACKGROUND OF THE DISCLOSURE
  • When working with electronic devices, solder joints should give sufficient reliability during service. Solder joint reliability largely relies on IMC growth that is caused by time and heat generated during service. In general, thicker IMC causes reliability problems due to brittleness of IMC, formation of Kirkendall voiding, and/or depletion of metal layer(s) upon which solder is applied, especially, when the metal layer(s) is thin such as in under bump metallization (UBM).
  • On the other hand, the development of new thermal interface materials (TIM's) is required to address increases in device processing speeds and heat generation. Thermal solders are very attractive because they have high thermal conductivities. Soldered TIM's have similar problems as solder joints in that IMC growth causing reliability problems may occur as devices run at elevated temperatures.
  • Low melting point metals, including liquid metals, are also useful as thermally conductive materials due to good conformity of the low melting point metals with contacting surfaces, good metallic phase continuity of the low melting point metals at service temperatures, and the formation of good thermally conductive pathways or chains of the low melting point metals at service temperatures. The use of low melting point metals, however, is limited in some specific applications due to rapid oxidation and high reactivity.
  • New types of TIM's, such as polymer solder hybrids (PSH), have been recently introduced wherein a polymer matrix acts as an adhesive on a surface of a die or package and solder filler serves as a thermal conductor. Several possible applications of low melting point metals have been attempted as thermal conductive fillers or as a part of conductive fillers in PSH's. However, low melting point metals, including liquid metals, oxidize very quickly and form loosely aggregated solids, which easily delaminate at interfaces. As a result, using this type of TIM is very challenging.
  • In view of the foregoing, it would be desirable to provide techniques for reducing IMC thickness and oxidation of metals and alloys which overcome the above-described inadequacies and shortcomings.
  • SUMMARY OF THE DISCLOSURE
  • Alloy compositions and techniques for reducing IMC thickness and oxidation of metals and alloys are disclosed. In one particular exemplary embodiment, the alloy compositions may be realized as a composition of alloy or mixture consisting essentially of from about 90% to about 99.999% by weight indium and from about 0.001% to about 10% by weight germanium and unavoidable impurities. In another particular exemplary embodiment, the alloy compositions may be realized as a composition of alloy or mixture consisting essentially of from about 90% to about 99.999% by weight indium and from about 0.001% to about 10% by weight of one or more of germanium, manganese, phosphorus, and titanium. In yet another particular exemplary embodiment, the alloy compositions may be realized as a composition of alloy consisting essentially of from about 90% to about 99.999% by weight gallium and from about 0.001% to about 10% by weight germanium and unavoidable impurities. In still another particular exemplary embodiment, the alloy compositions may be realized as a composition of alloy consisting essentially of from about 90% to about 99.999% by weight gallium and from about 0.001% to about 10% by weight of one or more of germanium, manganese, phosphorus, and titanium. In still yet another particular exemplary embodiment, the alloy compositions may be realized as a composition of alloy consisting essentially of gallium-indium alloy, gallium-indium-tin alloy, gallium-indium-tin-zinc alloy, cadmium, cadmium alloys, indium-lead alloy, indium-lead-silver alloy, mercury, mercury alloys, bismuth-tin alloy, indium-tin-bismuth alloy, and mixtures thereof containing from about 0.001% to about 10% by weight of one or more of germanium, manganese, phosphorus, and titanium and unavoidable impurities.
  • The alloy compositions may take the form of a metallurgical interconnect material, a thermal interface material, a thermally conductive filler, or a thermally conductive medium. The thermal interface material may comprise one or more of a phase change material, a thermally conductive gel, a thermally conductive tape, and a thermal grease.
  • In one particular exemplary embodiment, the techniques may be realized as a method of incorporating from about 0.001% to about 10% by weight of one or more dopants including one or more of germanium, manganese, phosphorus, and titanium in a metal or metal alloy comprising from about 90% to about 99.999% by weight gallium or indium, wherein the method comprises mixing the one or more dopants into the metal or metal alloy as a solution with heat. The mixture may be quickly cooled to get finer dopant or intermetallic particles that diffuse faster than larger particles.
  • In another particular exemplary embodiment, the techniques may be realized as a method of incorporating from about 0.001% to about 10% by weight of one or more dopants including one or more of germanium, manganese, phosphorus, and titanium in a metal or metal alloy comprising from about 90% to about 99.999% by weight gallium or indium, wherein the method comprises mixing the one or more dopants as particulates into a molten metal or metal alloy, and cooling the molten metal or metal alloy with the one or more dopant particulates to form a metal or metal alloy composite.
  • In another particular exemplary embodiment, the techniques may be realized as a method of incorporating from about 0.001% to about 10% by weight of one or more dopants including one or more of germanium, manganese, phosphorus, and titanium in a metal or metal alloy comprising from about 90% to about 99.999% by weight gallium or indium, wherein the method comprises mixing the one or more dopants into a solid form of the metal or metal alloy by mechanical force.
  • In another particular exemplary embodiment, the techniques may be realized as a method of incorporating from about 0.001% to about 10% by weight of one or more dopants including one or more of germanium, manganese, phosphorus, and titanium in a metal or metal alloy comprising from about 90% to about 99.999% by weight gallium or indium, wherein the method comprises mixing the one or more dopants as particulates into a metal or metal alloy powder to form a metal or metal alloy powder mixture.
  • In another particular exemplary embodiment, the techniques may be realized as a method of incorporating from about 0.001% to about 10% by weight of one or more dopants including one or more of germanium, manganese, phosphorus, and titanium in a metal or metal alloy comprising from about 90% to about 99.999% by weight gallium or indium, wherein the method comprises putting the one or more dopants as particulates in an interconnecting substrate with the metal or metal alloy, wherein the interconnecting substrate may include at least one of a pad on circuit board, a heat spreader, a heat sink, and a back side of component.
  • The present disclosure will now be described in more detail with reference to exemplary embodiments thereof as shown in the accompanying drawings. While the present disclosure is described below with reference to exemplary embodiments, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art having access to the teachings herein will recognize additional implementations, modifications, and embodiments, as well as other fields of use, which are within the scope of the present disclosure as described herein, and with respect to which the present disclosure may be of significant utility.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • In order to facilitate a fuller understanding of the present disclosure, reference is now made to the accompanying drawings, in which like elements are referenced with like numerals. These drawings should not be construed as limiting the present disclosure, but are intended to be exemplary only.
  • FIG. 1 is a table of IMC thickness and Nickel (Ni) layer consumption of aged pure Indium (In) and 2% Germanium (Ge)/Indium (In) samples in accordance with an embodiment of the present disclosure.
  • FIG. 2 shows a scanning electron microscopy (SEM) picture, magnified ×1000, of a pure Indium (In) sample on a Nickel (Ni)/Gold (Au) substrate aged for 1000 hrs at 150° C. in accordance with an embodiment of the present disclosure.
  • FIG. 3 shows a scanning electron microscopy (SEM) picture, magnified ×1000, of a 2% Germanium (Ge)/Indium (In) sample on a Nickel (Ni)/Gold (Au) substrate aged for 1000 hrs at 150° C. in accordance with an embodiment of the present disclosure.
  • FIG. 4 shows a scanning electron microscopy (SEM) picture, magnified ×3000, of a 2% Germanium (Ge)/Indium (In) sample on a Nickel (Ni)/Gold (Au) substrate aged for 1000 hrs at 150° C. in accordance with an embodiment of the present disclosure.
  • FIG. 5 is a table of IMC compositions of aged pure Indium (In) and 2% Germanium (Ge)/Indium (In) samples in accordance with an embodiment of the present disclosure.
  • FIG. 6 shows a graph of oxide formed in a 85° C./85% relative humidity chamber for pure Gallium (Ga) and 0.05% and 0.1% Germanium (Ge)-doped Gallium (Ga) in accordance with an embodiment of the present disclosure.
  • FIG. 7 shows a graph of oxide formed in a 85° C./85% relative humidity chamber for 0.5%, 1%, 2%, and 5% Germanium (Ge)-doped Gallium (Ga) in accordance with an embodiment of the present disclosure.
  • FIG. 8 shows a graph of oxide formed in a 85° C./85% relative humidity chamber for 0.0001% and 0.0005% Germanium (Ge)-doped Gallium (Ga) in accordance with an embodiment of the present disclosure.
  • FIG. 9 shows a graph of oxide formed in a 85° C./85% relative humidity chamber for Gallium (Ga)/Indium (In) alloys with and without 0.5% Germanium (Ge) in accordance with an embodiment of the present disclosure.
  • FIG. 10 shows a graph of oxide formed in a 85° C./85% relative humidity chamber for Indium (In)/Bismuth (Bi) alloys with and without 0.5% Germanium (Ge) in accordance with an embodiment of the present disclosure.
  • FIG. 11 shows a graph of oxide formed in a 85° C./85% relative humidity chamber for Gallium (Ga) alloys containing 0.5% Phosphorus (P), 0.5% Titanium (Ti), 0.5% Manganese (Mn), and no dopants in accordance with an embodiment of the present disclosure.
  • FIG. 12 is a table of relative peak intensity of Germanium (Ge) to Gallium (Ga) with different laser power for 2% Germanium (Ge)/Gallium (Ga) in accordance with an embodiment of the present disclosure.
  • FIG. 13 shows a graph of ICP-MS spectrum of 2% Germanium (Ge)/Gallium (Ga) for 15% laser power in accordance with an embodiment of the present disclosure.
  • FIG. 14 shows a graph of ICP-MS spectrum of 2% Germanium (Ge)/Gallium (Ga) for 25% laser power in accordance with an embodiment of the present disclosure.
  • FIG. 15 shows a mounting configuration wherein a metallurgical bond is formed between a pad of an electronic component and a pad of a substrate through an interconnecting material, such as solder, in accordance with an embodiment of the present disclosure.
  • FIG. 16 shows an application of a TIM in an electronic assembly in accordance with an embodiment of the present disclosure.
  • FIG. 17 shows a simplified example of a first TIM in the form of a phase change material, a thermally conductive gel, a thermally conductive tape, or a thermal grease that comprises a polymeric matrix filled with a thermally conductive filler between an IHS and an electronic component in accordance with an embodiment of the present disclosure.
  • FIG. 18 shows an example wherein a first TIM is a PSH where a thermally conductive filler stays as a liquid at service temperature and a polymeric matrix gives mechanical adhesion between an IHS and an electronic component in accordance with an embodiment of the present disclosure.
  • FIG. 19 shows an example wherein TIM material may be placed directly between an IHS and an electronic component without a polymeric matrix in accordance with an embodiment of the present disclosure.
  • DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS
  • Alloy compositions and techniques for reducing IMC thickness and oxidation of metals and alloys in accordance with embodiments of the present disclosure are described. Such alloy compositions and techniques were discovered through experimental testing. For example, in order to solve problems of solder joint reliability, an IMC growth test was used to reveal a technique for preventing IMC growth of interconnect material such as solder and TIM in accordance with an embodiment of the present disclosure. That is, significant, unprecedented effects were observed when IMC growths of 2% (wt) Germanium (Ge)/Indium (In) and pure Indium (In) on an electrolytic Nickel (Ni)/Gold (Au) substrate after aging in a 150° C. oven for 1000 hours. IMC thickness and Nickel (Ni) layer consumption of samples were measured after aging the samples. As shown in the table of FIG. 1, total IMC thickness of pure Indium (In) was about 18.8-19.6 microns while the IMC thickness of 2% Germanium (Ge)/Indium (In) was about 2.0-3.4 microns. The original thickness of Nickel (Ni) layer of the substrate was 5.3 microns and the Nickel (Ni) layer consumption of samples with pure Indium (In) and 2% Germanium (Ge)/Indium (In) were determined as 45.3-49.1% and 3.8-7.5%, respectively. FIGS. 2 and 3 show scanning electron microscopy (SEM) pictures of a pure Indium (In) sample and a 2% Germanium (Ge)/Indium (In) sample, respectively, on an electrolytic Nickel (Ni)/Gold (Au) substrate after aging in a 150° C. oven for 1000 hours. The decrease in IMC in the 2% Germanium (Ge)/Indium (In) sample is readily apparent. When seen at higher magnification, it is also apparent that the IMC consists of three layers (see FIG. 4).
  • In order to understand the mechanism for thinner IMC in germanium-doped indium, energy dispersive spectrometry (EDS) is helpful and thus was performed. The table of FIG. 5 summarizes EDS analysis results for the pure Indium (In) sample and the 2% Germanium (Ge)/Indium (In) sample.
  • Summarizing, as shown in FIG. 2, only one layer of IMC is found in the pure Indium (In) sample. However, as shown in FIGS. 3 and 4, three layers of IMC are found in the 2% Germanium (Ge)/Indium (In) sample. As shown in the table of FIG. 5, the composition of the IMC in the pure Indium (In) sample was determined to be (Ni, Au)28In72, Meanwhile, the composition of the first IMC layer (i.e., closest to solder) of the 2% Germanium (Ge)/Indium (In) sample was determined to be 54% Indium (In), 32% Nickel (Ni), 13% Germanium (Ge), and 1% Gold (Au). It should be noted, however, that the actual composition of the first IMC layer of the 2% Germanium (Ge)/Indium (In) sample may not be precisely accurate because the first IMC layer of the 2% Germanium (Ge)/Indium (In) sample was thinner than the measurement resolution. Thus, materials in areas other than the first IMC layer of the 2% Germanium (Ge)/Indium (In) sample may be included in the composition of the first IMC layer of the 2% Germanium (Ge)/Indium (In) sample. The second IMC layer of the 2% Germanium (Ge)/Indium (In) sample, however, was thicker than the first IMC layer of the 2% Germanium (Ge)/Indium (In) sample and thus it was possible to determine the exact composition of the second IMC layer of the 2% Germanium (Ge)/Indium (In) sample as (Ni, In, Au)50Ge50. The composition of third IMC layer of the 2% Germanium (Ge)/Indium (In) sample was same as the composition of the IMC in the pure Indium (In) sample.
  • It is believed that Germanium (Ge) reacts with Nickel (Ni) in the early stages of aging to form Germanium (Ge)-rich IMC layers and that these Germanium (Ge)-rich IMC layers protect the Nickel (Ni) layer from reaction with solder. It is also believed that when a certain IMC layer forms a dense and stable layer that can block inter-diffusion between solder and a substrate material, thinner total IMC and less consumption of the substrate material such as for UBM is observed. Thus, it is further believed that formation of such a protective IMC layer results in better reliability. From the discussion above, it may be concluded that the thin layer(s) of Germanium (Ge)-rich IMC plays a role as diffusion barrier to slow down solder diffusion to substrate.
  • In order to solve problems of oxidation of metals, including low melting temperature metals, an oxidation test was used to reveal a technique for preventing oxidation in accordance with an embodiment of the present disclosure. Indeed, the above-described significant, unprecedented effects of Germanium (Ge) were also observed in low melting temperature metals such as gallium in the oxidation test. That is, samples of low melting temperature metals 99.95% Gallium (Ga)/0.05% Germanium (Ge), 99.9% Gallium (Ga)/0.1% Germanium (Ge), and pure Gallium (Ga) were placed in a 85° C./85% relative humidity chamber. Metal oxide formed on top of the metals in a vial. The amount of oxide was determined by measuring the height of the oxide part (volume) formed on top of the metals. The amount of oxide for the pure Gallium (Ga) sample increased rapidly and showed about 90% oxide in 10 days. In contrast, the samples of Gallium (Ga) containing small amounts of Germanium (Ge) showed much slower oxidation rates. Indeed, the 99.95% Gallium (Ga)/0.05% Germanium (Ge) and 99.9% Gallium (Ga)/0.1% Germanium (Ge) samples didn't show a significant amount of oxide until after 80 days in the 85° C./85% relative humidity chamber (see FIG. 6).
  • To see if higher concentrations of Germanium (Ge) may give better oxidation properties, samples of Gallium (Ga) containing 0.5, 1, 2, and 5% (wt) Germanium (Ge) were tested. As shown in FIG. 7, there is no big improvement by using higher concentrations of Germanium (Ge).
  • To check for a lower limit of the effective amount of Germanium (Ge), 0.0001% Germanium (Ge)/Gallium (Ga) and 0.0005% Germanium (Ge)/Gallium (Ga) were tested. As shown in FIG. 8, only a slight effect was observed for these alloys.
  • Gallium (Ga)/Indium (In) is a eutectic alloy and thus may also be a good thermal interface material. The anti-oxidation effect of Germanium (Ge) on such an alloy would therefore be of interest in view of the above findings. Therefore, the oxidation rate of a 78.6% Gallium (Ga)/21.4% Indium (In) alloy was compared with a 0.5% Germanium (Ge)/78.2% Gallium (Ga)/21.3% Indium (In) alloy. As shown in FIG. 9, the Germanium (Ge)-containing Gallium (Ga)/Indium (In) alloy showed a much more stable oxidation property.
  • Bismuth (Bi)/Indium (In) is also a eutectic alloy and thus may also be a good thermal interface material. The anti-oxidation effect of Germanium (Ge) on such an alloy would therefore be of interest in view of the above findings. Therefore, the oxidation rate of a 66.7% Indium (In)/33.3% Bismuth (Bi) alloy was compared with a 0.5% Germanium (Ge)/66.4% Indium (In)/33.1% Bismuth (Bi) alloy. As shown in FIG. 10, only a slight anti-oxidation effect was observed for the Germanium (Ge)-containing Indium (In)/Bismuth (Bi) alloy.
  • For comparison purposes, the anti-oxidation effect of other dopants on Gallium (Ga) would be of interest in view of the above findings. Therefore, the oxidation rate of 0.5% Phosphorus (P)/Gallium (Ga), 0.5% Titanium (Ti)/Gallium (Ga), and 0.5% Manganese (Mn)/Gallium (Ga) were compared with pure Gallium (Ga). As shown in FIG. 11, some anti-oxidation effect was observed for the Phosphorus (P), Titanium (Ti), and Manganese (Mn)-doped Gallium (Ga), but not as much as Germanium (Ge)-doped Gallium (Ga).
  • The mechanism for using Germanium (Ge) to protect Gallium (Ga) from oxidation was investigated. It was assumed that a thin Germanium (Ge)-containing protective layer was formed and that this layer protected further reaction of Gallium (Ga) with oxygen. A laser ablation ICP-MS method was used to verify this mechanism. The laser ablation ICP-MS method is widely used for surface composition analysis. During this method a high energy laser ablates a small area of the surface of a sample. The ablated material is then transferred into an ICP-MS analysis chamber. The higher the laser intensity, the deeper the ablation.
  • When lower laser power (15%) was used so that the ablation was shallow, the relative intensity of the Germanium (Ge) major peak (68.8-68.9) was 31-32% to the Gallium (Ga) major peak (68.8-68.9) for 2% Germanium (Ge)/Gallium (Ga). When the higher laser power (25%) was used, the relative intensity of Germanium (Ge) was 8-10%. The results give qualitative evidence that the Germanium (Ge) atoms go to the surface to protect the alloy from oxidation. The test has repeated at a different spot of the sample and showed the same result. FIGS. 12-14 show the analysis results.
  • Referring to FIG. 15, there is shown a mounting configuration wherein a metallurgical bond is formed between a pad 2 of an electronic component 1 and a pad 4 of a substrate 5 through an interconnecting material 3, such as solder, in accordance with an embodiment of the present disclosure. IMC layers build up between the solder interconnecting material 3 and the component pad 2 and/or the substrate pad 4. The compositions described herein may reduce IMC growth between the solder interconnecting material 3 and the component pad 2 and/or the substrate pad 4 to increase reliability of the electronic component 1.
  • Referring to FIG. 16, there is shown an application of a TIM in an electronic assembly in accordance with an embodiment of the present disclosure. The electronic assembly comprises a substrate 5 connected to an electronic component 1 through interconnecting material 10. An integrated heat spreader (IHS) 8 is attached to a top side of the electronic component 1 using a first TIM 9 to dissipate heat generated from the electronic component 1. The IHS 8 is also connected to a heat sink 6 by a second TIM 7 for further dissipation of heat.
  • One of the most effective materials for the first TIM 9 and the second TIM 7 is a thermal solder such as indium, indium alloys, gallium-indium alloy, gallium-indium-tin alloy, gallium-indium-tin-zinc alloy, indium-lead alloy, indium-lead-silver alloy, bismuth-tin alloy, and indium-tin-bismuth alloy. The compositions described herein may reduce IMC growth between the electronic component 1 and the IHS 8 and/or between the IHS 8 and the heat sink 6 to increase reliability.
  • Referring to FIG. 17, there is shown a simplified example of the first TIM 9 in the form of a phase change material, a thermally conductive gel, a thermally conductive tape, or a thermal grease that comprises a polymeric matrix 12 filled with a thermally conductive filler 11 between the IHS 8 and the electronic component 1 in accordance with an embodiment of the present disclosure. The conductive filler 11 may include indium, indium alloys, gallium, gallium-indium alloy, gallium-indium-tin alloy, gallium-indium-tin-zinc alloy, cadmium, cadmium alloys, indium-lead alloy, indium-lead-silver alloy, mercury, mercury alloys, bismuth-tin alloy, and indium-tin-bismuth alloy. The compositions described herein may improve oxidation properties and reduce reactivity of the thermally conductive filler 11.
  • Referring to FIG. 18, there is shown an example wherein the first TIM 9 is a PSH where a thermally conductive filler 13 stays as a liquid at service temperature and the polymeric matrix 12 gives mechanical adhesion between the IHS 8 and the electronic component 1 in accordance with an embodiment of the present disclosure. The thermally conductive filler 13 may include indium, gallium, gallium-indium alloy, gallium-indium-tin alloy, gallium-indium-tin-zinc alloy, cadmium, cadmium alloys, indium-lead alloy, indium-lead-silver alloy, mercury, mercury alloys, bismuth-tin alloy, and indium-tin-bismuth alloy. The compositions described herein may improve oxidation properties and reduce reactivity of the thermally conductive filler 13.
  • Referring to FIG. 19, there is shown an example wherein TIM material 15 may be placed directly between the IHS 8 and the electronic component 1 without the polymeric matrix 12 in accordance with an embodiment of the present disclosure. The TIM material 15 may be liquid metal such as gallium or low melting point metals or alloys. A confiner 14 may be used to prevent the TIM material 15 in liquid form from leaking out from between the IHS 8 and the electronic component 1. The compositions described herein may improve oxidation properties and reduce reactivity of the TIM material 15.
  • The present disclosure is not to be limited in scope by the specific embodiments described herein. Indeed, other various embodiments of and modifications to the present disclosure, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Thus, such other embodiments and modifications are intended to fall within the scope of the present disclosure. Further, although the present disclosure has been described herein in the context of a particular implementation in a particular environment for a particular purpose, those of ordinary skill in the art will recognize that its usefulness is not limited thereto and that the present disclosure may be beneficially implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below should be construed in view of the full breadth and spirit of the present disclosure as described herein.

Claims (17)

1. A composition of alloy or mixture consisting essentially of from about 90% to about 99.999% by weight indium and from about 0.001% to about 10% by weight germanium and unavoidable impurities.
2. A composition of alloy or mixture consisting essentially of from about 90% to about 99.999% by weight indium and from about 0.001% to about 10% by weight of one or more of germanium, manganese, phosphorus, and titanium.
3. A composition of alloy consisting essentially of from about 90% to about 99.999% by weight gallium and from about 0.001% to about 10% by weight germanium and unavoidable impurities.
4. A composition of alloy consisting essentially of from about 90% to about 99.999% by weight gallium and from about 0.001% to about 10% by weight of one or more of germanium, manganese, phosphorus, and titanium.
5. A composition of alloy consisting essentially of gallium-indium alloy, gallium-indium-tin alloy, gallium-indium-tin-zinc alloy, cadmium, cadmium alloys, indium-lead alloy, indium-lead-silver alloy, mercury, mercury alloys, bismuth-tin alloy, indium-tin-bismuth alloy, and mixtures thereof containing from about 0.001% to about 10% by weight of one or more of germanium, manganese, phosphorus, and titanium and unavoidable impurities.
6. A method of incorporating from about 0.001% to about 10% by weight of one or more dopants including one or more of germanium, manganese, phosphorus, and titanium in a metal or metal alloy comprising from about 90% to about 99.999% by weight gallium or indium, the method comprising:
mixing the one or more dopants into the metal or metal alloy as a solution with heat.
7. The method of claim 6, further comprising:
cooling the mixture quickly to get finer dopant or intermetallic particles that diffuse faster than larger particles.
8. A method of incorporating from about 0.001% to about 10% by weight of one or more dopants including one or more of germanium, manganese, phosphorus, and titanium in a metal or metal alloy comprising from about 90% to about 99.999% by weight gallium or indium, the method comprising:
mixing the one or more dopants as particulates into a molten metal or metal alloy; and
cooling the molten metal or metal alloy with the one or more dopant particulates to form a metal or metal alloy composite.
9. A method of incorporating from about 0.001% to about 10% by weight of one or more dopants including one or more of germanium, manganese, phosphorus, and titanium in a metal or metal alloy comprising from about 90% to about 99.999% by weight gallium or indium, the method comprising:
mixing the one or more dopants into a solid form of the metal or metal alloy by mechanical force.
10. A method of incorporating from about 0.001% to about 10% by weight of one or more dopants including one or more of germanium, manganese, phosphorus, and titanium in a metal or metal alloy comprising from about 90% to about 99.999% by weight gallium or indium, the method comprising:
mixing the one or more dopants as particulates into a metal or metal alloy powder to form a metal or metal alloy powder mixture.
11. A method of incorporating from about 0.001% to about 10% by weight of one or more dopants including one or more of germanium, manganese, phosphorus, and titanium in a metal or metal alloy comprising from about 90% to about 99.999% by weight gallium or indium, the method comprising:
putting the one or more dopants as particulates in an interconnecting substrate with the metal or metal alloy.
12. The method of claim 11, wherein the interconnecting substrate includes at least one of a pad on circuit board, a heat spreader, a heat sink, and a back side of component.
13. A metallurgical interconnect material formed of the composition in any of claims 1 to 5.
14. A thermal interface material formed of the composition in any of claims 1 to 5.
15. The thermal interface material of claim 14, further comprising one or more of a phase change material, a thermally conductive gel, a thermally conductive tape, and a thermal grease.
16. A thermally conductive filler formed of the composition in any of claims 1 to 5.
17. A thermally conductive medium formed of the composition in any of claims 1 to 5.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011112722A1 (en) * 2010-03-09 2011-09-15 Indium Corporation Composite solder alloy perform
US20120234687A1 (en) * 2009-09-08 2012-09-20 Kenneth Seddon Soldering process using electrodeposited indium and/or gallium, and article comprising an intermediate layer with indium and/or gallium
US8771592B2 (en) 2011-02-04 2014-07-08 Antaya Technologies Corp. Lead-free solder composition
US20170103937A1 (en) * 2015-10-09 2017-04-13 Taiwan Semiconductor Manufacturing Company, Ltd. Cooling Devices, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices
JP2017212253A (en) * 2016-05-23 2017-11-30 三菱電機株式会社 Heat radiation sheet and semiconductor device

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103107104A (en) * 2011-11-11 2013-05-15 北京大学深圳研究生院 Flip chip manufacture method
CN103131396B (en) * 2011-12-02 2016-01-27 中国科学院理化技术研究所 Thermal interface material and manufacturing method thereof
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US10607857B2 (en) * 2017-12-06 2020-03-31 Indium Corporation Semiconductor device assembly including a thermal interface bond between a semiconductor die and a passive heat exchanger

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2850412A (en) * 1954-08-13 1958-09-02 Sylvania Electric Prod Process for producing germaniumindium alloyed junctions
US4735771A (en) * 1986-12-03 1988-04-05 Chrysler Motors Corporation Method of preparing oxidation resistant iron base alloy compositions
US4960654A (en) * 1988-08-29 1990-10-02 Matsushita Electric Industrial Co., Ltd. Metal composition comprising zinc oxide whiskers
US5445308A (en) * 1993-03-29 1995-08-29 Nelson; Richard D. Thermally conductive connection with matrix material and randomly dispersed filler containing liquid metal
US5770482A (en) * 1996-10-08 1998-06-23 Advanced Micro Devices, Inc. Multi-level transistor fabrication method with a patterned upper transistor substrate and interconnection thereto
US5773359A (en) * 1995-12-26 1998-06-30 Motorola, Inc. Interconnect system and method of fabrication
US6220607B1 (en) * 1998-04-17 2001-04-24 Applied Materials, Inc. Thermally conductive conformal media

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2806807A (en) * 1955-08-23 1957-09-17 Gen Electric Method of making contacts to semiconductor bodies
GB2201545B (en) * 1987-01-30 1991-09-11 Tanaka Electronics Ind Method for connecting semiconductor material
US5053195A (en) * 1989-07-19 1991-10-01 Microelectronics And Computer Technology Corp. Bonding amalgam and method of making
US5061442A (en) * 1990-10-09 1991-10-29 Eastman Kodak Company Method of forming a thin sheet of an amalgam
MXPA03010716A (en) * 2001-05-24 2004-05-27 Fry Metals Inc THERMAL INTERFACE MATERIAL AND HEAT SHOOT CONFIGURATION.

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2850412A (en) * 1954-08-13 1958-09-02 Sylvania Electric Prod Process for producing germaniumindium alloyed junctions
US4735771A (en) * 1986-12-03 1988-04-05 Chrysler Motors Corporation Method of preparing oxidation resistant iron base alloy compositions
US4960654A (en) * 1988-08-29 1990-10-02 Matsushita Electric Industrial Co., Ltd. Metal composition comprising zinc oxide whiskers
US5445308A (en) * 1993-03-29 1995-08-29 Nelson; Richard D. Thermally conductive connection with matrix material and randomly dispersed filler containing liquid metal
US5773359A (en) * 1995-12-26 1998-06-30 Motorola, Inc. Interconnect system and method of fabrication
US5770482A (en) * 1996-10-08 1998-06-23 Advanced Micro Devices, Inc. Multi-level transistor fabrication method with a patterned upper transistor substrate and interconnection thereto
US6220607B1 (en) * 1998-04-17 2001-04-24 Applied Materials, Inc. Thermally conductive conformal media

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120234687A1 (en) * 2009-09-08 2012-09-20 Kenneth Seddon Soldering process using electrodeposited indium and/or gallium, and article comprising an intermediate layer with indium and/or gallium
WO2011112722A1 (en) * 2010-03-09 2011-09-15 Indium Corporation Composite solder alloy perform
US20110220704A1 (en) * 2010-03-09 2011-09-15 Weiping Liu Composite solder alloy preform
US8348139B2 (en) 2010-03-09 2013-01-08 Indium Corporation Composite solder alloy preform
US8771592B2 (en) 2011-02-04 2014-07-08 Antaya Technologies Corp. Lead-free solder composition
US9975207B2 (en) 2011-02-04 2018-05-22 Antaya Technologies Corporation Lead-free solder composition
US20170103937A1 (en) * 2015-10-09 2017-04-13 Taiwan Semiconductor Manufacturing Company, Ltd. Cooling Devices, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices
US10269682B2 (en) * 2015-10-09 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices
US20190252294A1 (en) * 2015-10-09 2019-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Cooling Devices, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices
US11004771B2 (en) * 2015-10-09 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices
JP2017212253A (en) * 2016-05-23 2017-11-30 三菱電機株式会社 Heat radiation sheet and semiconductor device

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