US20070218579A1

US20070218579A1 - Wide output swing CMOS imager

Info

Publication number: US20070218579A1
Application number: US11/416,742
Authority: US
Inventors: Jong-Jan Lee; Sheng Hsu
Original assignee: Sharp Laboratories of America Inc
Current assignee: Sharp Laboratories of America Inc
Priority date: 2006-03-17
Filing date: 2006-05-03
Publication date: 2007-09-20
Also published as: US7737391B2; US7233036B1; US20070215921A1

Abstract

A CMOS active pixel sensor (APS) imager cell is provided on a silicon-on-insulator (SOI) substrate. The APS imager cell is made from a SOI substrate including a silicon (Si) substrate, a silicon dioxide insulator overlying the substrate, and a Si top layer overlying the insulator. A pixel sensor cell including a photodiode is formed in the Si top layer of the SOI substrate. A pixel transistor set is formed in the SOI top Si layer and connected to the pixel sensor cell. The pixel transistor set includes at least one p-channel MOS (PMOS) transistor and at least one n-channel MOS (NMOS) transistor. In the case of a three-transistor (3T) pixel transistor set, the selected transistor is NMOS, the reset transistor is PMOS, and the source follower may be either NMOS or PMOS.

Description

RELATED APPLICATIONS

This application is a Continuation-in-Part of a pending patent application entitled, A REAL-TIME CMOS IMAGER HAVING STACKED PHOTODIODES FABRICATED ON SOI WAFER, invented by Lee et al., Ser. No. 11/384,110, filed Mar. 17, 2006, Attorney Docket No. SLA8033, which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention
This invention generally relates complementary metal/oxide/semiconductor (CMOS) imaging sensors and, more particularly, to an imager pixel sensor cell made from a combination of n-channel MOS devices, p-channel MOS devices, and photodiodes on a silicon-on-insulator (SOI) substrate.
2. Description of the Related Art
FIG. 1 is a schematic diagram depicting an active pixel sensor (APS) imager cell made with n-channel MOS (NMOS) transistors (prior art). The APS cell includes a reset transistor, source follower transistor, select transistor, and a photodiode. All three transistors in the APS cell are NMOS. The drain and source terminals of the reset transistor are respectively coupled to a reference supply (V_Ref) and a cathode (node 1) of photodiode, whose anode is coupled to a ground or fixed reference voltage (V_ss). The source terminal of reset transistor drives the gate terminal of source follower transistor, whose drain and source terminals are coupled, respectively, to a power supply (V_DD) and drain terminal of the select transistor. The reference supply (V_Ref) may be, but need not be, equal to the power supply (V_DD). During operation, a high reset voltage (V_Reset) is initially provided at the reset transistor to pull node 1 up to a dark reference voltage (V_Dark). If the active reset voltage is high enough to keep reset transistor in the linear region, the dark reference voltage V_Darkequals V_Ref. When the reset voltage is turned off, the charge trapped at photodiode cathode (i.e., node 1) maintains a high voltage there. When the APS cell is exposed to light, the photodiode discharges node 1, to bring the voltage at node 1 towards the ground reference voltage. The voltage at node 1 can be read by turning on the select transistor, which is done by applying a selection voltage to the gate terminal of the select transistor, and sensing the output voltage V_out. For an undischarged pixel, voltage V_outis given by:
V _out =V _Dark −V _noise −V _TN
where V_Darkis the dark reference voltage at node 1, V_noiserepresents a reset noise, and V_TNis the threshold voltage for source follower transistor.
If the reset transistor is a typical NMOS transistor, the reset transistor can operate in the linear region, so that V_Darkcan be made very close to reference supply voltage V_Ref. In a transistor typically used in a 0.25 micrometer (um) gate width CMOS logic circuit, the threshold voltage V_TNis approximately 0.5 volts, and the supply voltage is approximately 2.5 volts. Consequently, V_outhas an output swing of less than 2 volts between the undischarged state and the discharged state of APS cell. If the reset voltage V_Resetat the gate terminal of the reset transistor is set to V_Ref, V_Darkis approximately V_Ref−V_TN, and the output swing is even less. For example, if both V_Refand V_Reset, set are set to V_DD, V_Dark=V_DD−V_TN, and V_outhas an output swing of less than V_DD−2V_TN. For the 0.25 um CMOS case, the voltage swing between the undischarged state and the discharged state of APS cell is only 1.5 volts. Thus, the active pixel sensor of the prior art has poor performance under low power supply conditions.
FIG. 2 is a schematic diagram depicting a bulk silicon (Si) six-transistor (6T) stacked junction imager cell (prior art). The 6T cell includes the 3T cell of FIG. 1, plus additional transfer transistors.
FIG. 3 is a schematic diagram depicting a bulk Si nine-transistor (9T) stacked junction imager cell (prior art). The 9T cell includes three of the 3T cells of FIG. 1. Stacked photodetectors are used for color imaging, one diode for each of the red (R), green (G), and blue (B) colors. A stacked RGB photodiode can directly measure red, green, and blue signals by efficiently stacking three photodiodes on top of one another using a triple-well CMOS process wherein the blue, green, and red sensitive pn junctions are disposed at different depths beneath the surface of a semiconductor substrate upon which the imager is formed. This technology increases the sampling density, improves sharpness, and eliminates the color aliasing artifacts. Further, this technology does not require color filters.
Conventional CMOS design uses cooperating NMOS and p-channel MOS (PMOS) transistors fabricated in adjoining p-type doped wells (p-well) and n-type doped wells (n-wells). In order to fabricate imager cells as small as possible, it is preferable that the pixel control transistors be fabricated in a single well structure. To that end, the imager cells of FIGS. 2 and 3 are conventionally formed in a (p-well and the transistors must necessarily all be NMOS, even if the diodes are formed in a triple-well structure. However, as mentioned above in the description of FIG. 1, an NMOS transistor with V_DDon both the gate and drain can only reach a source voltage of V_DD−V_T, thereby decreasing the dynamic range of the pixel.
One approach to increasing the output voltage swing of a CMOS APS imager is to use a higher reset voltage (on the gate) to turn on the reset transistor. The use of such a voltage is detrimental to device operation, however, as the higher voltage can damage the transistor. This is especially true with advanced IC technologies that use a very thin gate oxide thickness, which is more easily damaged when using a higher reset voltage.
U.S. Pat. No. 6,476,372, invented by Merrill et al., describes another attempt to address the above-mentioned limitations in output voltage swing. To that end, Merrill et al. suggest the use of low threshold voltage (V_TN) NMOS reset and source follower transistors. However, even with this solution, the operating range is limited at the low-end by leakage current in the reset transistor. That is, with a low V_TN, the transistor is leaky when off, and the V_Darkvoltage can drop with time (between resets).
The use of PMOS reset and source follower transistors would increase the output voltage swing of an APS imager cell. However, if fabricated in bulk Si, this solution would require that the imager to be fabricated in adjacent p and n-wells, which would significantly increase the size of the imager.
It would be advantageous if the output voltage swing of a 3T (6T or 9T) APS imager cell could be increased, without increasing the imager size.

SUMMARY

The present invention describes an APS imager cell made from a Si-on-insulator (SOI) substrate, using PMOS reset and source follower transistors. The use of PMOS transistors increases the output swing, without increasing supply voltage V_DD. Since the pixel transistors are fabricated on the Si layer of the SOI wafer, separate n-wells and p-wells are not needed. The isolation between the NMOS and PMOS transistors is accomplished with a trench etch in the top Si layer. As a result, the size of the improved voltage swing imager cell is similar to an APS imager cell made from all NMOS transistors.
Accordingly, CMOS active pixel sensor (APS) imager cell is provided on a silicon-on-insulator (SOI) substrate. The APS imager cell is made from a SOI substrate including a silicon (Si) substrate, a silicon dioxide insulator overlying the substrate, and a Si top layer overlying the insulator. A pixel sensor cell including a photodiode is formed in the Si top layer of the SOI substrate. A pixel transistor set is formed in the SOI top Si layer and connected to the pixel sensor cell. The pixel transistor set includes at least one PMOS transistor and at least one NMOS transistor.
In one aspect, the pixel sensor cell is a stacked pixel sensor cell including a first photodiode with a pn junction formed in the SOI Si top layer, a second photodiode with a pn junction formed in the SOI Si substrate, and a third photodiode with a pn junction formed in the SOI Si substrate, underlying the second photodiode pn junction. More particularly, the first photodiode includes a first p layer formed in the SOI Si top layer connected to a reference voltage and a first n+layer in the SOI Si top layer, overlying the first p layer. The second photodiode includes a second p layer in the SOI Si substrate connected to the reference voltage, and a second n+layer in the SOI Si substrate, overlying the second p layer, and separated from the first p layer by the SOI insulator. The third photodiode includes a third p layer in the SOI Si substrate connected to the reference voltage, and a third n+layer in the SOI Si substrate, overlying the third p layer, and separated from the second p layer by a fourth p layer having a doping density greater than the second p layer.
In the case of a three-transistor (3T) pixel transistor set, the select transistor is NMOS, the reset transistor is PMOS, and the source follower may be either NMOS or PMOS. If the pixel transistor set is a 9T cell, it includes a first cell connected to the first photodiode, a second 3T cell connected to the second photodiode, and a third 3T cell connected to the third photodiode. If the pixel transistor set is a 6T cell, it includes a 3T cell, a first transfer transistor connected between the first photodiode and the 3T cell, a second transfer transistor connected between the second photodiode and the 3T cell, and a third transfer transistor connected between the third photodiode and the 3T cell.
Additional details of the above-described APS imager cell are provided below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram depicting an active pixel sensor (APS) imager cell made with n-channel MOS (NMOS) transistors (prior art).
FIG. 2 is a schematic diagram depicting a bulk silicon (Si) six-transistor (6T) stacked junction imager cell (prior art).
FIG. 3 is a schematic diagram depicting a bulk Si nine-transistor (9T) stacked junction imager cell (prior art).
FIG. 4 is a schematic block diagram depicting a CMOS APS imager cell on a silicon-on-insulator (SOI) substrate.
FIG. 5 is a schematic block diagram depicting the APS imager cell of FIG. 4 made with a stacked pixel sensor cell.
FIG. 6 is a schematic diagram depicting the APS imager cell of FIG. 4 as a 3T cell pixel transistor set connected to a single photodiode.
FIG. 7 is a schematic diagram depicting the APS imager cell of FIG. 4 as a 9T cell pixel transistor set connected to a stacked pixel sensor cell.
FIG. 8 is a schematic diagram depicting the APS imager cell of FIG. 4 as a 6T cell pixel transistor set connected to a stacked pixel sensor cell.
FIG. 9 is a flowchart illustrating a method for operating a CMOS APS imager cell on a SOI substrate.
FIG. 10 is a schematic diagram depicting a CMOS APS imager made from a plurality of 9T APS imager cells.

DETAILED DESCRIPTION

FIG. 4 is a schematic block diagram depicting a CMOS APS imager cell on a silicon-on-insulator (SOI) substrate. The APS imager cell is comprised of a pixel sensor cell and a pixel transistor set. The APS imager cell 400 comprises a SOI substrate 402 including a silicon (Si) substrate 404, a silicon dioxide insulator 406 overlying the substrate 404, and a Si top layer 408 overlying the insulator 406. A pixel sensor cell 410, including a photodiode 412, is formed in the Si top layer 408 of the SOI substrate 402. A pixel transistor set 414 is also formed in the SOI top Si layer 408 and connected to the pixel sensor cell 410. As described in more detail below, the pixel transistor set 414 includes at least one p-channel MOS (PMOS) transistor and at least one n-channel MOS (NMOS) transistor. Typically, the pixel transistor set 414 is a three-transistor (3T) set for use with a single photodiode, or a nine-transistor (9T) or a six-transistor (6T) cell, for use with stacked (multiple) photodiodes. A CMOS APS imager may be made up of thousands of APS imager cells arranged in a matrix structure.
FIG. 5 is a schematic block diagram depicting the APS imager cell of FIG. 4 made with a stacked pixel sensor cell. The stacked pixel sensor cell 500 includes the first photodiode 412 with a pn junction 502 formed in the SOI Si top layer 408. A second photodiode 504 with a pn junction 506 is formed in the SOI Si substrate 404. A third photodiode 508 with a pn junction 510 is formed in the SOI Si substrate 404, underlying the second photodiode pn junction 506. As described in more detail below, the pixel transistor set 414, represented by transistor 511, may be a 6T or 9T cell.
More particularly, the first photodiode 412 includes a first p layer 512 formed in the SOI Si top layer 408, connected to a reference voltage (not shown). For simplicity, the reference voltage can be assumed to be ground. A first n+layer 514 is formed in the SOI Si top layer 408, overlying the first p layer 512. The second photodiode 504 includes a second p layer 516 in the SOI Si substrate 404 connected to the reference voltage. A second n+layer 518 is formed in the SOI Si substrate 404, overlying the second p layer 516, and separated from the first p layer 512 by the SOI insulator 406. The third photodiode 508 includes a third p layer 520 in the SOI Si substrate 404 connected to the reference voltage. A third n+layer 522 is formed in the SOI Si substrate 404 overlying the third p layer 520, and separated from the second p layer 516 by a fourth p layer 524. The fourth p layer 524 has a doping density that is greater than the second p layer 516.
In another aspect, the SOI Si top layer 408 has a top surface 526. The first photodiode pn junction 502 has a depth 528 about 0.1 to 0.5 micrometers (μm) beneath the SOI Si top layer top surface 526. Typically, the Si top layer 408 has an overall thickness 540 of about 0.1 to 1 um. This depth is associated with the sensing of blue light. The second photodiode pn junction 506 has an effective depth 530 about 0.5 to 1.5 μm beneath the SOI Si top layer top surface 526, and is associated with the sensing of green light. “Effective depth” is defined herein as the depth beneath top surface 526, after the thickness of the SiO2 layer 406 is subtracted from the total depth (from 526 to 530). The SiO2 layer 506 has a thickness 542 of about 0.02 to 1 um, and its thickness can be subtracted from the effective depth because it is transparent to visible spectrum light. The thickness 540 of the Si top layer 408, however, acts as a color filter. The third photodiode pn junction 510 has an effective depth 532 about 1.5 to 6 μm beneath the SOI Si top layer top surface 408, and is associated with sensing red light.
Fabrication details for the above-described stacked pixel sensor cell, and related sensor cells, are provided in a pending parent application, A REAL-TIME CMOS IMAGER HAVING STACKED PHOTODIODES FABRICATED ON SOI WAFER, invented by Lee et al., Ser. No. 11/384,110, filed Mar. 17, 2006, which is incorporated herein by reference.
FIG. 6 is a schematic diagram depicting the APS imager cell of FIG. 4 as a 3T cell pixel transistor set connected to a single photodiode. The 3T cell 600 includes an NMOS select transistor 602 with a first source/drain (S/D) region 604 connected to a column out line 606, a second S/D region 608, and a gate 610 connected to a select line 612. A source follower transistor 614 may be either a PMOS device or an NMOS device (as shown). The source follower 614 has a first S/D region 616 connected to the second S/D 608 of the select transistor 602. A second S/D region 618 is connected to a supply voltage (V_DD), and a gate 620 is connected to an n+region (514, see FIG. 5) or cathode of the photodiode 412. A PMOS reset transistor 624 has a first S/D region 626 connected to the n+region (cathode) of the photodiode 412, a second S/D region 628 connected to the supply voltage, and a gate 630 connected to a reset line 632.
FIG. 7 is a schematic diagram depicting the APS imager cell of FIG. 4 as a 9T cell pixel transistor set connected to a stacked pixel sensor cell. The 9T pixel transistor set 700 includes a first 3T cell 702 with a reset transistor 704, a source follower transistor 706, and a row select transistor 708 connected to the first photodiode 412. A second 3T cell 710 has a reset transistor 712, a source follower transistor 714, and a row select transistor 716, connected to the second photodiode 504. A third 3T cell 718 has a reset transistor 720, a source follower transistor 722, and a row select transistor 724, connected to the third photodiode 508.
The first 3T cell row select transistor 708 is an NMOS with a first S/D region 726 connected to a first column out line 728, a second S/D region 730, and a gate 732 connected to a row select line 734. The first 3T source follower 706 may be either a PMOS or an NMOS device (as shown). The first S/D region 736 is connected to the second S/D 730 of the row select transistor 708. A second S/D region 738 is connected to a supply voltage (V_DD), and a gate 740 is connected to an n+region (514, see FIG. 5) or cathode, of the first photodiode 412. The first 3T reset transistor 704 is a PMOS with a first S/D region 742 connected to the n+region (cathode) of the first photodiode 412, a second S/D region 744 connected to the supply voltage, and a gate 746 connected to the reset line 748.
The second 3T cell row select transistor 714 is an NMOS with a first S/D region 750 connected to a second column out line 752, a second S/D region 754, and a gate 756 connected to the row select line 758. The second 3T source follower 712 may be of a PMOS or an NMOS device (as shown), with a first S/D region 760 connected to the second S/D 754 of the row select transistor, a second S/D region 762 connected to a supply voltage, and a gate 764 connected to an n+region (see 518, FIG. 5) or cathode of the second photodiode 504. The second 3T reset transistor 710 is a PMOS with a first S/D region 766 connected to the n+region (cathode) of the second photodiode 504, a second S/D region 768 connected to the supply voltage, and a gate 770 connected to the reset line 748.
The third 3T cell row select transistor 724 is an NMOS with a first S/D region 772 connected to a third column out line 774, a second S/D region 776, and a gate 778 connected to the row select line 780. The third 3T source follower 722 may be a PMOS or an NMOS device (as shown), with a first S/D region 782 connected to the second S/D 776 of the row select transistor, a second S/D region 784 connected to the supply voltage, and a gate 786 connected to an n+region (522, see FIG. 5) or cathode of the third photodiode 508. The third 3T reset transistor is a PMOS with a first S/D region 788 connected to the n+region (cathode) of the third photodiode 508, a second S/D region 790 connected to the supply voltage, and a gate 792 connected to the reset line 794. Reset line 748 and 794 are typically connected together. Likewise, row select lines 734, 758 and 780 are typically a common line.
FIG. 10 is a schematic diagram depicting a CMOS APS imager made from a plurality of 9T APS imager cells. This diagram illustrates that a plurality of APS imager cells may all be controlled with a single reset and a single row select line.
FIG. 8 is a schematic diagram depicting the APS imager cell of FIG. 4 as a 6T cell pixel transistor set connected to a stacked pixel sensor cell. The 6T cell 800 includes a 3T cell 802 with a reset transistor 804, a source follower transistor 806, and a select transistor 808. A first transfer transistor 810 is connected between the first photodiode 412 and the 3T cell 802. A second transfer transistor 812 is connected between the second photodiode 504 and the 3T cell 802. A third transfer transistor 814 is connected between the third photodiode 508 and the 3T cell 802.
The 3T cell select transistor 808 is an NMOS with a first S/D region 816 connected to a column out line 818, a second S/D region 820, and a gate 822 connected to a select line 824. The 3T source follower 806 can be a PMOS and an NMOS device (as shown), with a first S/D region 826 connected to the second S/D 820 of the select transistor, a second S/D region 828 connected to a supply voltage (V_DD), and a gate 830. The 3T reset transistor 804 is a PMOS with a first S/D region 832 connected to the gate 830 of the source follower transistor, a second S/D region 834 connected to the supply voltage, and a gate 836 connected to a reset line 838.
The first transfer transistor 810 is an NMOS with a first S/D region 840 connected to an n+region (514, see FIG. 5) or cathode of the first photodiode 412, a second S/D region 842 connected to the gate 830 of the source follower transistor, and a gate 844 connected to a first transfer line 846. The second transfer transistor 812 is an NMOS with a first S/D region 848 connected to an n+region (518, see FIG. 5) or cathode of the second photodiode 504, a second S/D region 850 connected to the gate 830 of the source follower transistor, and a gate 852 connected to a second transfer line 854. The third transfer transistor 814 is an NMOS with a first S/D region 856 connected to an n+region (522, see FIG. 5) or cathode of the third photodiode 508, a second S/D region 858 connected to the gate 830 of the source follower transistor, and a gate 860 connected to a third transfer line 862.

Functional Description

The 6T and 9T designs shown in FIGS. 7 and 8 are especially advantageous when used with stacked photodetectors fabricated on an SOI substrate. Both NMOS and PMOS devices are used for the active pixel sensor cell, and they are fabricated on the top Si layer of the SOI wafer. The isolation between the NMOS and PMOS devices is achieved by a simple trench etching, as there is no well isolation issue. Furthermore, because the transistors are electrically isolated from the green and blue diodes by the buried oxide layer of the SOI wafer, there is no isolation issue between the pixel transistors and the photodiodes. Therefore, a stacked junction APS cell on SOI wafer can be fabricated in a much smaller area than a stacked junction APS cell on bulk Si wafer.
Returning to FIG. 6, the benefits associated with using a PMOS transistor in the APS imager cell are discussed in more detail below. As noted above, the active pixel sensor circuit of FIG. 6 is a basic component of the 9T (FIG. 7) and the 6T (FIG. 8) stacked junction imager cells. The reset transistor is PMOS, whereas the source follower and the select transistors are NMOS. The drain and source terminals of the reset transistor are respectively coupled to reference supply (V_Ref) and a cathode (node 1) of photodiode, whose anode is coupled to a ground or fixed reference voltage (V_ss) source. The source terminal of the reset transistor drives the gate terminal of the source follower transistor, whose drain and source terminals are coupled, respectively, to a power supply (V_DD) and drain terminal of the select transistor. Reference supply (V_Ref) can be, but need not be, equal to the power supply V_DD. During operation, a reset voltage V_Resetis initially provided at the reset transistor to pull node 1 to a dark reference voltage, V_Dark. Typically, the reset voltage is a negative value, so the V_Darkis pulled close to the V_Ref.
When the reset voltage is turned off, the charge trapped at photodiode cathode (node 1) is maintained at V_Ref. When the APS cell is exposed to light, the photodiode discharges node 1, to bring the voltage at node 1 towards the fixed or ground reference voltage V_ss. The voltage at node 1 is read by turning on the select transistor, by asserting a selection signal at the gate terminal of the select transistor, and sensing the output voltage Vout. For an undischarged pixel, voltage Vout is given by:
V_Out =V _Dark −V _Noise −V _TN.
where V_Darkis the dark reference voltage at node 1, V_Noiserepresents a reset noise, and V_TNis the threshold voltage for NMOS source follower transistor. Different from the prior art, which must use a smaller (less positive) reset voltage, V_Darkcan be pulled to the reference voltage V_Ref, using a reset voltage with a lower absolute value, because the reset transistor is PMOS. The low absolute value of the reset voltage tends to prevent degradation of the thin gate oxide.
For example, with a design using 0.25 um CMOS logic circuit gate widths, the threshold voltage V_TNis 0.5 V, V_TP(the threshold voltage for the reset transistor) is approximately −0.5 volts, and the supply voltage is approximately 2.5 volts. With the reset voltage less than −0.5 V (more negative than 0.5 V), then V_Dark=V_Ref. If V_Ref=V_DD, then V_Dark=2.5 V. In this case, V_outhas an output swing of 2.0 volts between the undischarged state and the discharged state of APS cell.
FIG. 9 is a flowchart illustrating a method for operating a CMOS APS imager cell on a SOI substrate. Although the method is depicted as a sequence of numbered steps for clarity, the numbering does not necessarily dictate the order of the steps. It should be understood that some of these steps may be skipped, performed in parallel, or performed without the requirement of maintaining a strict order of sequence. The method starts at Step 900.
Step 902 provides a MOS three-transistor (3T) cell including a p-channel (PMOS) reset transistor, an n-channel (NMOS) select transistor, a source follower transistor, and a photodiode fabricated in a top silicon (Si) layer of a SOI substrate, connected between a supply voltage (V_DD) and a reference (ground) voltage (see the explanation of FIG. 6, above). Step 904 accepts a select signal at the gate of the select transistor. Step 905 accepts a maximum reset voltage at the reset transistor gate that is less than the reset transistor threshold voltage (VTP). Step 906 supplies a photodiode cathode voltage swing at the reset transistor drain that is equal to V_dark−0=V_DD(assuming the reference voltage is ground). Step 908 supplies an output voltage (Vout) swing from the select transistor source greater than, or equal to V_DD—the source follower transistor threshold voltage (V_TN).
In one aspect, Step 902 provides a PMOS source follower transistor. Then, supplying the Vout voltage swing in Step 908 includes supplying a Vout voltage swing equal to V_DD(V_dark). In another aspect, Step 902 provides an NMOS source follower. Then, supplying the Vout voltage swing in Step 908 includes supplying a Vout voltage swing equal to V_DD−V_TN.
A CMOS APS imager cell, fabricated on a SOI substrate, has been presented. 3T, 6T, and 9T transistor sets have been described to illustrate the invention. However, the invention is not limited to merely these examples. Likewise, single photodiode and 3-diode sensors cells have been used as examples, but the invention is not limited to any particular number of diodes. It will be appreciated that further variations and modifications thereof may be made within the scope of the invention as defined in the appended claims.

Claims

1. A complimentary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) imager cell on a silicon-on-insulator (SOI) substrate, the APS imager cell comprising:

a SOI substrate including a silicon (Si) substrate, a silicon dioxide insulator overlying the substrate, and a Si top layer overlying the insulator;

a pixel sensor cell including a photodiode formed in the Si top layer of the SOI substrate; and,

a pixel transistor set in the SOI top Si layer connected to the pixel sensor cell and including at least one p-channel MOS (PMOS) transistor and at least one n-channel MOS (NMOS) transistor.

2. The APS imager cell of claim 1 wherein the pixel sensor cell is a stacked pixel sensor cell including:

a first photodiode with a pn junction formed in the SOI Si top layer;

a second photodiode with a pn junction formed in the SOI Si substrate; and,

a third photodiode with a pn junction formed in the SOI Si substrate, underlying the second photodiode pn junction.

3. The APS imager cell of claim 1 wherein the pixel transistor set is selected from a group including a three-transistor (3T), nine-transistor (9T) and a six-transistor (6T) cell.

4. The APS imager cell of claim 1 wherein the pixel transistor set is a 3T cell including:

an NMOS select transistor with a first source/drain (S/D) region connected to a column out line, a second S/D region, and a gate connected to a select line;

a source follower transistor selected from a group consisting of a PMOS and NMOS device, with a first S/D region connected to the second S/D of the select transistor, a second S/D region connected to a supply voltage, and a gate connected to an n+region of the photodiode; and,

a PMOS reset transistor with a first S/D region connected to the n+region of the photodiode, a second S/D region connected to the supply voltage, and a gate connected to a reset line.

5. The APS imager cell of claim 2 wherein the pixel transistor set is a 9T cell including:

a first 3T cell with a reset, source follower, and a row select transistor connected to the first photodiode;

a second 3T cell with a reset, source follower, and a row select transistor connected to the second photodiode; and,

a third 3T cell with a reset, source follower, and a row select transistor connected to the third photodiode.

6. The APS imager cell of claim 5 wherein the first 3T cell row select transistor is an NMOS with a first S/D region connected to a first column out line, a second S/D region, and a gate connected to a row select line;

wherein the first 3T source follower is selected from a group consisting of a PMOS and an NMOS device, with a first S/D region connected to the second S/D of the row select transistor, a second S/D region connected to a supply voltage, and a gate connected to an n+region of the first photodiode; and,

wherein the first 3T reset transistor is a PMOS with a first S/D region connected to the n+region of the first photodiode, a second S/D region connected to the supply voltage, and a gate connected to the reset line.

7. The APS imager cell of claim 6 wherein the second 3T cell row select transistor is an NMOS with a first S/D region connected to a second column out line, a second S/D region, and a gate connected to the row select line;

wherein the second 3T source follower is selected from a group consisting of a PMOS and an NMOS device, with a first S/D region connected to the second S/D of the row select transistor, a second S/D region connected to the supply voltage, and a gate connected to an n+region of the second photodiode; and,

wherein the second 3T reset transistor is a PMOS with a first S/D region connected to the n+region of the second photodiode, a second S/D region connected to the supply voltage, and a gate connected to the reset line.

8. The APS imager cell of claim 7 wherein the third 3T cell row select transistor is an NMOS with a first S/D region connected to a third column out line, a second S/D region, and a gate connected to the row select line;

wherein the third 3T source follower is selected from a group consisting of a PMOS and an NMOS device, with a first S/D region connected to the second S/D of the row select transistor, a second S/D region connected to the supply voltage, and a gate connected to an n+region of the third photodiode; and,

wherein the third 3T reset transistor is a PMOS with a first S/D region connected to the n+region of the third photodiode, a second S/D region connected to the supply voltage, and a gate connected to the reset line.

9. The APS imager cell of claim 2 wherein the pixel transistor set is a 6T cell including:

a 3T cell with a reset, source follower, and a select transistor;

a first transfer transistor connected between the first photodiode and the 3T cell;

a second transfer transistor connected between the second photodiode and the 3T cell; and,

a third transfer transistor connected between the third photodiode and the 3T cell.

10. The APS imager cell of claim 9 wherein the 3T cell select transistor is an NMOS with a first S/D region connected to a column out line, a second S/D region, and a gate connected to a select line;

wherein the 3T source follower is selected from a group consisting of a PMOS and an NMOS device, with a first S/D region connected to the second S/D of the select transistor, a second S/D region connected to a supply voltage, and a gate; and,

wherein the 3T reset transistor is a PMOS with a first S/D region connected to the gate of the source follower transistor, a second S/D region connected to the supply voltage, and a gate connected to a reset line.

11. The APS imager cell of claim 10 wherein the first transfer transistor is an NMOS with a first S/D region connected to an n+region of the first photodiode, a second S/D region connected to the gate of the source follower transistor, and a gate connected to a first transfer line;

wherein the second transfer transistor is an NMOS with a first S/D region connected to an n+region of the second photodiode, a second S/D region connected to the gate of the source follower transistor, and a gate connected to a second transfer line; and,

wherein the third transfer transistor is an NMOS with a first S/D region connected to an n+region of the third photodiode, a second S/D region connected to the gate of the source follower transistor, and a gate connected to a third transfer line.

12. The APS imager cell of claim 2 wherein the first photodiode includes:

a first p layer formed in the SOI Si top layer connected to a reference voltage; and,

a first n+layer in the SOI Si top layer, overlying the first p layer;

wherein the second photodiode includes:

a second p layer in the SOI Si substrate connected to the reference voltage; and,

a second n+layer in the SOI Si substrate, overlying the second p layer, and separated from the first p layer by the SOI insulator; and,

wherein the third photodiode includes:

a third p layer in the SOI Si substrate connected to the reference voltage; and,

a third n+layer in the SOI Si substrate, overlying the third p layer, and separated from the second p layer by a fourth p layer having a doping density greater than the second p layer.

13. The APS imager cell of claim 2 wherein the SOI Si top layer has a top surface;

wherein the first photodiode pn junction has a depth about 0.1 to 0.5 micrometers (μm) beneath the SOI Si top layer top surface;

wherein the second photodiode pn junction has an effective depth about 0.5 to 1.5 μm beneath the SOI Si top layer top surface; and,

wherein the third photodiode pn junction has an effective depth about 1.5 to 6 μm beneath the SOI Si top layer top surface.

14. A method for operating a complimentary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) imager cell on a silicon-on-insulator (SOI) substrate, the method comprising:

providing a MOS three-transistor (3T) cell including a p-channel (PMOS) reset transistor, an n-channel (NMOS) select transistor, a source follower transistor, and a photodiode fabricated in a top silicon (Si) layer of a SOI substrate, connected between a supply voltage (V_DD) and a ground voltage;

accepting a select signal at the gate of the select transistor; and,

supplying an output voltage (Vout) swing from the select transistor source greater than, or equal to V_DD—the source follower transistor threshold voltage (V_TN).

15. The method of claim 14 further comprising:

supplying a photodiode cathode voltage swing at the reset transistor drain that is equal to V_dark−0=V_DD.

16. The method of claim 15 wherein providing the 3T cell includes supplying a PMOS source follower transistor; and,

wherein supplying the Vout voltage swing from the select transistor source includes supplying a Vout voltage swing equal to V_DD(V_dark).

17. The method of claim 15 wherein providing the 3T cell includes supplying a NMOS source follower transistor; and,

wherein supplying the Vout voltage swing from the select transistor source includes supplying a Vout voltage swing equal to V_DD−V_TN.

18. The method of claim 15 further comprising:

accepting a maximum reset voltage at the reset transistor gate that is less than the reset transistor threshold voltage (V_TP).