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US20070158199A1 - Method to modulate the surface roughness of a plated deposit and create fine-grained flat bumps - Google Patents

Method to modulate the surface roughness of a plated deposit and create fine-grained flat bumps Download PDF

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Publication number
US20070158199A1
US20070158199A1 US11/323,547 US32354705A US2007158199A1 US 20070158199 A1 US20070158199 A1 US 20070158199A1 US 32354705 A US32354705 A US 32354705A US 2007158199 A1 US2007158199 A1 US 2007158199A1
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US
United States
Prior art keywords
plating bath
layer
copper
metal layer
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/323,547
Inventor
Scott Haight
Tzuen-Iuh Huang
Liang Harry
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Intel Corp
Original Assignee
Individual
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Publication date
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Priority to US11/323,547 priority Critical patent/US20070158199A1/en
Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HAIGHT, SCOTT M., HARRY, LIANG Y., HANG, TZUEH-IUH
Publication of US20070158199A1 publication Critical patent/US20070158199A1/en
Abandoned legal-status Critical Current

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    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/38—Electroplating: Baths therefor from solutions of copper
    • C—CHEMISTRY; METALLURGY
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    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/18—Electroplating using modulated, pulsed or reversing current
    • C—CHEMISTRY; METALLURGY
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    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
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    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0495—5th Group
    • H01L2924/04953—TaN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method

Definitions

  • Embodiments of this invention relate to a method for the formation of contact formations, particularly for use on semiconductor substrate and a system utilizing such contact formations.
  • Integrated circuits are formed on semiconductor substrates, such as wafers.
  • the wafers are then sawed (or “singulated” or “diced”) into microelectronic die, also known as semiconductor chips, with each chip carrying a respective integrated circuit.
  • microelectronic die also known as semiconductor chips
  • Each semiconductor chip is then mounted to a package, or carrier, substrate. Often the packages are then mounted to circuit boards, such as motherboards, which may then be installed in computing systems.
  • the package substrate provides structural integrity to the semiconductor chips and are used to connect the integrated circuits electrically to the motherboard.
  • a modern trend for these contact formations is the use of “copper bumps” which are formed on bonding pads on the die.
  • An underfill material such as an epoxy or paste, may also be present between the die and the packages.
  • Copper bumps are typically formed using an electroplating process. The formation of the bumps begins within a depression on the surface of the die. This depression leads to a dimple or other formations on the surface of the copper bumps opposite the die. It is this dimpled surfaced which is used to connect the die to the packages.
  • This dimple may allow material, such as solder, underfill material, or even air, to get caught between the copper bump and the package substrate when the chip-to-package connections are made. This trapped material weakens the strength of the mechanical bond between the die and package substrates and results in a decrease in the maximum amount of current that can be conducted through the copper bumps.
  • FIG. 1A is a top plan view of a semiconductor substrate.
  • FIG. 1B is a sectional view of the semiconductor substrate illustrated in FIG. 1A .
  • FIG. 2A is a cross-sectional side view of a microelectronic die, or a portion of the semiconductor substrate illustrated in FIG. 1A .
  • FIG. 2B is a cross-sectional side view of the microelectronic die with a passivation layer formed thereon.
  • FIG. 2C is a cross-sectional side view of the microelectronic die with an adhesion layer and a seed layer formed over the passivation layer.
  • FIG. 2D is a cross-sectional side view of the microelectronic die with a photoresist layer formed over the seed layer.
  • FIG. 3 is a cross-sectional schematic view of an electroplating apparatus.
  • FIGS. 4A and 4B are cross-sectional schematic views of the microelectronic die illustrating the formation of a contact formation within a trench in the photoresist layer.
  • FIGS. 5A and 5B are cross-sectional side views of the microelectronic die illustrating the removal of the photoresist layer.
  • FIG. 6 is a perspective view of the semiconductor substrate with a plurality of contact formations formed thereon.
  • FIG. 7A is a perspective view of the microelectronic die attached to the printed circuit board.
  • FIG. 8 is a perspective view of the package substrate attached to a printed circuit board.
  • the present invention relates to plating of a semiconductor structure by use of an inventive copper bath composition. Because of the inventive use of the copper bath composition, grain size is controlled and the presence of voids is reduced. Additionally, because of the inventive use of the copper baths composition, an article results in the form of an inventive contact structure.
  • FIGS. 1A and 1B illustrate a semiconductor substrate 10 .
  • the semiconductor substrate 10 may be a semiconductor wafer with a circular outer edge 12 , having a diameter of, for example, 200 or 300 mm, and an indicator 14 thereon.
  • the semiconductor substrate 10 may have a thickness 16 of, for example, 0.7 mm and a plurality of integrated circuits, separate amongst multiple die 18 , formed thereon.
  • FIGS. 2A illustrates one of the die 18 , or another portion of the semiconductor substrate 10 illustrated in FIGS. 1A and 1B .
  • Each die 18 may include an integrated circuit, such a microprocessor formed therein, which may include multiple transistors and capacitors 20 .
  • the die 18 may also include a plurality of alternating insulating and conducting layers and be in what is known as a “flip-chip” configuration, as is commonly understood in the art.
  • the die 18 may also include a bonding pad 22 formed within an upper surface thereof.
  • the bonding pad may have, for example, a width 24 of approximately 10 microns and a thickness 26 of approximately 1 micron.
  • the bonding pad 22 may be made of a conductive material, such as copper, and may be formed using electroplating.
  • the bonding pad 22 may be part of the integrated circuit, or be electrically connected to the integrated circuit within the die 18 .
  • FIG. 2B illustrates the die 18 with a passivation layer 28 formed thereon.
  • the passivation layer 28 may have a thickness of, for example, approximately 2 microns and may be selectively deposited or etched so that a central portion of the bonding pad 22 remains exposed.
  • the passivation layer 28 may include an upper layer made of, for example, polyimide or benzocyclobutene, formed over a lower layer made of a nitride, such as silicon nitride (SiN) or silicon oxide nitride (SiON).
  • FIG. 2C illustrates the die 18 with an adhesion layer 38 and a seed layer 40 deposited over the passivation layer 28 and the exposed portion of the bonding pad 22 .
  • the adhesion layer 38 may be made of a conductive material such as aluminum, titanium, titanium nitride, tantalum, tantalum nitride, tantalum silicon nitride, tungsten nitride, tungsten silicon nitride, titanium tungsten, nickel valadium, cobalt nickel tungsten phosphorous, cobalt nickel rhenium phosphorous, cobalt nickel tungsten boron, cobalt nickel rhenium boron, and or cobalt nickel rhenium boron phosphorous.
  • the adhesion layer 38 may be deposited by such methods as plasma vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and electroless plating.
  • PVD plasma vapor deposition
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • electroless plating may be electroless plating.
  • the adhesion layer 38 may have a thickness of, for example, between 10 and 1000 nanometers and may be formed over the exposed portion of the bonding pad 22 .
  • the seed layer 40 may be made of a conductive material such as, for example, copper, silver, gold, nickel, and or cobalt and may be deposited using PVD, CVD, ALD, electroless plating, and electroplating.
  • the seed layer 40 may have a thickness of, for example, between 10 and 10,000 nanometers and may be formed directly over the adhesion layer 38 . Due to the shape of the adhesion layer 38 and the passivation layer 28 , the seed layer 40 may have a depression 42 and an upper surface thereof.
  • the seed layer 40 is a base metal layer.
  • FIG. 2D illustrates the die 18 with a photoresist layer 32 formed over the passivation layer 28 .
  • the photoresist layer 32 may have a thickness of, for example, between 10 and 100 microns and may be selectively deposited or etched not to cove the portion of the passivation layer 28 covering the exposed portion bonding pad 22 , as illustrated in FIG. 2D , to form a trench 36 .
  • the trench 36 may be positioned directly above the bonding pad 22 .
  • the semiconductor die 10 may undergo a pre-wet and or pre-plating etch treatment prior to electroplating.
  • a pre-wet process may entail immersing semiconductor die 10 in a solution, such as DI water, and allowing exposure to the openings in semiconductor die 10 to the solution to avoid air bubbles and other defects in the semiconductor die 10 .
  • the pre-plating etch process may involve etching the openings in semiconductor die 10 with a solution, such as sulfuric acid, to remove native oxide.
  • FIG. 3 illustrates an electroplating apparatus 44 .
  • the electroplating apparatus 44 may include a liquid container 46 , a substrate support 48 within the container 46 , and a voltage supply 50 having a first electrode 52 and a second electrode 54 .
  • the container 46 may contain an inventive plating bath 56 so that both of the electrodes 52 and 54 are completely immersed therein.
  • the composition of the plating bath 56 is preferably an aqueous electroplating composition. It comprises copper, at least one acid, selected from sulfuric, methane sulfonic, amidosulfuric, aminoacetic, flouroboric, and mixtures thereof and the like, at least one halogen ion, and at least two agents selected from an accelerating agent and a suppressing agent.
  • a preferred range of copper ions in the plating bath 56 is from about 0.1 mole/L to about 1.5 mole/L, preferably from about 0.2 mole/IL to about 1 mole/L, and more preferably about 0.23 mole/L.
  • refractory metals examples include vanadium, niobium, tantalum, chromium, molybdenum, tungsten, cobalt, rhenium, and the like, and combinations thereof.
  • useful noble metals examples include gold, silver.
  • Other useful metals that may be combined with the copper include nickel, palladium, platinum, zinc, ruthenium, rhodium, cadmium, indium, and the like, and combinations thereof.
  • Other useful metals that may be combined with copper include alkaline earth metals such as magnesium and the like.
  • the composition of the plating bath 56 contains a preferred range of total metal deposit ions in a range from about 0.01 mole/L to about 1.5 mole/L, preferably from about 0.1 mole/L to about 1 mole/L, and most preferably about 0.23 mole/L.
  • the preferred ratio of copper to any other metal ions is in a range from about 1:1 to about 100: 1, preferably from about 2:1 to about 50:1.
  • composition of the plating bath 56 may contain mineral acids such as sulfuric, fluoboric, combinations thereof, and the like.
  • the plating bath 56 composition may also contain organic acids such as methane sulfonic (MSA), amidosulfuric, aminoacetic, combinations thereof, and the like.
  • the composition of the plating bath 56 may also contain combinations of mineral acids and organic acids.
  • a preferred concentration range of acids in the inventive plating bath composition I from about 0.1 mole/L to about 4 mole/L, preferably from about 0.15 mole/L to about 3.6 mole/L, and more preferably from about 0.2 mole/L to about 2.6 mole/L.
  • the effective acid content in the inventive plating bath composition mya be expressed by pH in a preferred range from about pH ⁇ 0 to about pH 14, prefer ably from about pH 0.4 to about pH 3.
  • the composition of the plating bath 56 may include at least one halogen such as fluorine, chlorine, bromine, iodine, and combinations thereof.
  • the composition of the plating bath 56 includes at least one halogen of chloride or bromine.
  • a preferred range of halogens in the plating bath 56 is the range from about 150 micron mole/L to about 3500 micron mole/L, preferably from about 1000 micron mole/L to about 3225 micron mole/L.
  • Accelerating agents may include a bath composition soluble disulfide or monsulfide organic compound including their mixtures.
  • accelerating agent is SPS, 1-propane sulfonic acid, 3,3′-dithio-bis, di-sodium salt, that may include bis-(soldium-sulfopropyl) -disulfide as the di-sodium salt.
  • Another accelerating agent is 1-propanesulfonic acid, 3-[(ethoxy-thiomethyl)thi],-potassium salt.
  • Another accelerating agent is a sulphonated or a phosphonated monosulfide, such as 3-mercapto-1-propanesulfonic acid (MPS) or 2-Mercaptoethanesulfonic acid (MES).
  • the accelerating agent comprises a phosphonated disulfide in a concentration range from about 2 micron mole/liter to about 500 micron mole/L, preferably from about 5 micron mole/L to about 250 micron mole/L.
  • accelerating agent is selected from a sulfonated monosulphide and a phosphonated monosulfide in a concentration range from about 2 micron mole/L to about 500 micron mole/L, preferably from about 5 micron mole/liter to about 250 micron mole/L.
  • the accelerating agent is selected from 3-mercapto-1-propanesulfonic acid, and 2-mercaptoethanesulfonic acid sodium salt in a concentration ranger from about 2 micron mole/L to about 500 micron mole/L, preferably from about 5 micron mole/L to about 250 micron mole/L.
  • the accelerating agent may also be selected from acylthioureas, thiocarboxylic acid amides, thiocarbamates, thiosemicarbazones, thiohydantoin, mixtures thereof, and the like in a concentration range from about 2 micron mole/L to about 500 micron mole/L, preferably from about 5 micron mole/L to about 250 micron mole/L.
  • the accelerating agent may comprise (O-Ethyldithiocarbonato)-S-(3-sulfopropyl)-ester, potassium salt.
  • the suppressing agent is provided in a concentration range from about 0.6 mole/L to about 600 micron mole/L, preferably from about 3 micron mole/L to about 300 micron/L.
  • the suppressing agent comprises a cross-linked polyamide in a concentration range from about 0.6 micron mole/L to about 600 micron mole/L, and wherein the cross-linked polyamide has an average molecular weight in a range from about 2,000 gram/mole to about 3,000 gram/mole.
  • the suppressing agent is selected from a polyether such as polyoxyethylene lauryl ether (POE).
  • POE polyoxyethylene lauryl ether
  • the suppressing agent may also be a glycol such as polyethylene glycol, polypropylene glycol, combinations thereof, and the like.
  • the suppressing agent may also be an aromatic compound such as alkoxylated beta-naphtol, alkyl naphthalene sulphonate, combinations, and the like.
  • the suppressing agent is selected from a polyether, a polyethylene, a naphtol, a sulphonate, a polyamine, a polyimid, and mixtures thereof.
  • the suppressing agent comprises a beta-naphtol having the structure: C 6 H 4 C 6 H 3 —O —(CH 2 CH 3 CH 2 O)n—(CH 2 —CH 2 O)m-H, Wherein n may be equal to 1 and wherein m may be equal to 1 and wherein the molecular weight is in the range from about 800 to about 1,500.
  • the suppressing agent may also be polyethylene oxide.
  • the suppressing agent may also be a nitrogen-containing compound such as polyimines, poly amines, polyamids, combinations and the like. Additionally, the suppressing agent may be cross-combinations of any two up to all of ethers, glycols, double aromatics, polyethylenes, and nitrogren-containing compounds.
  • the semiconductor substrate 10 may be placed on the substrate support 48 within the liquid container 46 of the electroplating apparatus 44 so that the semiconductor substrate 10 is completely immersed within the plating bath 56 .
  • the second electrode 54 may be connected to the semiconductor substrate 10 such that the second electrode 54 is electrically connected to each of the bonding pads 22 , or the adhesion layer 38 , as illustrated in FIG. 2D , and thus the exposed seed layer 40 .
  • the plating operation is initiated with a high plating current for the first portion of the plating.
  • the plating speed may depend on the current density. In an embodiment, a high plating current is greater than 1 micron/minute.
  • the deposition speed, or the rate in which the copper bump is formed initially, is approximately 65 microns/3600 seconds.
  • the remainder of the deposit is plated at another deposition rate.
  • the rate of the next plating event is approximately 118 microns/3600 seconds.
  • the time of the two-step deposition process may be between approximately 20 to 40 minutes. In an embodiment, the time of the two-step deposition process is approximately 30 minutes.
  • Operating conditions according to present invention may be selected depending upon a particular application.
  • the wafer may be contacted by the copper plating bath composition by moving the bath composition in relation to the wafer.
  • the wafer may be rotated.
  • a preferred rotation speed is in the range from about 0 to about 500 rpm.
  • the bath composition may be rotated and the wafer held in place. This embodiment allows for the elimination of moving parts in a wafer electroplating chamber with the advantage of reducing the likelihood of particulates contaminating the electroplating bath composition.
  • a plating tool containing 1-25 plating chambers is loaded with between 1 and 25 wafers and the inventive copper plating bath composition is flowed at a rate from about 3 L/min to about 60 L/min for each wafer.
  • the wafer rotation speed, relative to the solution is between 0 rpm and about 500 rpm.
  • the temperature is between about 7 C and about 35 C.
  • FIG. 4A illustrates one of the die 18 on the semiconductor substrate 10 as the semiconductor substrate 10 is immersed within the plating bath solution 56 illustrated in FIG. 3 .
  • particles of the accelerating agents and the suppressing agents are deposited on an upper surface of the seed layer 40 within the trench 36 .
  • cupric ions within the plating solution 56 may undergo a reduction process, or become reduced to metal, and become deposited, or “electroplated”, as is commonly understood in the art, on the seed layer 40 .
  • the suppressing particles improve wettability and “suppress” the plating rate to prevent a dendritic copper deposit from forming.
  • the accelerating agent may act to increase the electroplating rate. Because of the distribution of the suppressing and accelerating agents illustrated in FIG. 4A , the electroplating process may occur more quickly within the depression 42 on the upper surface of the seed layer 40 . As illustrated in FIG. 4B , a contact formation 58 may be formed during the electroplating process within the trench 36 . As shown a central portion of the contact formation 58 , located directly over the depression 42 may form more rapidly than portions of the contact formation 58 not located directly over the trench 42 .
  • FIG. 5A illustrates the semiconductor die 18 after the completion of the electroplating process illustrated in FIGS. 4A and 4B .
  • the contact formation 58 may be a copper bump as commonly understood in the art, and have a domed upper surface.
  • the semiconductor substrate 10 may then be removed from the plating bath 56 , and the photoresist layer 32 may then be removed by known processes, such as plasma ashing, and the adhesion 38 and seed 40 layers may be removed form in between the copper bumps 58 by known wet and dry etch processes, as illustrated in FIG. 5B .
  • the contact formation 58 may have a height 50 microns between 10 microns and 100 microns, and a surface roughness between 1 and 500 angstroms root mean square (RMS).
  • RMS root mean square
  • FIG. 6A illustrates the semiconductor substrate 10 after the removal of the photoresist layer 32 .
  • each of the die 18 may now have a plurality of contact formations 58 connected thereon, it should be understood that each die 18 may have literally hundreds of contact formations 58 thereon.
  • the die 18 may then be separated, or cingulated, from the semiconductor wafer 10 into separate microelectronic die 18 .
  • the die 18 may then beattached to a package substrate 62 .
  • the package substrate 62 may be square with, for example, side lengths of approximately 3 cm and a thickness of 3 mm.
  • the package substrate 62 may include alternating conducting and insulating layers formed therein, as is commonly understood in the art.
  • the package substrate 62 may include contact pads 64 formed on an upper surface thereof.
  • the contact pads 64 may be made of, for example, a conductive material such as solder or copper.
  • the contact pads 64 may be electrically connected to the conducting layers within the package substrate 62 .
  • the contact formations 58 may be connected to the contact pads 64 by known processes, such as reflow and thermocompression.
  • Ball Grid Array (BGA) solder ball contact formations 66 or other suitable contact formations may be contacted to a lower surface of package substrate 62 .
  • BGA Ball Grid Array
  • FIG. 8 illustrates the package substrate 62 attached to a printed circuit board 68 , such as a motherboard.
  • the motherboard 68 may be a large silicon plane having a plurality of sockets for securing and providing electrical signals to various package substrates, microelectronic die, and other electronic devices, as wells as conductive traces to electrically connect such devices, as is commonly understood in the art.
  • the BGA solder balls 66 may be heated and bonded to a socket on the motherboard 68 .
  • an underfill material such as an adhesive paste or epoxy, may be deposited between the die 18 and the package substrate 62 , as is commonly understood in the art.
  • the motherboard 68 may be installed in a computing system. Electric signals such as input/output(IO) signals, are then sent from the integrated circuit within the die 18 through the contact formations 58 , into the package substrate 62 , and into the computing system through the motherboard 68 . Power and ground signals may also be provided to the die 18 .
  • the computing system may send similar, or different, signals back to the integrated circuit within the die 18 through the motherboard 68 , the package substrate 62 , and the contact formations 58 .
  • One advantage is that because of the domed shape and the smooth upper surface of the copper bumps, when the die is attached to the package substrate, the likelihood of any solder material, underfill material, or air being trapped between the copper bump and the package substrate is reduced. Therefore, the mechanical strength of the bond between the copper bumps and the package substrates is increased, resulting in a more reliable electrical connection.
  • Another advantage is that a greater portion of the copper bumps may be an electrical contact with the package substrate, allowing the amount of current that is conducted through each copper bump to be maximized.
  • inventions may use a plating bath solution that does not contain the suppressing agent.
  • a two-step electroplating process may also be used.
  • the contact formations resulting from this alternative embodiment may not be domed or smooth to the same extent as the copper bump illustrated in FIG. 5B , as the upper surfaces thereof may be substantially flat.
  • the alternative embodiment may be useful to achieve flat contact formations without a center dimple.

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  • Chemical Kinetics & Catalysis (AREA)
  • Organic Chemistry (AREA)
  • Materials Engineering (AREA)
  • Electrochemistry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
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  • Crystallography & Structural Chemistry (AREA)
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  • Electroplating Methods And Accessories (AREA)

Abstract

The present invention relates to a plating bath consisting of a plating solution, accelerating agent and a suppressing agent and a method of forming contact formations on a semiconductor substrate. In an embodiment, the deposition of contact formations occurs in a two step deposition process wherein the deposition process has different deposition rates. Furthermore, the present invention includes a method of forming smooth, flat contact formations for use in electronic packages.

Description

    BACKGROUND
  • 1) Field of Invention
  • Embodiments of this invention relate to a method for the formation of contact formations, particularly for use on semiconductor substrate and a system utilizing such contact formations.
  • 2) Description of Related Art
  • Integrated circuits are formed on semiconductor substrates, such as wafers. The wafers are then sawed (or “singulated” or “diced”) into microelectronic die, also known as semiconductor chips, with each chip carrying a respective integrated circuit. Each semiconductor chip is then mounted to a package, or carrier, substrate. Often the packages are then mounted to circuit boards, such as motherboards, which may then be installed in computing systems.
  • The package substrate provides structural integrity to the semiconductor chips and are used to connect the integrated circuits electrically to the motherboard. On the side of the package substrate connected to the motherboard, there are contact formations, such as Ball Grid Array (BGA) solder balls, which are soldered to the motherboard. Electric signals are sent through the BGA solder balls into and out of the package. On the other side of the package substrate, there are other smaller contact formations used to connect the die to the package substrate. A modern trend for these contact formations is the use of “copper bumps” which are formed on bonding pads on the die. An underfill material, such as an epoxy or paste, may also be present between the die and the packages.
  • Copper bumps are typically formed using an electroplating process. The formation of the bumps begins within a depression on the surface of the die. This depression leads to a dimple or other formations on the surface of the copper bumps opposite the die. It is this dimpled surfaced which is used to connect the die to the packages.
  • This dimple may allow material, such as solder, underfill material, or even air, to get caught between the copper bump and the package substrate when the chip-to-package connections are made. This trapped material weakens the strength of the mechanical bond between the die and package substrates and results in a decrease in the maximum amount of current that can be conducted through the copper bumps.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1A is a top plan view of a semiconductor substrate.
  • FIG. 1B is a sectional view of the semiconductor substrate illustrated in FIG. 1A.
  • FIG. 2A is a cross-sectional side view of a microelectronic die, or a portion of the semiconductor substrate illustrated in FIG. 1A.
  • FIG. 2B is a cross-sectional side view of the microelectronic die with a passivation layer formed thereon.
  • FIG. 2C is a cross-sectional side view of the microelectronic die with an adhesion layer and a seed layer formed over the passivation layer.
  • FIG. 2D is a cross-sectional side view of the microelectronic die with a photoresist layer formed over the seed layer.
  • FIG. 3 is a cross-sectional schematic view of an electroplating apparatus.
  • FIGS. 4A and 4B are cross-sectional schematic views of the microelectronic die illustrating the formation of a contact formation within a trench in the photoresist layer.
  • FIGS. 5A and 5B are cross-sectional side views of the microelectronic die illustrating the removal of the photoresist layer.
  • FIG. 6 is a perspective view of the semiconductor substrate with a plurality of contact formations formed thereon.
  • FIG. 7A is a perspective view of the microelectronic die attached to the printed circuit board.
  • FIG. 8 is a perspective view of the package substrate attached to a printed circuit board.
    • DETAILED DESCRIPTION OF THE PRESENT INVENTION
  • The present invention relates to plating of a semiconductor structure by use of an inventive copper bath composition. Because of the inventive use of the copper bath composition, grain size is controlled and the presence of voids is reduced. Additionally, because of the inventive use of the copper baths composition, an article results in the form of an inventive contact structure.
  • FIGS. 1A and 1B illustrate a semiconductor substrate 10. The semiconductor substrate 10 may be a semiconductor wafer with a circular outer edge 12, having a diameter of, for example, 200 or 300 mm, and an indicator 14 thereon. The semiconductor substrate 10 may have a thickness 16 of, for example, 0.7 mm and a plurality of integrated circuits, separate amongst multiple die 18, formed thereon.
  • FIGS. 2A illustrates one of the die 18, or another portion of the semiconductor substrate 10 illustrated in FIGS. 1A and 1B. Each die 18 may include an integrated circuit, such a microprocessor formed therein, which may include multiple transistors and capacitors 20. The die 18 may also include a plurality of alternating insulating and conducting layers and be in what is known as a “flip-chip” configuration, as is commonly understood in the art. The die 18 may also include a bonding pad 22 formed within an upper surface thereof. The bonding pad may have, for example, a width 24 of approximately 10 microns and a thickness 26 of approximately 1 micron. The bonding pad 22 may be made of a conductive material, such as copper, and may be formed using electroplating. The bonding pad 22 may be part of the integrated circuit, or be electrically connected to the integrated circuit within the die 18.
  • FIG. 2B illustrates the die 18 with a passivation layer 28 formed thereon. The passivation layer 28 may have a thickness of, for example, approximately 2 microns and may be selectively deposited or etched so that a central portion of the bonding pad 22 remains exposed. Although not illustrated in the detail, the passivation layer 28 may include an upper layer made of, for example, polyimide or benzocyclobutene, formed over a lower layer made of a nitride, such as silicon nitride (SiN) or silicon oxide nitride (SiON).
  • FIG. 2C illustrates the die 18 with an adhesion layer 38 and a seed layer 40 deposited over the passivation layer 28 and the exposed portion of the bonding pad 22. The adhesion layer 38 may be made of a conductive material such as aluminum, titanium, titanium nitride, tantalum, tantalum nitride, tantalum silicon nitride, tungsten nitride, tungsten silicon nitride, titanium tungsten, nickel valadium, cobalt nickel tungsten phosphorous, cobalt nickel rhenium phosphorous, cobalt nickel tungsten boron, cobalt nickel rhenium boron, and or cobalt nickel rhenium boron phosphorous. The adhesion layer 38 may be deposited by such methods as plasma vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and electroless plating. The adhesion layer 38 may have a thickness of, for example, between 10 and 1000 nanometers and may be formed over the exposed portion of the bonding pad 22.
  • The seed layer 40 may be made of a conductive material such as, for example, copper, silver, gold, nickel, and or cobalt and may be deposited using PVD, CVD, ALD, electroless plating, and electroplating. The seed layer 40 may have a thickness of, for example, between 10 and 10,000 nanometers and may be formed directly over the adhesion layer 38. Due to the shape of the adhesion layer 38 and the passivation layer 28, the seed layer 40 may have a depression 42 and an upper surface thereof. In an embodiment, the seed layer 40 is a base metal layer.
  • FIG. 2D illustrates the die 18 with a photoresist layer 32 formed over the passivation layer 28. The photoresist layer 32 may have a thickness of, for example, between 10 and 100 microns and may be selectively deposited or etched not to cove the portion of the passivation layer 28 covering the exposed portion bonding pad 22, as illustrated in FIG. 2D, to form a trench 36. The trench 36 may be positioned directly above the bonding pad 22.
  • The semiconductor die 10 may undergo a pre-wet and or pre-plating etch treatment prior to electroplating. A pre-wet process may entail immersing semiconductor die 10 in a solution, such as DI water, and allowing exposure to the openings in semiconductor die 10 to the solution to avoid air bubbles and other defects in the semiconductor die 10. The pre-plating etch process may involve etching the openings in semiconductor die 10 with a solution, such as sulfuric acid, to remove native oxide.
  • FIG. 3 illustrates an electroplating apparatus 44. The electroplating apparatus 44 may include a liquid container 46, a substrate support 48 within the container 46, and a voltage supply 50 having a first electrode 52 and a second electrode 54. The container 46 may contain an inventive plating bath 56 so that both of the electrodes 52 and 54 are completely immersed therein.
  • The composition of the plating bath 56 is preferably an aqueous electroplating composition. It comprises copper, at least one acid, selected from sulfuric, methane sulfonic, amidosulfuric, aminoacetic, flouroboric, and mixtures thereof and the like, at least one halogen ion, and at least two agents selected from an accelerating agent and a suppressing agent.
  • A preferred range of copper ions in the plating bath 56 is from about 0.1 mole/L to about 1.5 mole/L, preferably from about 0.2 mole/IL to about 1 mole/L, and more preferably about 0.23 mole/L.
  • In addition to copper, other metals may be combined with the copper such as refractory metals, noble metals, and other transition metals. Examples of useful refractory metals that may be combined with the copper include vanadium, niobium, tantalum, chromium, molybdenum, tungsten, cobalt, rhenium, and the like, and combinations thereof. Examples of useful noble metals that may be combined with the copper include gold, silver. Other useful metals that may be combined with the copper include nickel, palladium, platinum, zinc, ruthenium, rhodium, cadmium, indium, and the like, and combinations thereof. Other useful metals that may be combined with copper include alkaline earth metals such as magnesium and the like. As a whole, the composition of the plating bath 56 contains a preferred range of total metal deposit ions in a range from about 0.01 mole/L to about 1.5 mole/L, preferably from about 0.1 mole/L to about 1 mole/L, and most preferably about 0.23 mole/L. The preferred ratio of copper to any other metal ions is in a range from about 1:1 to about 100: 1, preferably from about 2:1 to about 50:1.
  • Additionally, the composition of the plating bath 56 may contain mineral acids such as sulfuric, fluoboric, combinations thereof, and the like. The plating bath 56 composition may also contain organic acids such as methane sulfonic (MSA), amidosulfuric, aminoacetic, combinations thereof, and the like. The composition of the plating bath 56 may also contain combinations of mineral acids and organic acids. A preferred concentration range of acids in the inventive plating bath composition I from about 0.1 mole/L to about 4 mole/L, preferably from about 0.15 mole/L to about 3.6 mole/L, and more preferably from about 0.2 mole/L to about 2.6 mole/L. Alternatively, the effective acid content in the inventive plating bath composition mya be expressed by pH in a preferred range from about pH <0 to about pH 14, prefer ably from about pH 0.4 to about pH 3.
  • The composition of the plating bath 56 may include at least one halogen such as fluorine, chlorine, bromine, iodine, and combinations thereof. Preferably, the composition of the plating bath 56 includes at least one halogen of chloride or bromine. A preferred range of halogens in the plating bath 56 is the range from about 150 micron mole/L to about 3500 micron mole/L, preferably from about 1000 micron mole/L to about 3225 micron mole/L.
  • Accelerating agents may include a bath composition soluble disulfide or monsulfide organic compound including their mixtures. Once accelerating agent is SPS, 1-propane sulfonic acid, 3,3′-dithio-bis, di-sodium salt, that may include bis-(soldium-sulfopropyl) -disulfide as the di-sodium salt. Another accelerating agent is 1-propanesulfonic acid, 3-[(ethoxy-thiomethyl)thi],-potassium salt. Another accelerating agent is a sulphonated or a phosphonated monosulfide, such as 3-mercapto-1-propanesulfonic acid (MPS) or 2-Mercaptoethanesulfonic acid (MES).
  • In one embodiment, the accelerating agent comprises a phosphonated disulfide in a concentration range from about 2 micron mole/liter to about 500 micron mole/L, preferably from about 5 micron mole/L to about 250 micron mole/L.
  • In another embodiment, accelerating agent is selected from a sulfonated monosulphide and a phosphonated monosulfide in a concentration range from about 2 micron mole/L to about 500 micron mole/L, preferably from about 5 micron mole/liter to about 250 micron mole/L.
  • In another embodiment, the accelerating agent is selected from 3-mercapto-1-propanesulfonic acid, and 2-mercaptoethanesulfonic acid sodium salt in a concentration ranger from about 2 micron mole/L to about 500 micron mole/L, preferably from about 5 micron mole/L to about 250 micron mole/L.
  • The accelerating agent may also be selected from acylthioureas, thiocarboxylic acid amides, thiocarbamates, thiosemicarbazones, thiohydantoin, mixtures thereof, and the like in a concentration range from about 2 micron mole/L to about 500 micron mole/L, preferably from about 5 micron mole/L to about 250 micron mole/L. The accelerating agent may comprise (O-Ethyldithiocarbonato)-S-(3-sulfopropyl)-ester, potassium salt.
  • The suppressing agent is provided in a concentration range from about 0.6 mole/L to about 600 micron mole/L, preferably from about 3 micron mole/L to about 300 micron/L.
  • In one embodiment, the suppressing agent comprises a cross-linked polyamide in a concentration range from about 0.6 micron mole/L to about 600 micron mole/L, and wherein the cross-linked polyamide has an average molecular weight in a range from about 2,000 gram/mole to about 3,000 gram/mole.
  • In another embodiment, the suppressing agent is selected from a polyether such as polyoxyethylene lauryl ether (POE). The suppressing agent may also be a glycol such as polyethylene glycol, polypropylene glycol, combinations thereof, and the like.
  • The suppressing agent may also be an aromatic compound such as alkoxylated beta-naphtol, alkyl naphthalene sulphonate, combinations, and the like. In one embodiment, the suppressing agent is selected from a polyether, a polyethylene, a naphtol, a sulphonate, a polyamine, a polyimid, and mixtures thereof. In another embodiment, the suppressing agent comprises a beta-naphtol having the structure:
    C6H4C6H3—O —(CH2CH3CH2O)n—(CH2—CH2O)m-H,
    Wherein n may be equal to 1 and wherein m may be equal to 1 and wherein the molecular weight is in the range from about 800 to about 1,500. The suppressing agent may also be polyethylene oxide. The suppressing agent may also be a nitrogen-containing compound such as polyimines, poly amines, polyamids, combinations and the like. Additionally, the suppressing agent may be cross-combinations of any two up to all of ethers, glycols, double aromatics, polyethylenes, and nitrogren-containing compounds.
  • The semiconductor substrate 10 may be placed on the substrate support 48 within the liquid container 46 of the electroplating apparatus 44 so that the semiconductor substrate 10 is completely immersed within the plating bath 56. The second electrode 54 may be connected to the semiconductor substrate 10 such that the second electrode 54 is electrically connected to each of the bonding pads 22, or the adhesion layer 38, as illustrated in FIG. 2D, and thus the exposed seed layer 40. Referring again to FIG. 3, the plating operation is initiated with a high plating current for the first portion of the plating. The plating speed may depend on the current density. In an embodiment, a high plating current is greater than 1 micron/minute. The deposition speed, or the rate in which the copper bump is formed initially, is approximately 65 microns/3600 seconds. The remainder of the deposit is plated at another deposition rate. In an embodiment, the rate of the next plating event is approximately 118 microns/3600 seconds. The time of the two-step deposition process may be between approximately 20 to 40 minutes. In an embodiment, the time of the two-step deposition process is approximately 30 minutes.
  • Operating conditions according to present invention may be selected depending upon a particular application. The wafer may be contacted by the copper plating bath composition by moving the bath composition in relation to the wafer. For example, the wafer may be rotated. A preferred rotation speed is in the range from about 0 to about 500 rpm. Optionally, the bath composition may be rotated and the wafer held in place. This embodiment allows for the elimination of moving parts in a wafer electroplating chamber with the advantage of reducing the likelihood of particulates contaminating the electroplating bath composition.
  • In one embodiment, a plating tool containing 1-25 plating chambers is loaded with between 1 and 25 wafers and the inventive copper plating bath composition is flowed at a rate from about 3 L/min to about 60 L/min for each wafer. Where the wafer is rotated, or the solution is rotated, the wafer rotation speed, relative to the solution, is between 0 rpm and about 500 rpm.
  • Depending upon the specific chemical make-up of the plating bath composition and the preferred plating amount, the temperature is between about 7 C and about 35 C.
  • FIG. 4A illustrates one of the die 18 on the semiconductor substrate 10 as the semiconductor substrate 10 is immersed within the plating bath solution 56 illustrated in FIG. 3. As illustrated specifically in FIG. 4A, particles of the accelerating agents and the suppressing agents are deposited on an upper surface of the seed layer 40 within the trench 36.
  • As illustrated in FIGS. 4A and 4B, while the voltage is applied across the first and second electrodes, the cupric ions within the plating solution 56 may undergo a reduction process, or become reduced to metal, and become deposited, or “electroplated”, as is commonly understood in the art, on the seed layer 40.
  • During the electroplating process, the suppressing particles improve wettability and “suppress” the plating rate to prevent a dendritic copper deposit from forming. The accelerating agent may act to increase the electroplating rate. Because of the distribution of the suppressing and accelerating agents illustrated in FIG. 4A, the electroplating process may occur more quickly within the depression 42 on the upper surface of the seed layer 40. As illustrated in FIG. 4B, a contact formation 58 may be formed during the electroplating process within the trench 36. As shown a central portion of the contact formation 58, located directly over the depression 42 may form more rapidly than portions of the contact formation 58 not located directly over the trench 42.
  • FIG. 5A illustrates the semiconductor die 18 after the completion of the electroplating process illustrated in FIGS. 4A and 4B. The contact formation 58 may be a copper bump as commonly understood in the art, and have a domed upper surface. The semiconductor substrate 10 may then be removed from the plating bath 56, and the photoresist layer 32 may then be removed by known processes, such as plasma ashing, and the adhesion 38 and seed 40 layers may be removed form in between the copper bumps 58 by known wet and dry etch processes, as illustrated in FIG. 5B.
  • Still referring to FIG. 5B, the contact formation 58 may have a height 50 microns between 10 microns and 100 microns, and a surface roughness between 1 and 500 angstroms root mean square (RMS).
  • FIG. 6A illustrates the semiconductor substrate 10 after the removal of the photoresist layer 32. As illustrated, each of the die 18 may now have a plurality of contact formations 58 connected thereon, it should be understood that each die 18 may have literally hundreds of contact formations 58 thereon. The die 18 may then be separated, or cingulated, from the semiconductor wafer 10 into separate microelectronic die 18.
  • As illustrated in FIGS. 7A and 7B, the die 18 may then beattached to a package substrate 62. The package substrate 62 may be square with, for example, side lengths of approximately 3 cm and a thickness of 3 mm. The package substrate 62 may include alternating conducting and insulating layers formed therein, as is commonly understood in the art. As illustrated specifically in FIG. 7A, the package substrate 62 may include contact pads 64 formed on an upper surface thereof. The contact pads 64 may be made of, for example, a conductive material such as solder or copper. The contact pads 64 may be electrically connected to the conducting layers within the package substrate 62. The contact formations 58 may be connected to the contact pads 64 by known processes, such as reflow and thermocompression. As illustrated in FIG. 7B, Ball Grid Array (BGA) solder ball contact formations 66 or other suitable contact formations may be contacted to a lower surface of package substrate 62.
  • FIG. 8 illustrates the package substrate 62 attached to a printed circuit board 68, such as a motherboard. The motherboard 68 may be a large silicon plane having a plurality of sockets for securing and providing electrical signals to various package substrates, microelectronic die, and other electronic devices, as wells as conductive traces to electrically connect such devices, as is commonly understood in the art. Although not illustrated in detail, the BGA solder balls 66 may be heated and bonded to a socket on the motherboard 68. Additionally, an underfill material, such as an adhesive paste or epoxy, may be deposited between the die 18 and the package substrate 62, as is commonly understood in the art.
  • In use, the motherboard 68 may be installed in a computing system. Electric signals such as input/output(IO) signals, are then sent from the integrated circuit within the die 18 through the contact formations 58, into the package substrate 62, and into the computing system through the motherboard 68. Power and ground signals may also be provided to the die 18. The computing system may send similar, or different, signals back to the integrated circuit within the die 18 through the motherboard 68, the package substrate 62, and the contact formations 58.
  • One advantage is that because of the domed shape and the smooth upper surface of the copper bumps, when the die is attached to the package substrate, the likelihood of any solder material, underfill material, or air being trapped between the copper bump and the package substrate is reduced. Therefore, the mechanical strength of the bond between the copper bumps and the package substrates is increased, resulting in a more reliable electrical connection. Another advantage is that a greater portion of the copper bumps may be an electrical contact with the package substrate, allowing the amount of current that is conducted through each copper bump to be maximized.
  • Other embodiments may use a plating bath solution that does not contain the suppressing agent. A two-step electroplating process may also be used. The contact formations resulting from this alternative embodiment may not be domed or smooth to the same extent as the copper bump illustrated in FIG. 5B, as the upper surfaces thereof may be substantially flat. The alternative embodiment may be useful to achieve flat contact formations without a center dimple.

Claims (20)

1. A plating bath consisting of:
a plating solution; and
an accelerating agent in said plating solution; and
a suppressing agent in said plating solution.
2. The plating bath of claim 1, wherein said plating solution is selected from the group consisting of methane sulfonic, amidosulfuric, and aminoacetic.
3. The plating bath of claim 1, wherein said accelerating agent is selected from the group consisting of SPS, 1-propane sulfonic acid, 3,3′-dithio-bis, di-sodium salt; 1-propanesulfonic acid, 3-[(ethoxy-thiomethyl_thio],-potassium salt; phosphonated disulfide; sulphonated monosulfide; phosphonated monsulfide.
4. The plating bath of claim 1, wherein said suppressing agent is selected from the group consisting of polyoxyethylene lauryl ether; polyethylene glycol, polypropylene glycol; alkoxylated beta-naphtol; alkyl naphthalene sulphonate.
5. The plating bath of claim 1 further comprising copper.
6. The plating bath of claim 1 further comprising refractory metals, noble metals, transition metals, and halogens.
7. A plating bath consisting of:
a methane sulfonic; and
a sulphonated monosulfide; and
polyethylene glycol; and
copper; and
bromine.
8. The plating bath of claim 7 further consists of metal deposit ions.
9. The plating bath of claim 7 further consists of mineral acids.
10. A method consisting of:
forming an adhesion layer over the top surface of a semiconductor substrate;
forming a seed layer over the top surface of said adhesion layer;
patterning a first resist for a bump pattern over said seed layer;
exposing said semiconductor substrate to a plating bath, wherein said plating bath consists of a plating solution, accelerating agent, and a suppressing agent;
applying a current to said plating bath, wherein a first metal layer is deposited in said bump pattern;
removing said first resist;
etching a first portion of said adhesion layer and said seed layer, wherein the portion of said adhesion layer and said seed layer that remains is directly underneath said first metal layer.
11. The method of claim 10, wherein said first metal layer deposition occurs in a first step and a second step.
12. The method of claim 11, wherein said first step comprises applying a current to said plating bath, wherein said second metal layer is deposited at a rate approximately 69 microns/3600 seconds.
13. The method of claim 11, wherein said second step comprises applying a current to said plating bath, wherein said second metal layer is deposited at a rate approximately 118 microns/3600 seconds.
14. The method of claim 10, wherein said seed layer is a base metal layer.
15. The method of claim 14, wherein said base metal layer comprises titanium copper.
16. The method of claim 10, wherein said first metal layer comprises copper.
17. A method consisting of:
forming an adhesion layer over the top surface of a semiconductor substrate;
forming a base metal layer over the top surface of said adhesion layer;
patterning a first resist for a bump pattern over said base metal layer;
exposing said semiconductor substrate to a plating bath, wherein said plating bath consists of a plating solution, accelerating agent, and a suppressing agent;
applying a current to said plating bath, wherein a copper layer is deposited in said bump pattern in a first step and a second step and wherein said first step deposits said copper layer at a rate of approximately 69 microns/3600 seconds and wherein said second step deposits said copper layer at a rate of approximately 118 microns/3600 seconds;
removing said first resist;
etching a first portion of said adhesion layer and said base metal layer, wherein the portion of said adhesion layer and said base metal layer that remains is directly underneath said copper layer.
18. The method of claim 17, wherein said semiconductor substrate comprises a passivation layer, and wherein said passivation layer is on the top surface of said semiconductor substrate.
19. The method of claim 17, wherein said adhesion layer comprises titanium.
20. The method of claim 17 further consisting of a pre-wet process prior to forming an adhesion layer over the top surface of said semiconductor substrate.
US11/323,547 2005-12-30 2005-12-30 Method to modulate the surface roughness of a plated deposit and create fine-grained flat bumps Abandoned US20070158199A1 (en)

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