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US20070084730A1 - Plating apparatuses and processes - Google Patents

Plating apparatuses and processes Download PDF

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Publication number
US20070084730A1
US20070084730A1 US11/248,176 US24817605A US2007084730A1 US 20070084730 A1 US20070084730 A1 US 20070084730A1 US 24817605 A US24817605 A US 24817605A US 2007084730 A1 US2007084730 A1 US 2007084730A1
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US
United States
Prior art keywords
plating
station
wafer
post
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/248,176
Inventor
Kei-Wei Chen
Shih-Ho Lin
Yu-Ku Lin
Ying-Lang Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority to US11/248,176 priority Critical patent/US20070084730A1/en
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. reassignment TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, KEI-WEI, LIN, SHIH-HO, LIN, YU-KU, WANG, YING-LANG
Priority to TW095109584A priority patent/TWI314954B/en
Publication of US20070084730A1 publication Critical patent/US20070084730A1/en
Abandoned legal-status Critical Current

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    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D21/00—Processes for servicing or operating cells for electrolytic coating
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D21/00—Processes for servicing or operating cells for electrolytic coating
    • C25D21/12—Process control or regulation
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method

Definitions

  • the invention relates to semiconductor technology, and more specifically to plating apparatuses and processes.
  • the metal systems necessary to connect the devices and different layers are added to a chip by a process called metallization, comprising forming a dielectric layer over a semiconductor wafer, planarizing and patterning the dielectric layer to form trenches and/or vias, and filling the trenches and/or vias to form conductive wires and/or via plugs.
  • a chemical mechanical polishing process is then performed to planarize the surface of the wafer.
  • the wires and plugs are metal such as copper or copper alloys, they are typically formed by electroplating or electroless plating. The wires and plugs, however, cannot be completely adhered to the dielectric layer, forming gaps therebetween. Metal peel-off may occur at the gaps resulting from stress exertion in subsequent processes, negatively affecting the yield of the wafer production process and reliability of a product using a device from the wafer.
  • JP2002129385 discloses a plating method comprising a pre-treatment step, a plating step, and a post-treatment step, wherein the pre-treatment step comprises spraying water or a liquid comprising plating bath to wet a predetermined plating surface of a wafer, and the post-treatment step is to rinse the wafer.
  • the pre-treatment and post-treatment steps can be performed in the same post-treatment station of a plating apparatus used by the method. Further, a pre-treatment station may be added in the plating apparatus for the pre-treatment step.
  • the processing wafer is transferred to the post-treatment stations, followed by transfer to a plating station and transfer back to the post-treatment stations, thus, the operational flow of the plating apparatus is complicated and processing is prolonged.
  • the pre-treatment station is added to the plating apparatus, the apparatus must be modified, prolonging the process period, and negatively affecting process cost and throughput.
  • the invention provide plating apparatuses and processes utilizing the same, substantially preventing metal peel-off from dielectric layers without affecting process duration and operational flow of the apparatus, improving yield and reliability of the semiconductor device.
  • the invention provides a plating apparatus.
  • the apparatus comprises a plating station and a post plating treatment station adjacent to the plating station.
  • the plating station comprises at least one plating cell and provides a first environment therein with a first relative humidity (RH) higher than that of a clean room where the plating apparatus is disposed.
  • the post plating treatment station provides a second environment therein with a second RH lower than the first RH.
  • the invention further provides a plating process utilizing the plating apparatus.
  • a wafer comprising a recess thereon is provided.
  • a metal layer is then plated in the recess under a first relative humidity (RH) higher than that of a clean room for wafer fabrication.
  • RH relative humidity
  • a post plating treatment procedure is performed on the wafer under a second RH lower than the first RH.
  • FIG. 1 is a schematic diagram of a plating apparatus of the invention.
  • FIGS. 2A through 2C are schematic diagrams of a plating process of the invention.
  • the inventors discover that a plating bath tends to be hydrophobic resulting from macromolecular additions therein.
  • contact angle between the plating bath and a processing wafer is too large (typically between 20 and 70 degrees) to completely wet a predetermined plating surface of the wafer, resulting in gaps formed between the wafer and a metal layer subsequently formed by plating.
  • the subsequent plating apparatus and process can effectively decrease the contact angle between wafer and plating bath, substantially preventing gaps from forming between the wafer and a metal layer subsequently formed by plating.
  • FIG. 1 shows a schematic diagram of an embodiment of a plating apparatus.
  • the apparatus comprises a plating station 120 and post plating treatment station 130 adjacent to the plating station 120 .
  • the plating station 120 typically comprises at least one plating cell 125 .
  • the plating cell 125 comprises a plating bath therein.
  • the bath compositions depend on materials predetermined for plating of processed wafers. When plating copper on the wafer, for example, the main composition of the plating bath is copper sulphate and two or more macromolecular additives.
  • the plating station 120 may further comprise a robot arm for holding and transferring the processing wafers.
  • the plating station 120 provides a first environment with a first relative humidity (RH) higher than a clean room where the plating apparatus is disposed.
  • the first RH is preferably higher than 40%, and more preferably higher than 60%.
  • the first RH is preferably controlled by introduction of deionized vapor or wet nitrogen along an original atmosphere control system of the apparatus into the plating station 120 .
  • the post plating treatment station 130 typically comprises systems 131 and 132 .
  • the system 131 typically comprising spin/rinse/dry (SRD) and/or integrated bevel clean (IBC) sub-systems, is utilized following the metal plating to remove undesirable deposits from the backside and edges of the processing wafers.
  • the system 132 typically comprises a heating device to anneal the metal layer on the processing wafer.
  • the post plating treatment station 130 provides a second environment with a second RH lower than the first RH. In this embodiment, the second RH is between 30% and 40%.
  • the plating apparatus may further comprise a loading station 110 adjacent to the plating station 120 , and an unloading station 140 adjacent to the post plating treatment station 130 respectively for automatic wafer loading and unloading.
  • a wafer 200 comprising a recess 221 thereon is provided.
  • the wafer 200 comprises a substrate 210 and a dielectric layer on the substrate 210 , and the recess 221 exposes parts of the substrate 210 .
  • the recess 221 is a single damascene structure. In an alternative embodiment, the recess 221 is a dual damascene structure.
  • the wafer 200 can be loaded in the plating station 120 via the loading station 110 , followed by plating a metal layer 230 in the recess 221 using a method such as electroplating under the first RH.
  • the metal layer 230 is copper.
  • the first RH is preferably higher than 40% for wetting the wafer 200 to decrease the contact angle between the plating bath and the wafer 200 to less than 20 degrees, and thus, adhesion between the wafer 200 and the metal layer 120 is improved, improving the process yield and product reliability.
  • the first RH is more preferably higher than 60%.
  • the. contact angle between the plating bath and the wafer 200 is reduced to approximately 12 degrees, substantially preventing gaps between the plating bath and wafer 200 , and thus, process yield and product reliability is further improved.
  • wetting of the wafer 200 is achieved without additional steps or stations, further reducing process cost and increasing throughput compared to Ito et al.
  • the wafer 200 is transferred to the post plating treatment station 130 to perform a post plating treatment procedure thereon under the second RH.
  • the post plating treatment procedure typically comprises cleaning and drying the wafer 200 utilizing the system 131 , and annealing the metal layer 230 for improving electrical property utilizing the system 131 .
  • the processed wafer 200 can be unloaded utilizing the unloading station 130 .
  • plating yield is approximately 67.10%. In an embodiment of the invention, the plating yield is approximately 82.62%, effectively improving the process yield, and thus, product reliability can be effectively improved.
  • the inventors discover an additional advantage.
  • the conventional copper plating apparatus suffers copper sulphate particle contamination from the plating cell thereof.
  • the control of the first RH of the invention tends to decrease particle contamination, and thus, the preliminary maintenance (PM) frequency for the plating apparatus can be decreased, further decreasing process cost.
  • the results show the efficacy of the inventive plating apparatuses and methods in reducing contact angle between plating bath and a processing wafer, and preventing metal peel-off from the wafer, thus improving process yield and product reliability.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Materials Engineering (AREA)
  • Electrochemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Automation & Control Theory (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Chemically Coating (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Plating apparatuses and plating processes. Plating apparatuses includes a plating station and a post plating treatment station adjacent to the plating station. The plating station comprises at least one plating cell and provides a first environment therein with a first relative humidity (RH) higher than that of a clean room where the plating apparatus is disposed. The post plating treatment station provides a second environment therein with a second RH lower than the first RH.

Description

    BACKGROUND
  • The invention relates to semiconductor technology, and more specifically to plating apparatuses and processes.
  • In the back end of a semiconductor chip fabricating process, the metal systems necessary to connect the devices and different layers are added to a chip by a process called metallization, comprising forming a dielectric layer over a semiconductor wafer, planarizing and patterning the dielectric layer to form trenches and/or vias, and filling the trenches and/or vias to form conductive wires and/or via plugs. A chemical mechanical polishing process is then performed to planarize the surface of the wafer.
  • When the wires and plugs are metal such as copper or copper alloys, they are typically formed by electroplating or electroless plating. The wires and plugs, however, cannot be completely adhered to the dielectric layer, forming gaps therebetween. Metal peel-off may occur at the gaps resulting from stress exertion in subsequent processes, negatively affecting the yield of the wafer production process and reliability of a product using a device from the wafer.
  • JP2002129385, Ito et al., discloses a plating method comprising a pre-treatment step, a plating step, and a post-treatment step, wherein the pre-treatment step comprises spraying water or a liquid comprising plating bath to wet a predetermined plating surface of a wafer, and the post-treatment step is to rinse the wafer. The pre-treatment and post-treatment steps can be performed in the same post-treatment station of a plating apparatus used by the method. Further, a pre-treatment station may be added in the plating apparatus for the pre-treatment step. When the pre-treatment and post-treatment steps are performed in the same station, the processing wafer is transferred to the post-treatment stations, followed by transfer to a plating station and transfer back to the post-treatment stations, thus, the operational flow of the plating apparatus is complicated and processing is prolonged. When the pre-treatment station is added to the plating apparatus, the apparatus must be modified, prolonging the process period, and negatively affecting process cost and throughput.
    • SUMMARY
  • The invention provide plating apparatuses and processes utilizing the same, substantially preventing metal peel-off from dielectric layers without affecting process duration and operational flow of the apparatus, improving yield and reliability of the semiconductor device.
  • The invention provides a plating apparatus. The apparatus comprises a plating station and a post plating treatment station adjacent to the plating station. The plating station comprises at least one plating cell and provides a first environment therein with a first relative humidity (RH) higher than that of a clean room where the plating apparatus is disposed. The post plating treatment station provides a second environment therein with a second RH lower than the first RH.
  • The invention further provides a plating process utilizing the plating apparatus. First, a wafer comprising a recess thereon is provided. A metal layer is then plated in the recess under a first relative humidity (RH) higher than that of a clean room for wafer fabrication. Finally, a post plating treatment procedure is performed on the wafer under a second RH lower than the first RH.
  • Further scope of the applicability of the invention will become apparent from the detailed description given hereinafter. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The invention can be more fully understood by reading the subsequent detailed description in conjunction with the examples and references made to the accompanying drawings, which are given by way of illustration only, and thus are not limitative of the invention, and wherein:
  • FIG. 1 is a schematic diagram of a plating apparatus of the invention.
  • FIGS. 2A through 2C are schematic diagrams of a plating process of the invention.
    • DESCRIPTION
  • The following embodiments are intended to illustrate the invention more fully without limiting the scope of the claims, since numerous modifications and variations will be apparent to those skilled in this art.
  • The inventors discover that a plating bath tends to be hydrophobic resulting from macromolecular additions therein. Thus, contact angle between the plating bath and a processing wafer is too large (typically between 20 and 70 degrees) to completely wet a predetermined plating surface of the wafer, resulting in gaps formed between the wafer and a metal layer subsequently formed by plating. The subsequent plating apparatus and process can effectively decrease the contact angle between wafer and plating bath, substantially preventing gaps from forming between the wafer and a metal layer subsequently formed by plating.
  • FIG. 1 shows a schematic diagram of an embodiment of a plating apparatus. The apparatus comprises a plating station 120 and post plating treatment station 130 adjacent to the plating station 120.
  • The plating station 120 typically comprises at least one plating cell 125. The plating cell 125 comprises a plating bath therein. The bath compositions depend on materials predetermined for plating of processed wafers. When plating copper on the wafer, for example, the main composition of the plating bath is copper sulphate and two or more macromolecular additives. The plating station 120 may further comprise a robot arm for holding and transferring the processing wafers. The plating station 120 provides a first environment with a first relative humidity (RH) higher than a clean room where the plating apparatus is disposed. The first RH is preferably higher than 40%, and more preferably higher than 60%. The first RH is preferably controlled by introduction of deionized vapor or wet nitrogen along an original atmosphere control system of the apparatus into the plating station 120.
  • The post plating treatment station 130 typically comprises systems 131 and 132. The system 131, typically comprising spin/rinse/dry (SRD) and/or integrated bevel clean (IBC) sub-systems, is utilized following the metal plating to remove undesirable deposits from the backside and edges of the processing wafers. The system 132 typically comprises a heating device to anneal the metal layer on the processing wafer. The post plating treatment station 130 provides a second environment with a second RH lower than the first RH. In this embodiment, the second RH is between 30% and 40%.
  • The plating apparatus may further comprise a loading station 110 adjacent to the plating station 120, and an unloading station 140 adjacent to the post plating treatment station 130 respectively for automatic wafer loading and unloading.
  • Subsequently, a plating process utilizing the plating apparatus is disclosed.
  • In FIG. 2A, a wafer 200 comprising a recess 221 thereon is provided. Specifically, the wafer 200 comprises a substrate 210 and a dielectric layer on the substrate 210, and the recess 221 exposes parts of the substrate 210. In this embodiment, the recess 221 is a single damascene structure. In an alternative embodiment, the recess 221 is a dual damascene structure.
  • In FIG. 2B, and further referring to FIG. 1, the wafer 200 can be loaded in the plating station 120 via the loading station 110, followed by plating a metal layer 230 in the recess 221 using a method such as electroplating under the first RH. In this embodiment, the metal layer 230 is copper.
  • The first RH is preferably higher than 40% for wetting the wafer 200 to decrease the contact angle between the plating bath and the wafer 200 to less than 20 degrees, and thus, adhesion between the wafer 200 and the metal layer 120 is improved, improving the process yield and product reliability. The first RH is more preferably higher than 60%. In this embodiment, the. contact angle between the plating bath and the wafer 200 is reduced to approximately 12 degrees, substantially preventing gaps between the plating bath and wafer 200, and thus, process yield and product reliability is further improved. Thus, wetting of the wafer 200 is achieved without additional steps or stations, further reducing process cost and increasing throughput compared to Ito et al.
  • In FIG. 2C, and further referring to FIG. 1, the wafer 200 is transferred to the post plating treatment station 130 to perform a post plating treatment procedure thereon under the second RH. The post plating treatment procedure typically comprises cleaning and drying the wafer 200 utilizing the system 131, and annealing the metal layer 230 for improving electrical property utilizing the system 131. Finally, the processed wafer 200 can be unloaded utilizing the unloading station 130.
  • Conventional process data of electroplating a copper layer on a wafer show the plating yield is approximately 67.10%. In an embodiment of the invention, the plating yield is approximately 82.62%, effectively improving the process yield, and thus, product reliability can be effectively improved.
  • Further, the inventors discover an additional advantage. The conventional copper plating apparatus suffers copper sulphate particle contamination from the plating cell thereof. The control of the first RH of the invention tends to decrease particle contamination, and thus, the preliminary maintenance (PM) frequency for the plating apparatus can be decreased, further decreasing process cost.
  • Thus, the results show the efficacy of the inventive plating apparatuses and methods in reducing contact angle between plating bath and a processing wafer, and preventing metal peel-off from the wafer, thus improving process yield and product reliability.
  • While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. It is therefore intended that the following claims be interpreted as covering all such alteration and modifications as fall within the true spirit and scope of the invention.

Claims (14)

1. A plating apparatus, comprising:
a plating station, comprising at least one plating cell, providing a first environment therein with a first relative humidity (RH) higher than that of a clean room where the plating apparatus is disposed; and
a post plating treatment station adjacent to the plating station, providing a second environment therein with a second RH lower than the first RH.
2. The apparatus as claimed in claim 1, further comprising:
a loading station adjacent to the plating station; and
an unloading station adjacent to the post plating treatment station.
3. The apparatus as claimed in claim 1, wherein the first RH is higher than 40%.
4. The apparatus as claimed in claim 1, wherein the first RH is higher than 60%.
5. The apparatus as claimed in claim 1, wherein the second RH is between 30% and 40%.
6. The apparatus as claimed in claim 1, wherein the first RH is controlled by introduction of deionized vapor or wet nitrogen into the plating station.
7. A plating process, comprising:
providing a wafer comprising a recess thereon;
plating a metal layer in the recess under a first relative humidity (RH) higher than that of a clean room for wafer fabrication; and
performing a post plating treatment procedure on the wafer under a second RH lower than the first RH.
8. The method as claimed in claim 7, wherein the post plating treatment procedure further comprises:
Cleaning and drying the wafer; and
annealing the metal layer.
9. The method as claimed in claim 7, wherein the first RH is higher than 40%.
10. The method as claimed in claim 7, wherein the first RH is higher than 60%.
11. The method as claimed in claim 7, wherein the second RH is between 30% and 40%.
12. The method as claimed in claim 7, wherein the first RH is controlled by introduction of deionized vapor or wet nitrogen.
13. The method as claimed in claim 7, wherein the metal layer is substantially copper.
14. The method as claimed in claim 7, wherein the metal layer is formed by electroplating.
US11/248,176 2005-10-13 2005-10-13 Plating apparatuses and processes Abandoned US20070084730A1 (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4168960A (en) * 1978-04-18 1979-09-25 Westinghouse Electric Corp. Method of making a glass encapsulated diode
US5423974A (en) * 1991-09-17 1995-06-13 Hydro-Quebec Plastic supported metallic sheets obtained by metallization-plating
US20050145267A1 (en) * 2002-09-30 2005-07-07 Lam Research Corp. Controls of ambient environment during wafer drying using proximity head
US20050160990A1 (en) * 2004-01-26 2005-07-28 Dmitry Lubomirsky Apparatus for electroless deposition of metals onto semiconductor substrates
US7147827B1 (en) * 1998-05-01 2006-12-12 Applied Materials, Inc. Chemical mixing, replenishment, and waste management system
US20070080067A1 (en) * 2005-10-07 2007-04-12 Applied Materials, Inc. Pre-treatment to eliminate the defects formed during electrochemical plating

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4168960A (en) * 1978-04-18 1979-09-25 Westinghouse Electric Corp. Method of making a glass encapsulated diode
US5423974A (en) * 1991-09-17 1995-06-13 Hydro-Quebec Plastic supported metallic sheets obtained by metallization-plating
US7147827B1 (en) * 1998-05-01 2006-12-12 Applied Materials, Inc. Chemical mixing, replenishment, and waste management system
US20050145267A1 (en) * 2002-09-30 2005-07-07 Lam Research Corp. Controls of ambient environment during wafer drying using proximity head
US20050160990A1 (en) * 2004-01-26 2005-07-28 Dmitry Lubomirsky Apparatus for electroless deposition of metals onto semiconductor substrates
US20070080067A1 (en) * 2005-10-07 2007-04-12 Applied Materials, Inc. Pre-treatment to eliminate the defects formed during electrochemical plating

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Publication number Publication date
TWI314954B (en) 2009-09-21
TW200714744A (en) 2007-04-16

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Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIW

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