US20060003267A1 - Nano-structure and method of fabricating nano-structures - Google Patents
Nano-structure and method of fabricating nano-structures Download PDFInfo
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- US20060003267A1 US20060003267A1 US11/215,985 US21598505A US2006003267A1 US 20060003267 A1 US20060003267 A1 US 20060003267A1 US 21598505 A US21598505 A US 21598505A US 2006003267 A1 US2006003267 A1 US 2006003267A1
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- 239000002086 nanomaterial Substances 0.000 title claims abstract description 45
- 238000004519 manufacturing process Methods 0.000 title description 12
- 239000000463 material Substances 0.000 claims abstract description 58
- 238000000034 method Methods 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000000151 deposition Methods 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 239000010931 gold Substances 0.000 description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 7
- 229910052737 gold Inorganic materials 0.000 description 7
- 229910052715 tantalum Inorganic materials 0.000 description 5
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 5
- 230000032798 delamination Effects 0.000 description 4
- 230000003628 erosive effect Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C4/00—Coating by spraying the coating material in the molten state, e.g. by flame, plasma or electric discharge
- C23C4/12—Coating by spraying the coating material in the molten state, e.g. by flame, plasma or electric discharge characterised by the method of spraying
- C23C4/123—Spraying molten metal
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C4/00—Coating by spraying the coating material in the molten state, e.g. by flame, plasma or electric discharge
- C23C4/18—After-treatment
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/60—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape characterised by shape
- C30B29/68—Crystals with laminate structure, e.g. "superlattices"
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/40—Treatment after imagewise removal, e.g. baking
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0104—Tools for processing; Objects used during processing for patterning or coating
- H05K2203/0117—Pattern shaped electrode used for patterning, e.g. plating or etching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/025—Abrading, e.g. grinding or sand blasting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
Definitions
- problems can be encountered when a nano-structure is formed that includes a plurality layers of material that are to be planarized. Such problems may include, for example, fraying, delamination, erosion, dishing, and rounding.
- Desired is a method for forming nano-structures that overcome or reduce such problems.
- a nano-structure comprises a substrate, a feature formed on the substrate that extends upwardly from a surface of the substrate, layers of material that overlie the substrate surface and at least a portion of the feature, and an exposed surface comprising a top surface of the feature and edges of the layers of material, wherein portions of selected layers of material have been etched away to form trenches adjacent the top surface of the top surface of the feature.
- a method for fabricating a nano-structure comprises forming a feature on a substrate, depositing multiple layers of material over the substrate and feature to form a multi-layer stack, depositing a film over the multi-layer stack, removing a portion of the film and the multi-layer stack to expose edges of the layers of material, and removing portions of the layers of material to form trenches at a surface of the nano-structure.
- FIG. 1 is an end view of an embodiment of a nano-structure in an initial stage of fabrication.
- FIG. 2 is a top perspective view of the nano-structure shown in FIG. 1 .
- FIG. 3 is an end view of the nano-structure of FIG. 1 in a later stage of fabrication.
- FIG. 4 is an end view of the nano-structure of FIG. 1 in yet a later stage of fabrication.
- FIG. 5 is an end view the nano-structure of FIG. 1 in yet another later stage of fabrication.
- FIG. 6 is an end view of an embodiment of a completed nano-structure.
- FIG. 7 is a detail view of trenches formed in the nano-structure of FIG. 6 .
- FIG. 8 is a flow diagram of an embodiment of a method for fabricating a nano-structure.
- a nano-structure and a method for fabricating nano-structures are disclosed. According to at least one embodiment of the method, multiple layers of material that overlie a feature that is formed on the surface of a substrate are covered by a sacrificial film that enables planarization of the multiple layers while reducing or preventing one or more of fraying, delamination, erosion, dishing, and rounding.
- FIG. 1 illustrates an embodiment of a nano-structure 100 in an initial stage of fabrication.
- the nano-structure 100 includes a substrate 102 that, for example, comprises a silicon wafer.
- a feature 106 that, in the embodiment shown in FIG. 1 , comprises a dielectric bump.
- the bump 106 can be composed of silicon oxide and can be formed using any one of various fabrication methods.
- the bump 106 can be formed by depositing a layer of silicon oxide (not shown), and etching the silicon oxide away to leave a bump having the general shape and configuration illustrated in FIG. 1 .
- the bump 106 has a trapezoidal cross-section that is defined by a base 108 , opposed sides 110 , and a top 112 .
- the base 108 is larger than the top 112
- the opposed sides 110 extend diagonally or obliquely toward each other from the base to the top.
- the bump 106 is elongated (as compared to the sides 110 and top 112 ) so as to extend a relatively long distance across the surface 104 of the substrate 102 .
- the feature 106 formed on the substrate 102 is described and illustrated as comprising a bump having a trapezoidal cross-section, other configurations and shapes are possible.
- the nano-structure 100 is constructed on a nano-scale.
- the bump 106 has a height dimension, h, that ranges from approximately 200 nanometers (nm) to approximately 5000 nm, and a width dimension, w, that ranges from approximately 250 nm to 100 microns ( ⁇ m).
- the bump 106 has a height of approximately 2500 nm and a width of approximately 5000 nm.
- the feature has been illustrated and described as a bump, the feature could take substantially any other form including, for example, a step.
- the feature could have other dimensions, which may only be limited by the size of the substrate.
- multiple overlapping layers 114 of material are deposited over the substrate 102 and the bump 106 to form a multi-layered stack 116 of material having opposed comers 118 .
- the layers can alternate between the types of material. For instance, a first layer of gold can be deposited, followed by a layer of tantalum, followed by a further layer of gold, followed by a further layer of tantalum, etc., until a desired number of alternating layers 114 of material have been deposited.
- Such deposition can be achieved using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or another process.
- CVD chemical vapor deposition
- PVD physical vapor deposition
- ALD atomic layer deposition
- other types of materials can be used to form the layers 114 .
- Example alternative materials include titanium nitride, silicon, silicon oxide, and metal oxides.
- each layer 114 is approximately 10 Angstoms ( ⁇ ) to approximately 1000 ⁇ thick.
- each layer 114 can be approximately 500 ⁇ thick.
- multiple trenches which are useful for nano-imprinting (for example), can be formed by planarizing the layers 114 above the bump 106 to yield a bump that has multiple layers of material along both sides of its length. Assuming an alternating arrangement of materials such as that described above, multiple trenches can be formed by etching away one of the materials (i.e., multiple layers of that material), leaving trenches defined by the layers of material that were not etched away. Unfortunately, such planarization often results in one or more of fraying, delamination, erosion, dishing, and rounding using known techniques.
- a sacrificial or planarizing film 120 of material is deposited over the multiple layers 114 prior to planarization, as is shown in FIG. 4 .
- the planarizing film 120 comprises a thick layer of silicon oxide.
- examples of other materials that can be used for the planarizing film. 120 include amorphous silicon and spin-on-glass.
- the planarizing film 120 has a thickness that will result in a film height that equals or exceeds the height of the multi-layered stack 116 (see FIG. 4 ). With such a configuration, the low-topography points of the structure 100 are brought above the bump 106 and the multi-layered stack 116 that has been deposited thereon.
- the planarizing film 120 has a thickness of approximately 200 nm to approximately 10 ⁇ m.
- the film 120 can be approximately 2.5 micons ( ⁇ m) thick.
- the planarizing film 120 and the top of the multi-layered stack 116 can be removed. Specifically, as is indicated in FIG. 5 , the film 120 and top of the stack 116 are removed, for example using a chemical-mechanical planarization (CMP) process, such that the top portion of the bump 106 is exposed. Alternatively, mechanical or chemical-mechanical polishing can be used to achieve this result. As is indicated in FIG. 5 , little or no fraying, delamination, erosion, or dishing has occurred. In addition, the comers 118 of the multi-layered stack 116 are minimized due to the provision of the planarizing film 120 .
- CMP chemical-mechanical planarization
- trenches 124 can be formed by etching one or more of the layers 114 of material of the multi-layer stack 116 .
- the stack 116 is composed of alternating materials
- one of the materials can be selectively etched away to produce trenches 124 that are defined by the remaining layers.
- FIG. 7 illustrates such an embodiment in detail.
- the tantalum layers (Ta) remain intact and extend to the surface 122 , while the gold layers (Au) have been etched away to define the trenches 124 .
- the trenches 124 are defined by side walls 126 (e.g., of tantalum) and bases 128 (e.g., of gold).
- the trenches 124 have widths equal to the thickness of the layers (in this example gold layers) that have been etched away.
- the structure that results from the above-described fabrication is a comb-like structure in which diagonal or oblique trenches 124 are formed in the surface of the nano-structure 100 .
- multiple parallel, oblique trenches 124 are formed on both sides of the bump 106 such that the trenches are angled toward each other as they are traversed upward from the bases 126 to the surface 122 .
- each trench 124 forms an angle, ⁇ , of approximately 30 to approximately 90 degrees relative to the surface 122 (see FIG. 7 ).
- the structure 100 can, for example, be used for nano-imprinting. In such a case, the nano-structure 100 may be considered to be a nano-imprinting structure.
- a feature such as a dielectric bump
- the feature can be formed by, for instance, depositing a layer of material on top of the substrate, and etching away a portion of the deposited layer.
- multiple layers of material are deposited over the substrate and feature to form a multi-layer stack, as indicated in block 802 .
- two or more different types of materials are deposited in an alternating fashion.
- a sacrificial film is deposited over the multi-layer stack such that the height of the film equals or exceeds the height of the multi-layer stack, including the portion of the stack that overlies the feature.
- a portion of the film and the stack is removed, as indicated in block 806 , for example using a planarization process.
- portions of various layers of the multi-layer stack are removed to form trenches in a surface that results when the portion of the film and stack are removed (in block 806 ).
- the portions of the layers can be removed using a selective etching process.
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Abstract
Description
- This application is a continuation-in-part of copending U.S. utility application entitled, “Fabrication and Use of Superlattice,” having Ser. No. 10/817,729, filed Apr. 2, 2004, which is entirely incorporated herein by reference.
- Although fabrication of structures on a “nano” scale has been practiced for several years, there are still many challenges that are to be overcome to enable manufacture of desired structures.
- For instance, problems can be encountered when a nano-structure is formed that includes a plurality layers of material that are to be planarized. Such problems may include, for example, fraying, delamination, erosion, dishing, and rounding.
- Desired is a method for forming nano-structures that overcome or reduce such problems.
- In one embodiment, a nano-structure comprises a substrate, a feature formed on the substrate that extends upwardly from a surface of the substrate, layers of material that overlie the substrate surface and at least a portion of the feature, and an exposed surface comprising a top surface of the feature and edges of the layers of material, wherein portions of selected layers of material have been etched away to form trenches adjacent the top surface of the top surface of the feature.
- In one embodiment, a method for fabricating a nano-structure comprises forming a feature on a substrate, depositing multiple layers of material over the substrate and feature to form a multi-layer stack, depositing a film over the multi-layer stack, removing a portion of the film and the multi-layer stack to expose edges of the layers of material, and removing portions of the layers of material to form trenches at a surface of the nano-structure.
- The disclosed nano-structure and method can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale.
-
FIG. 1 is an end view of an embodiment of a nano-structure in an initial stage of fabrication. -
FIG. 2 is a top perspective view of the nano-structure shown inFIG. 1 . -
FIG. 3 is an end view of the nano-structure ofFIG. 1 in a later stage of fabrication. -
FIG. 4 is an end view of the nano-structure ofFIG. 1 in yet a later stage of fabrication. -
FIG. 5 is an end view the nano-structure ofFIG. 1 in yet another later stage of fabrication. -
FIG. 6 is an end view of an embodiment of a completed nano-structure. -
FIG. 7 is a detail view of trenches formed in the nano-structure ofFIG. 6 . -
FIG. 8 is a flow diagram of an embodiment of a method for fabricating a nano-structure. - Disclosed is a nano-structure and a method for fabricating nano-structures. According to at least one embodiment of the method, multiple layers of material that overlie a feature that is formed on the surface of a substrate are covered by a sacrificial film that enables planarization of the multiple layers while reducing or preventing one or more of fraying, delamination, erosion, dishing, and rounding.
- Referring now in more detail to the drawings, in which like numerals indicate corresponding parts throughout the several views,
FIG. 1 illustrates an embodiment of a nano-structure 100 in an initial stage of fabrication. As is indicated inFIG. 1 , the nano-structure 100 includes asubstrate 102 that, for example, comprises a silicon wafer. Formed on asurface 104 of thesubstrate 102 is afeature 106 that, in the embodiment shown inFIG. 1 , comprises a dielectric bump. Thebump 106 can be composed of silicon oxide and can be formed using any one of various fabrication methods. For example, thebump 106 can be formed by depositing a layer of silicon oxide (not shown), and etching the silicon oxide away to leave a bump having the general shape and configuration illustrated inFIG. 1 . - In this embodiment, the
bump 106 has a trapezoidal cross-section that is defined by abase 108, opposedsides 110, and a top 112. As is apparent fromFIG. 1 , thebase 108 is larger than thetop 112, and theopposed sides 110 extend diagonally or obliquely toward each other from the base to the top. As is shown inFIG. 2 , thebump 106 is elongated (as compared to thesides 110 and top 112) so as to extend a relatively long distance across thesurface 104 of thesubstrate 102. Although thefeature 106 formed on thesubstrate 102 is described and illustrated as comprising a bump having a trapezoidal cross-section, other configurations and shapes are possible. - As is described above, the nano-
structure 100 is constructed on a nano-scale. By way of example, thebump 106 has a height dimension, h, that ranges from approximately 200 nanometers (nm) to approximately 5000 nm, and a width dimension, w, that ranges from approximately 250 nm to 100 microns (μm). In one embodiment, thebump 106 has a height of approximately 2500 nm and a width of approximately 5000 nm. - It is noted that, although the feature has been illustrated and described as a bump, the feature could take substantially any other form including, for example, a step. Moreover, although specific example dimensions have been described, those dimensions are only examples, and the feature could have other dimensions, which may only be limited by the size of the substrate.
- Referring next to
FIGS. 3-6 , various other steps of the fabrication of the nano-structure 100 will be described. Beginning withFIG. 3 , multiple overlappinglayers 114 of material (e.g., metal) are deposited over thesubstrate 102 and thebump 106 to form amulti-layered stack 116 of material having opposedcomers 118. When more than one type of material is used to form thelayers 114, such as two types of material, the layers can alternate between the types of material. For instance, a first layer of gold can be deposited, followed by a layer of tantalum, followed by a further layer of gold, followed by a further layer of tantalum, etc., until a desired number ofalternating layers 114 of material have been deposited. Depending on the material, such deposition can be achieved using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or another process. Notably, other types of materials can be used to form thelayers 114. Example alternative materials include titanium nitride, silicon, silicon oxide, and metal oxides. - In the embodiment shown in the figures, nine
layers 114 of material have been deposited. By way of example, eachlayer 114 is approximately 10 Angstoms (Å) to approximately 1000 Å thick. For instance, in one embodiment, eachlayer 114 can be approximately 500 Å thick. - With the structure illustrated in
FIG. 3 , multiple trenches, which are useful for nano-imprinting (for example), can be formed by planarizing thelayers 114 above thebump 106 to yield a bump that has multiple layers of material along both sides of its length. Assuming an alternating arrangement of materials such as that described above, multiple trenches can be formed by etching away one of the materials (i.e., multiple layers of that material), leaving trenches defined by the layers of material that were not etched away. Unfortunately, such planarization often results in one or more of fraying, delamination, erosion, dishing, and rounding using known techniques. - To avoid such problems, a sacrificial or
planarizing film 120 of material is deposited over themultiple layers 114 prior to planarization, as is shown inFIG. 4 . By way of example, theplanarizing film 120 comprises a thick layer of silicon oxide. Examples of other materials that can be used for the planarizing film. 120 include amorphous silicon and spin-on-glass. Regardless of the particular material that is used, theplanarizing film 120 has a thickness that will result in a film height that equals or exceeds the height of the multi-layered stack 116 (seeFIG. 4 ). With such a configuration, the low-topography points of thestructure 100 are brought above thebump 106 and themulti-layered stack 116 that has been deposited thereon. This enables a non-zero removal rate of the low points to be above the height of themulti-layered stack 116. In some embodiments, theplanarizing film 120 has a thickness of approximately 200 nm to approximately 10 μm. For example, thefilm 120 can be approximately 2.5 micons (μm) thick. - At this point, the
planarizing film 120 and the top of themulti-layered stack 116 can be removed. Specifically, as is indicated inFIG. 5 , thefilm 120 and top of thestack 116 are removed, for example using a chemical-mechanical planarization (CMP) process, such that the top portion of thebump 106 is exposed. Alternatively, mechanical or chemical-mechanical polishing can be used to achieve this result. As is indicated inFIG. 5 , little or no fraying, delamination, erosion, or dishing has occurred. In addition, thecomers 118 of themulti-layered stack 116 are minimized due to the provision of theplanarizing film 120. - At this point, multiple trenches can be formed in the
new surface 122, and the exposed edges of thestacked layers 114, that results from the planarization process. Referring toFIG. 6 ,trenches 124 can be formed by etching one or more of thelayers 114 of material of themulti-layer stack 116. For instance, in cases in which thestack 116 is composed of alternating materials, one of the materials (and therefore multiple layers 114) can be selectively etched away to producetrenches 124 that are defined by the remaining layers. To cite a specific example, when alternating layers of tantalum and gold are deposited, a portion of the gold layers can be etched away to define thetrenches 124.FIG. 7 illustrates such an embodiment in detail. As is shown in that figure, the tantalum layers (Ta) remain intact and extend to thesurface 122, while the gold layers (Au) have been etched away to define thetrenches 124. As is further shown in the figure, thetrenches 124 are defined by side walls 126 (e.g., of tantalum) and bases 128 (e.g., of gold). Thetrenches 124 have widths equal to the thickness of the layers (in this example gold layers) that have been etched away. - The structure that results from the above-described fabrication is a comb-like structure in which diagonal or
oblique trenches 124 are formed in the surface of the nano-structure 100. In particular, multiple parallel,oblique trenches 124 are formed on both sides of thebump 106 such that the trenches are angled toward each other as they are traversed upward from thebases 126 to thesurface 122. By way of example, eachtrench 124 forms an angle, α, of approximately 30 to approximately 90 degrees relative to the surface 122 (seeFIG. 7 ). As is mentioned above, thestructure 100 can, for example, be used for nano-imprinting. In such a case, the nano-structure 100 may be considered to be a nano-imprinting structure. - An embodiment of a method for fabricating a nano-structure can be summarized as provided in
FIG. 8 . Beginning withblock 800, a feature, such as a dielectric bump, is formed on a substrate. The feature can be formed by, for instance, depositing a layer of material on top of the substrate, and etching away a portion of the deposited layer. Next, multiple layers of material are deposited over the substrate and feature to form a multi-layer stack, as indicated inblock 802. By way of example, two or more different types of materials are deposited in an alternating fashion. - Referring next to block 804, a sacrificial film is deposited over the multi-layer stack such that the height of the film equals or exceeds the height of the multi-layer stack, including the portion of the stack that overlies the feature. Once the film has been deposited, a portion of the film and the stack is removed, as indicated in
block 806, for example using a planarization process. - Finally, as is indicated in
block 808, portions of various layers of the multi-layer stack are removed to form trenches in a surface that results when the portion of the film and stack are removed (in block 806). By way of example, the portions of the layers can be removed using a selective etching process.
Claims (27)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/215,985 US20060003267A1 (en) | 2004-04-02 | 2005-08-31 | Nano-structure and method of fabricating nano-structures |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/817,729 US7407738B2 (en) | 2004-04-02 | 2004-04-02 | Fabrication and use of superlattice |
| US11/215,985 US20060003267A1 (en) | 2004-04-02 | 2005-08-31 | Nano-structure and method of fabricating nano-structures |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US10/817,729 Continuation-In-Part US7407738B2 (en) | 2004-04-02 | 2004-04-02 | Fabrication and use of superlattice |
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| Publication Number | Publication Date |
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| US20060003267A1 true US20060003267A1 (en) | 2006-01-05 |
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| US10/817,729 Active 2025-11-25 US7407738B2 (en) | 2004-04-02 | 2004-04-02 | Fabrication and use of superlattice |
| US11/215,985 Abandoned US20060003267A1 (en) | 2004-04-02 | 2005-08-31 | Nano-structure and method of fabricating nano-structures |
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| US10/817,729 Active 2025-11-25 US7407738B2 (en) | 2004-04-02 | 2004-04-02 | Fabrication and use of superlattice |
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| Country | Link |
|---|---|
| US (2) | US7407738B2 (en) |
| EP (1) | EP1735820B1 (en) |
| JP (1) | JP4796569B2 (en) |
| CN (1) | CN1961259B (en) |
| AT (1) | ATE467151T1 (en) |
| DE (1) | DE602005021082D1 (en) |
| TW (1) | TWI389171B (en) |
| WO (1) | WO2005096351A2 (en) |
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| US20050221235A1 (en) * | 2004-04-02 | 2005-10-06 | Pavel Kornilovich | Fabrication and use of superlattice |
| US20070178229A1 (en) * | 2006-01-30 | 2007-08-02 | Bergendahl Albert S | Systems and methods for forming magnetic nanocomposite materials |
| US20170334255A1 (en) * | 2013-05-22 | 2017-11-23 | Kevin McAllister | Ball assembly for measuring tongue weight of a trailer |
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| US8695501B2 (en) * | 2005-01-28 | 2014-04-15 | Hewlett-Packard Development Company, L.P. | Method of forming a contact printing stamp |
| US7662299B2 (en) | 2005-08-30 | 2010-02-16 | Micron Technology, Inc. | Nanoimprint lithography template techniques for use during the fabrication of a semiconductor device and systems including same |
| WO2007097380A1 (en) | 2006-02-21 | 2007-08-30 | Nikon Corporation | Pattern forming apparatus, pattern forming method, mobile object driving system, mobile body driving method, exposure apparatus, exposure method and device manufacturing method |
| CN103862032B (en) * | 2014-02-26 | 2016-08-03 | 国家纳米科学中心 | The nucleocapsid noble metal nano rod of four directions superlattices and self-assembling method thereof |
| US11294435B2 (en) * | 2018-12-14 | 2022-04-05 | Dell Products L.P. | Information handling system high density motherboard |
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Also Published As
| Publication number | Publication date |
|---|---|
| ATE467151T1 (en) | 2010-05-15 |
| DE602005021082D1 (en) | 2010-06-17 |
| TWI389171B (en) | 2013-03-11 |
| TW200539276A (en) | 2005-12-01 |
| JP2007531998A (en) | 2007-11-08 |
| CN1961259A (en) | 2007-05-09 |
| JP4796569B2 (en) | 2011-10-19 |
| US20050221235A1 (en) | 2005-10-06 |
| US7407738B2 (en) | 2008-08-05 |
| WO2005096351A2 (en) | 2005-10-13 |
| CN1961259B (en) | 2010-06-16 |
| EP1735820B1 (en) | 2010-05-05 |
| WO2005096351A3 (en) | 2006-07-20 |
| EP1735820A2 (en) | 2006-12-27 |
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