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US20060003267A1 - Nano-structure and method of fabricating nano-structures - Google Patents

Nano-structure and method of fabricating nano-structures Download PDF

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US20060003267A1
US20060003267A1 US11/215,985 US21598505A US2006003267A1 US 20060003267 A1 US20060003267 A1 US 20060003267A1 US 21598505 A US21598505 A US 21598505A US 2006003267 A1 US2006003267 A1 US 2006003267A1
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nano
layers
substrate
layer stack
feature
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Sriram Ramamoorthi
Peter Mardilovich
Pavel Kornilovich
Vincent Korthuis
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Hewlett Packard Development Co LP
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Publication of US20060003267A1 publication Critical patent/US20060003267A1/en
Assigned to NATIONAL ELEVATOR CAB & DOOR CORP. reassignment NATIONAL ELEVATOR CAB & DOOR CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FRIEDMAN, HAROLD S., FRIEDMAN, JEFFREY, GUSLAWSKI, WALTER, KARAZIM, GEORGE
Assigned to FRIEDMAN, HAROLD S. reassignment FRIEDMAN, HAROLD S. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NATIONAL ELEVATOR CAB & DOOR CORPORATION
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C4/00Coating by spraying the coating material in the molten state, e.g. by flame, plasma or electric discharge
    • C23C4/12Coating by spraying the coating material in the molten state, e.g. by flame, plasma or electric discharge characterised by the method of spraying
    • C23C4/123Spraying molten metal
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C4/00Coating by spraying the coating material in the molten state, e.g. by flame, plasma or electric discharge
    • C23C4/18After-treatment
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/60Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape characterised by shape
    • C30B29/68Crystals with laminate structure, e.g. "superlattices"
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26Processing photosensitive materials; Apparatus therefor
    • G03F7/40Treatment after imagewise removal, e.g. baking
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01Tools for processing; Objects used during processing
    • H05K2203/0104Tools for processing; Objects used during processing for patterning or coating
    • H05K2203/0117Pattern shaped electrode used for patterning, e.g. plating or etching
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/025Abrading, e.g. grinding or sand blasting
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier

Definitions

  • problems can be encountered when a nano-structure is formed that includes a plurality layers of material that are to be planarized. Such problems may include, for example, fraying, delamination, erosion, dishing, and rounding.
  • Desired is a method for forming nano-structures that overcome or reduce such problems.
  • a nano-structure comprises a substrate, a feature formed on the substrate that extends upwardly from a surface of the substrate, layers of material that overlie the substrate surface and at least a portion of the feature, and an exposed surface comprising a top surface of the feature and edges of the layers of material, wherein portions of selected layers of material have been etched away to form trenches adjacent the top surface of the top surface of the feature.
  • a method for fabricating a nano-structure comprises forming a feature on a substrate, depositing multiple layers of material over the substrate and feature to form a multi-layer stack, depositing a film over the multi-layer stack, removing a portion of the film and the multi-layer stack to expose edges of the layers of material, and removing portions of the layers of material to form trenches at a surface of the nano-structure.
  • FIG. 1 is an end view of an embodiment of a nano-structure in an initial stage of fabrication.
  • FIG. 2 is a top perspective view of the nano-structure shown in FIG. 1 .
  • FIG. 3 is an end view of the nano-structure of FIG. 1 in a later stage of fabrication.
  • FIG. 4 is an end view of the nano-structure of FIG. 1 in yet a later stage of fabrication.
  • FIG. 5 is an end view the nano-structure of FIG. 1 in yet another later stage of fabrication.
  • FIG. 6 is an end view of an embodiment of a completed nano-structure.
  • FIG. 7 is a detail view of trenches formed in the nano-structure of FIG. 6 .
  • FIG. 8 is a flow diagram of an embodiment of a method for fabricating a nano-structure.
  • a nano-structure and a method for fabricating nano-structures are disclosed. According to at least one embodiment of the method, multiple layers of material that overlie a feature that is formed on the surface of a substrate are covered by a sacrificial film that enables planarization of the multiple layers while reducing or preventing one or more of fraying, delamination, erosion, dishing, and rounding.
  • FIG. 1 illustrates an embodiment of a nano-structure 100 in an initial stage of fabrication.
  • the nano-structure 100 includes a substrate 102 that, for example, comprises a silicon wafer.
  • a feature 106 that, in the embodiment shown in FIG. 1 , comprises a dielectric bump.
  • the bump 106 can be composed of silicon oxide and can be formed using any one of various fabrication methods.
  • the bump 106 can be formed by depositing a layer of silicon oxide (not shown), and etching the silicon oxide away to leave a bump having the general shape and configuration illustrated in FIG. 1 .
  • the bump 106 has a trapezoidal cross-section that is defined by a base 108 , opposed sides 110 , and a top 112 .
  • the base 108 is larger than the top 112
  • the opposed sides 110 extend diagonally or obliquely toward each other from the base to the top.
  • the bump 106 is elongated (as compared to the sides 110 and top 112 ) so as to extend a relatively long distance across the surface 104 of the substrate 102 .
  • the feature 106 formed on the substrate 102 is described and illustrated as comprising a bump having a trapezoidal cross-section, other configurations and shapes are possible.
  • the nano-structure 100 is constructed on a nano-scale.
  • the bump 106 has a height dimension, h, that ranges from approximately 200 nanometers (nm) to approximately 5000 nm, and a width dimension, w, that ranges from approximately 250 nm to 100 microns ( ⁇ m).
  • the bump 106 has a height of approximately 2500 nm and a width of approximately 5000 nm.
  • the feature has been illustrated and described as a bump, the feature could take substantially any other form including, for example, a step.
  • the feature could have other dimensions, which may only be limited by the size of the substrate.
  • multiple overlapping layers 114 of material are deposited over the substrate 102 and the bump 106 to form a multi-layered stack 116 of material having opposed comers 118 .
  • the layers can alternate between the types of material. For instance, a first layer of gold can be deposited, followed by a layer of tantalum, followed by a further layer of gold, followed by a further layer of tantalum, etc., until a desired number of alternating layers 114 of material have been deposited.
  • Such deposition can be achieved using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or another process.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • other types of materials can be used to form the layers 114 .
  • Example alternative materials include titanium nitride, silicon, silicon oxide, and metal oxides.
  • each layer 114 is approximately 10 Angstoms ( ⁇ ) to approximately 1000 ⁇ thick.
  • each layer 114 can be approximately 500 ⁇ thick.
  • multiple trenches which are useful for nano-imprinting (for example), can be formed by planarizing the layers 114 above the bump 106 to yield a bump that has multiple layers of material along both sides of its length. Assuming an alternating arrangement of materials such as that described above, multiple trenches can be formed by etching away one of the materials (i.e., multiple layers of that material), leaving trenches defined by the layers of material that were not etched away. Unfortunately, such planarization often results in one or more of fraying, delamination, erosion, dishing, and rounding using known techniques.
  • a sacrificial or planarizing film 120 of material is deposited over the multiple layers 114 prior to planarization, as is shown in FIG. 4 .
  • the planarizing film 120 comprises a thick layer of silicon oxide.
  • examples of other materials that can be used for the planarizing film. 120 include amorphous silicon and spin-on-glass.
  • the planarizing film 120 has a thickness that will result in a film height that equals or exceeds the height of the multi-layered stack 116 (see FIG. 4 ). With such a configuration, the low-topography points of the structure 100 are brought above the bump 106 and the multi-layered stack 116 that has been deposited thereon.
  • the planarizing film 120 has a thickness of approximately 200 nm to approximately 10 ⁇ m.
  • the film 120 can be approximately 2.5 micons ( ⁇ m) thick.
  • the planarizing film 120 and the top of the multi-layered stack 116 can be removed. Specifically, as is indicated in FIG. 5 , the film 120 and top of the stack 116 are removed, for example using a chemical-mechanical planarization (CMP) process, such that the top portion of the bump 106 is exposed. Alternatively, mechanical or chemical-mechanical polishing can be used to achieve this result. As is indicated in FIG. 5 , little or no fraying, delamination, erosion, or dishing has occurred. In addition, the comers 118 of the multi-layered stack 116 are minimized due to the provision of the planarizing film 120 .
  • CMP chemical-mechanical planarization
  • trenches 124 can be formed by etching one or more of the layers 114 of material of the multi-layer stack 116 .
  • the stack 116 is composed of alternating materials
  • one of the materials can be selectively etched away to produce trenches 124 that are defined by the remaining layers.
  • FIG. 7 illustrates such an embodiment in detail.
  • the tantalum layers (Ta) remain intact and extend to the surface 122 , while the gold layers (Au) have been etched away to define the trenches 124 .
  • the trenches 124 are defined by side walls 126 (e.g., of tantalum) and bases 128 (e.g., of gold).
  • the trenches 124 have widths equal to the thickness of the layers (in this example gold layers) that have been etched away.
  • the structure that results from the above-described fabrication is a comb-like structure in which diagonal or oblique trenches 124 are formed in the surface of the nano-structure 100 .
  • multiple parallel, oblique trenches 124 are formed on both sides of the bump 106 such that the trenches are angled toward each other as they are traversed upward from the bases 126 to the surface 122 .
  • each trench 124 forms an angle, ⁇ , of approximately 30 to approximately 90 degrees relative to the surface 122 (see FIG. 7 ).
  • the structure 100 can, for example, be used for nano-imprinting. In such a case, the nano-structure 100 may be considered to be a nano-imprinting structure.
  • a feature such as a dielectric bump
  • the feature can be formed by, for instance, depositing a layer of material on top of the substrate, and etching away a portion of the deposited layer.
  • multiple layers of material are deposited over the substrate and feature to form a multi-layer stack, as indicated in block 802 .
  • two or more different types of materials are deposited in an alternating fashion.
  • a sacrificial film is deposited over the multi-layer stack such that the height of the film equals or exceeds the height of the multi-layer stack, including the portion of the stack that overlies the feature.
  • a portion of the film and the stack is removed, as indicated in block 806 , for example using a planarization process.
  • portions of various layers of the multi-layer stack are removed to form trenches in a surface that results when the portion of the film and stack are removed (in block 806 ).
  • the portions of the layers can be removed using a selective etching process.

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Abstract

In one embodiment, a method for fabricating a nano-structure includes forming a feature on a substrate, depositing multiple layers of material over the substrate and feature to form a multi-layer stack, depositing a film over the multi-layer stack, removing a portion of the film and the multi-layer stack to expose edges of the layers of material, and removing portions of the layers of material to form trenches at a surface of the nano-structure.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application is a continuation-in-part of copending U.S. utility application entitled, “Fabrication and Use of Superlattice,” having Ser. No. 10/817,729, filed Apr. 2, 2004, which is entirely incorporated herein by reference.
  • BACKGROUND
  • Although fabrication of structures on a “nano” scale has been practiced for several years, there are still many challenges that are to be overcome to enable manufacture of desired structures.
  • For instance, problems can be encountered when a nano-structure is formed that includes a plurality layers of material that are to be planarized. Such problems may include, for example, fraying, delamination, erosion, dishing, and rounding.
  • Desired is a method for forming nano-structures that overcome or reduce such problems.
  • SUMMARY
  • In one embodiment, a nano-structure comprises a substrate, a feature formed on the substrate that extends upwardly from a surface of the substrate, layers of material that overlie the substrate surface and at least a portion of the feature, and an exposed surface comprising a top surface of the feature and edges of the layers of material, wherein portions of selected layers of material have been etched away to form trenches adjacent the top surface of the top surface of the feature.
  • In one embodiment, a method for fabricating a nano-structure comprises forming a feature on a substrate, depositing multiple layers of material over the substrate and feature to form a multi-layer stack, depositing a film over the multi-layer stack, removing a portion of the film and the multi-layer stack to expose edges of the layers of material, and removing portions of the layers of material to form trenches at a surface of the nano-structure.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The disclosed nano-structure and method can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale.
  • FIG. 1 is an end view of an embodiment of a nano-structure in an initial stage of fabrication.
  • FIG. 2 is a top perspective view of the nano-structure shown in FIG. 1.
  • FIG. 3 is an end view of the nano-structure of FIG. 1 in a later stage of fabrication.
  • FIG. 4 is an end view of the nano-structure of FIG. 1 in yet a later stage of fabrication.
  • FIG. 5 is an end view the nano-structure of FIG. 1 in yet another later stage of fabrication.
  • FIG. 6 is an end view of an embodiment of a completed nano-structure.
  • FIG. 7 is a detail view of trenches formed in the nano-structure of FIG. 6.
  • FIG. 8 is a flow diagram of an embodiment of a method for fabricating a nano-structure.
  • DETAILED DESCRIPTION
  • Disclosed is a nano-structure and a method for fabricating nano-structures. According to at least one embodiment of the method, multiple layers of material that overlie a feature that is formed on the surface of a substrate are covered by a sacrificial film that enables planarization of the multiple layers while reducing or preventing one or more of fraying, delamination, erosion, dishing, and rounding.
  • Referring now in more detail to the drawings, in which like numerals indicate corresponding parts throughout the several views, FIG. 1 illustrates an embodiment of a nano-structure 100 in an initial stage of fabrication. As is indicated in FIG. 1, the nano-structure 100 includes a substrate 102 that, for example, comprises a silicon wafer. Formed on a surface 104 of the substrate 102 is a feature 106 that, in the embodiment shown in FIG. 1, comprises a dielectric bump. The bump 106 can be composed of silicon oxide and can be formed using any one of various fabrication methods. For example, the bump 106 can be formed by depositing a layer of silicon oxide (not shown), and etching the silicon oxide away to leave a bump having the general shape and configuration illustrated in FIG. 1.
  • In this embodiment, the bump 106 has a trapezoidal cross-section that is defined by a base 108, opposed sides 110, and a top 112. As is apparent from FIG. 1, the base 108 is larger than the top 112, and the opposed sides 110 extend diagonally or obliquely toward each other from the base to the top. As is shown in FIG. 2, the bump 106 is elongated (as compared to the sides 110 and top 112) so as to extend a relatively long distance across the surface 104 of the substrate 102. Although the feature 106 formed on the substrate 102 is described and illustrated as comprising a bump having a trapezoidal cross-section, other configurations and shapes are possible.
  • As is described above, the nano-structure 100 is constructed on a nano-scale. By way of example, the bump 106 has a height dimension, h, that ranges from approximately 200 nanometers (nm) to approximately 5000 nm, and a width dimension, w, that ranges from approximately 250 nm to 100 microns (μm). In one embodiment, the bump 106 has a height of approximately 2500 nm and a width of approximately 5000 nm.
  • It is noted that, although the feature has been illustrated and described as a bump, the feature could take substantially any other form including, for example, a step. Moreover, although specific example dimensions have been described, those dimensions are only examples, and the feature could have other dimensions, which may only be limited by the size of the substrate.
  • Referring next to FIGS. 3-6, various other steps of the fabrication of the nano-structure 100 will be described. Beginning with FIG. 3, multiple overlapping layers 114 of material (e.g., metal) are deposited over the substrate 102 and the bump 106 to form a multi-layered stack 116 of material having opposed comers 118. When more than one type of material is used to form the layers 114, such as two types of material, the layers can alternate between the types of material. For instance, a first layer of gold can be deposited, followed by a layer of tantalum, followed by a further layer of gold, followed by a further layer of tantalum, etc., until a desired number of alternating layers 114 of material have been deposited. Depending on the material, such deposition can be achieved using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or another process. Notably, other types of materials can be used to form the layers 114. Example alternative materials include titanium nitride, silicon, silicon oxide, and metal oxides.
  • In the embodiment shown in the figures, nine layers 114 of material have been deposited. By way of example, each layer 114 is approximately 10 Angstoms (Å) to approximately 1000 Å thick. For instance, in one embodiment, each layer 114 can be approximately 500 Å thick.
  • With the structure illustrated in FIG. 3, multiple trenches, which are useful for nano-imprinting (for example), can be formed by planarizing the layers 114 above the bump 106 to yield a bump that has multiple layers of material along both sides of its length. Assuming an alternating arrangement of materials such as that described above, multiple trenches can be formed by etching away one of the materials (i.e., multiple layers of that material), leaving trenches defined by the layers of material that were not etched away. Unfortunately, such planarization often results in one or more of fraying, delamination, erosion, dishing, and rounding using known techniques.
  • To avoid such problems, a sacrificial or planarizing film 120 of material is deposited over the multiple layers 114 prior to planarization, as is shown in FIG. 4. By way of example, the planarizing film 120 comprises a thick layer of silicon oxide. Examples of other materials that can be used for the planarizing film. 120 include amorphous silicon and spin-on-glass. Regardless of the particular material that is used, the planarizing film 120 has a thickness that will result in a film height that equals or exceeds the height of the multi-layered stack 116 (see FIG. 4). With such a configuration, the low-topography points of the structure 100 are brought above the bump 106 and the multi-layered stack 116 that has been deposited thereon. This enables a non-zero removal rate of the low points to be above the height of the multi-layered stack 116. In some embodiments, the planarizing film 120 has a thickness of approximately 200 nm to approximately 10 μm. For example, the film 120 can be approximately 2.5 micons (μm) thick.
  • At this point, the planarizing film 120 and the top of the multi-layered stack 116 can be removed. Specifically, as is indicated in FIG. 5, the film 120 and top of the stack 116 are removed, for example using a chemical-mechanical planarization (CMP) process, such that the top portion of the bump 106 is exposed. Alternatively, mechanical or chemical-mechanical polishing can be used to achieve this result. As is indicated in FIG. 5, little or no fraying, delamination, erosion, or dishing has occurred. In addition, the comers 118 of the multi-layered stack 116 are minimized due to the provision of the planarizing film 120.
  • At this point, multiple trenches can be formed in the new surface 122, and the exposed edges of the stacked layers 114, that results from the planarization process. Referring to FIG. 6, trenches 124 can be formed by etching one or more of the layers 114 of material of the multi-layer stack 116. For instance, in cases in which the stack 116 is composed of alternating materials, one of the materials (and therefore multiple layers 114) can be selectively etched away to produce trenches 124 that are defined by the remaining layers. To cite a specific example, when alternating layers of tantalum and gold are deposited, a portion of the gold layers can be etched away to define the trenches 124. FIG. 7 illustrates such an embodiment in detail. As is shown in that figure, the tantalum layers (Ta) remain intact and extend to the surface 122, while the gold layers (Au) have been etched away to define the trenches 124. As is further shown in the figure, the trenches 124 are defined by side walls 126 (e.g., of tantalum) and bases 128 (e.g., of gold). The trenches 124 have widths equal to the thickness of the layers (in this example gold layers) that have been etched away.
  • The structure that results from the above-described fabrication is a comb-like structure in which diagonal or oblique trenches 124 are formed in the surface of the nano-structure 100. In particular, multiple parallel, oblique trenches 124 are formed on both sides of the bump 106 such that the trenches are angled toward each other as they are traversed upward from the bases 126 to the surface 122. By way of example, each trench 124 forms an angle, α, of approximately 30 to approximately 90 degrees relative to the surface 122 (see FIG. 7). As is mentioned above, the structure 100 can, for example, be used for nano-imprinting. In such a case, the nano-structure 100 may be considered to be a nano-imprinting structure.
  • An embodiment of a method for fabricating a nano-structure can be summarized as provided in FIG. 8. Beginning with block 800, a feature, such as a dielectric bump, is formed on a substrate. The feature can be formed by, for instance, depositing a layer of material on top of the substrate, and etching away a portion of the deposited layer. Next, multiple layers of material are deposited over the substrate and feature to form a multi-layer stack, as indicated in block 802. By way of example, two or more different types of materials are deposited in an alternating fashion.
  • Referring next to block 804, a sacrificial film is deposited over the multi-layer stack such that the height of the film equals or exceeds the height of the multi-layer stack, including the portion of the stack that overlies the feature. Once the film has been deposited, a portion of the film and the stack is removed, as indicated in block 806, for example using a planarization process.
  • Finally, as is indicated in block 808, portions of various layers of the multi-layer stack are removed to form trenches in a surface that results when the portion of the film and stack are removed (in block 806). By way of example, the portions of the layers can be removed using a selective etching process.

Claims (27)

1. A nano-structure, comprising:
a substrate;
a feature formed on the substrate that extends upwardly from a surface of the substrate;
layers of material that overlie the substrate surface and at least a portion of the feature; and
an exposed surface comprising a top surface of the feature and edges of the layers of material;
wherein portions of selected layers of material have been etched away to form trenches adjacent the top surface of the top surface of the feature.
2. The nano-structure of claim 1, wherein the feature has a trapezoidal cross-section.
3. The nano-structure of claim 1, wherein the feature has a width adjacent the substrate surface of approximately 250 nanometers to approximately 100 microns.
4. The nano-structure of claim 1, wherein the layers of material comprise at least two different types of material.
5. The nano-structure of claim 4, wherein layers of different material are formed in an alternating arrangement.
6. The nano-structure of claim 5, wherein only the layers of one type of material have been etched away to form the trenches.
7. The nano-structure of claim 1, wherein each layer of material has a thickness of approximately 10 Angstroms to approximately 1000 Angstroms.
8. The nano-structure of claim 1, further comprising a planarization film adjacent the edges that overlies a portion of the layers of material.
9. The nano-structure of claim 8, wherein the planarization film is composed of silicon oxide.
10. The nano-structure of claim 1, wherein the trenches comprise opposed side walls and a base.
11. The nano-structure of claim 10, wherein the opposed side walls are formed from a first material and the base is formed of a second material.
12. The nano-structure of claim 1, wherein the trenches are oriented in an oblique direction relative to the exposed surface.
13. The nano-structure of claim 1, wherein the nano-structure is a nano-imprint stamp.
14. A method for fabricating a nano-structure, the method comprising:
forming a feature on a substrate;
depositing multiple layers of material over the substrate and feature to form a multi-layer stack;
depositing a film over the multi-layer stack;
removing a portion of the film and the multi-layer stack to expose edges of the layers of material; and
removing portions of the layers of material to form trenches at a surface of the nano-structure.
15. The method of claim 14, wherein forming a feature comprises forming a dielectric bump on the substrate.
16. The method of claim 15, wherein the dielectric bump has a trapezoidal cross-section.
17. The method of claim 15, wherein the dielectric bump has a width adjacent a surface of the substrate of approximately 250 nanometers to approximately 100 microns.
18. The method of claim 14, wherein depositing multiple layers of material comprises depositing at least two different materials in an alternating arrangement such that the multi-layer stack comprises alternating layers of material.
19. The method of claim 14, wherein depositing a film comprises depositing a film over the multi-layer stack having a height that exceeds the top of the multi-layer stack.
20. The method of claim 19, wherein removing a portion of the film and the multi-layer stack comprises planarizing the film and the multi-layer stack together to form the surface of the nano-structure and the edges.
21. The method of claim 14, wherein removing portions of the layers comprises etching away portions of selected layers to form the trenches.
22. The method of claim 21, wherein etching away portions of selected layers comprises etching away layers of a first type of material without etching away layers of a second type of material.
23. The method of claim 21, wherein the method comprises a method for fabricating a nano-imprint stamp.
24. A method for fabricating a nano-structure, the method comprising:
forming a dielectric bump on a surface of a substrate, the feature having opposed sides, at least one of the sides extending in an oblique direction from the substrate surface;
depositing multiple layers of at least two different materials in an alternating manner over the substrate surface and the dielectric bump to form a multi-layer stack of alternating materials;
depositing a film over the multi-layer stack such that the multi-layer stack is completely covered by the film;
planarizing the film and the multi-layer stack to form a surface that comprises exposed edges of the layers of material; and
etching away layers of one of the materials to form trenches in the formed surface, the trenches extending in an oblique direction relative to the formed surface.
25. The method of claim 24, wherein the dielectric bump has a trapezoidal cross-section.
26. The method of claim 24, wherein the dielectric bump has a width adjacent a surface of the substrate of approximately 250 nanometers to approximately 100 microns.
27. The method of claim 24, wherein the method comprises a method for fabricating a nano-imprint stamp.
US11/215,985 2004-04-02 2005-08-31 Nano-structure and method of fabricating nano-structures Abandoned US20060003267A1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050221235A1 (en) * 2004-04-02 2005-10-06 Pavel Kornilovich Fabrication and use of superlattice
US20070178229A1 (en) * 2006-01-30 2007-08-02 Bergendahl Albert S Systems and methods for forming magnetic nanocomposite materials
US20170334255A1 (en) * 2013-05-22 2017-11-23 Kevin McAllister Ball assembly for measuring tongue weight of a trailer

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8695501B2 (en) * 2005-01-28 2014-04-15 Hewlett-Packard Development Company, L.P. Method of forming a contact printing stamp
US7662299B2 (en) 2005-08-30 2010-02-16 Micron Technology, Inc. Nanoimprint lithography template techniques for use during the fabrication of a semiconductor device and systems including same
WO2007097380A1 (en) 2006-02-21 2007-08-30 Nikon Corporation Pattern forming apparatus, pattern forming method, mobile object driving system, mobile body driving method, exposure apparatus, exposure method and device manufacturing method
CN103862032B (en) * 2014-02-26 2016-08-03 国家纳米科学中心 The nucleocapsid noble metal nano rod of four directions superlattices and self-assembling method thereof
US11294435B2 (en) * 2018-12-14 2022-04-05 Dell Products L.P. Information handling system high density motherboard

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5879862A (en) * 1995-09-30 1999-03-09 Daewoo Electronics Co., Ltd. Method for planarizing a non planar layer
US6022669A (en) * 1995-05-02 2000-02-08 Symetrix Corporation Method of fabricating an integrated circuit using self-patterned thin films
US6365059B1 (en) * 2000-04-28 2002-04-02 Alexander Pechenik Method for making a nano-stamp and for forming, with the stamp, nano-size elements on a substrate
US6664031B2 (en) * 2000-06-13 2003-12-16 Hynix Semiconductor Inc Process for forming photoresist pattern by using gas phase amine treatment
US20050221235A1 (en) * 2004-04-02 2005-10-06 Pavel Kornilovich Fabrication and use of superlattice

Family Cites Families (81)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE511293A (en) * 1951-08-24
US2939057A (en) * 1957-05-27 1960-05-31 Teszner Stanislas Unipolar field-effect transistors
US3964296A (en) * 1975-06-03 1976-06-22 Terrance Matzuk Integrated ultrasonic scanning apparatus
US4701366A (en) * 1985-07-01 1987-10-20 Exxon Research And Engineering Company Micro-porous superlattice material having zeolite-like properties
JPH081908B2 (en) * 1987-07-22 1996-01-10 三菱電機株式会社 Superlattice semiconductor device
US5118801A (en) * 1988-09-30 1992-06-02 The Public Health Research Institute Nucleic acid process containing improved molecular switch
US5200051A (en) * 1988-11-14 1993-04-06 I-Stat Corporation Wholly microfabricated biosensors and process for the manufacture and use thereof
US5008616A (en) * 1989-11-09 1991-04-16 I-Stat Corporation Fluidics head for testing chemical and ionic sensors
US5132278A (en) * 1990-05-11 1992-07-21 Advanced Technology Materials, Inc. Superconducting composite article, and method of making the same
EP0533838B1 (en) * 1990-06-11 1997-12-03 NeXstar Pharmaceuticals, Inc. Nucleic acid ligands
US5237523A (en) * 1990-07-25 1993-08-17 Honeywell Inc. Flowmeter fluid composition and temperature correction
JPH04356963A (en) * 1991-06-03 1992-12-10 Nippon Telegr & Teleph Corp <Ntt> Manufacture of semiconductor quantum fine wiring
JP2976995B2 (en) * 1991-10-02 1999-11-10 株式会社アドバンテスト Atomic wire growth method and atomic wire device
JP3390468B2 (en) * 1991-10-16 2003-03-24 バイエル コーポレーション Gene probe binding method by a novel anhydrous mixture method
US5202290A (en) * 1991-12-02 1993-04-13 Martin Moskovits Process for manufacture of quantum dot and quantum wire semiconductors
US5376755A (en) * 1992-04-10 1994-12-27 Trustees Of Boston University Composite lead for conducting an electrical current between 75-80K and 4.5K temperatures
US5418558A (en) * 1993-05-03 1995-05-23 Hewlett-Packard Company Determining the operating energy of a thermal ink jet printhead using an onboard thermal sense resistor
JPH07130956A (en) * 1993-10-29 1995-05-19 Nippondenso Co Ltd Nano-step structure body and method of manufacturing minute coil using it
US5493167A (en) * 1994-05-03 1996-02-20 General Electric Company Lamp assembly with shroud employing insulator support stops
FR2722294B1 (en) 1994-07-07 1996-10-04 Lyon Ecole Centrale PROCESS FOR THE QUALITATIVE AND / OR QUANTITATIVE ANALYSIS OF BIOLOGICAL SUBSTANCES PRESENT IN A CONDUCTIVE LIQUID MEDIUM AND BIOCHEMICAL AFFINITY SENSORS USED FOR THE IMPLEMENTATION OF THIS PROCESS
JP3378413B2 (en) * 1994-09-16 2003-02-17 株式会社東芝 Electron beam drawing apparatus and electron beam drawing method
US5747180A (en) * 1995-05-19 1998-05-05 University Of Notre Dame Du Lac Electrochemical synthesis of quasi-periodic quantum dot and nanostructure arrays
US5716852A (en) * 1996-03-29 1998-02-10 University Of Washington Microfabricated diffusion-based chemical sensor
US5591896A (en) * 1995-11-02 1997-01-07 Lin; Gang Solid-state gas sensors
US5772905A (en) * 1995-11-15 1998-06-30 Regents Of The University Of Minnesota Nanoimprint lithography
US6120844A (en) * 1995-11-21 2000-09-19 Applied Materials, Inc. Deposition film orientation and reflectivity improvement using a self-aligning ultra-thin layer
AU713667B2 (en) * 1996-04-12 1999-12-09 Phri Properties, Inc. Detection probes, kits and assays
US6355436B1 (en) * 1996-05-17 2002-03-12 L'ecole Centrale De Lyon Method for analyzing biological substances in a conductive liquid medium
JP3470012B2 (en) * 1996-05-30 2003-11-25 日本碍子株式会社 Gas analyzer and its calibration method
DE19621996C2 (en) * 1996-05-31 1998-04-09 Siemens Ag Method for producing a combination of a pressure sensor and an electrochemical sensor
US6331680B1 (en) * 1996-08-07 2001-12-18 Visteon Global Technologies, Inc. Multilayer electrical interconnection device and method of making same
US5801124A (en) * 1996-08-30 1998-09-01 American Superconductor Corporation Laminated superconducting ceramic composite conductors
US6284979B1 (en) * 1996-11-07 2001-09-04 American Superconductor Corporation Low resistance cabled conductors comprising superconducting ceramics
US5837466A (en) * 1996-12-16 1998-11-17 Vysis, Inc. Devices and methods for detecting nucleic acid analytes in samples
US6034389A (en) * 1997-01-22 2000-03-07 International Business Machines Corporation Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array
EP0865078A1 (en) * 1997-03-13 1998-09-16 Hitachi Europe Limited Method of depositing nanometre scale particles
US6359288B1 (en) * 1997-04-24 2002-03-19 Massachusetts Institute Of Technology Nanowire arrays
US6085413A (en) * 1998-02-02 2000-07-11 Ford Motor Company Multilayer electrical interconnection device and method of making same
US6022749A (en) * 1998-02-25 2000-02-08 Advanced Micro Devices, Inc. Using a superlattice to determine the temperature of a semiconductor fabrication process
US6463124B1 (en) * 1998-06-04 2002-10-08 X-Technologies, Ltd. Miniature energy transducer for emitting x-ray radiation including schottky cathode
US6438501B1 (en) * 1998-12-28 2002-08-20 Battele Memorial Institute Flow through electrode with automated calibration
US6238085B1 (en) * 1998-12-31 2001-05-29 Honeywell International Inc. Differential thermal analysis sensor
US6256767B1 (en) * 1999-03-29 2001-07-03 Hewlett-Packard Company Demultiplexer for a molecular wire crossbar network (MWCN DEMUX)
US6680377B1 (en) * 1999-05-14 2004-01-20 Brandeis University Nucleic acid-based detection
EP2224508B1 (en) * 1999-07-02 2016-01-06 President and Fellows of Harvard College Method of separating metallic and semiconducting nanoscopic wires
US6573213B1 (en) * 1999-07-16 2003-06-03 Degussa Ag Metal catalysts
EP1085320A1 (en) * 1999-09-13 2001-03-21 Interuniversitair Micro-Elektronica Centrum Vzw A device for detecting an analyte in a sample based on organic materials
US6355438B1 (en) * 1999-11-12 2002-03-12 Isis Pharmaceuticals, Inc. Method for quantitating oligonucleotides
EP1137321A1 (en) * 1999-11-30 2001-09-26 Ibiden Co., Ltd. Ceramic heater
JP4679022B2 (en) * 1999-12-16 2011-04-27 学校法人片柳学園 Target base sequence detection method
US6265306B1 (en) * 2000-01-12 2001-07-24 Advanced Micro Devices, Inc. Resist flow method for defining openings for conductive interconnections in a dielectric layer
US6360582B1 (en) * 2000-01-18 2002-03-26 Texas Instruments Incorporated Method for calibration of chemical sensor in measuring changes in chemical concentration
US20010046674A1 (en) * 2000-02-03 2001-11-29 Andrew Ellington Signaling aptamers that transduce molecular recognition to a differential signal
US6294450B1 (en) * 2000-03-01 2001-09-25 Hewlett-Packard Company Nanoscale patterning for the formation of extensive wires
US20040009510A1 (en) * 2000-03-06 2004-01-15 Scott Seiwert Allosteric nucleic acid sensor molecules
JP3553461B2 (en) * 2000-04-27 2004-08-11 新光電気工業株式会社 Partial plating equipment
AU2001271401A1 (en) * 2000-06-23 2002-01-08 The United States Of America As Represented By The Secretary Of The Navy Microelectronic device and method for label-free detection and quantification ofbiological and chemical molecules
EP1299914B1 (en) * 2000-07-04 2008-04-02 Qimonda AG Field effect transistor
DE10036897C1 (en) * 2000-07-28 2002-01-03 Infineon Technologies Ag Field effect transistor used in a switching arrangement comprises a gate region between a source region and a drain region
US7301199B2 (en) * 2000-08-22 2007-11-27 President And Fellows Of Harvard College Nanoscale wires and related devices
JP2002174973A (en) * 2000-10-31 2002-06-21 Toshiba Tec Corp Fixing device
CA2430888C (en) * 2000-12-11 2013-10-22 President And Fellows Of Harvard College Nanosensors
JP3560333B2 (en) * 2001-03-08 2004-09-02 独立行政法人 科学技術振興機構 Metal nanowire and method for producing the same
US20020128067A1 (en) * 2001-03-09 2002-09-12 Victor Keith Blanco Method and apparatus for creating and playing soundtracks in a gaming system
TW554388B (en) * 2001-03-30 2003-09-21 Univ California Methods of fabricating nanostructures and nanowires and devices fabricated therefrom
TWI227285B (en) * 2001-10-15 2005-02-01 Univ Southern California Methods of and apparatus for producing a three-dimensional structure
US20030162190A1 (en) * 2001-11-15 2003-08-28 Gorenstein David G. Phosphoromonothioate and phosphorodithioate oligonucleotide aptamer chip for functional proteomics
US7185542B2 (en) * 2001-12-06 2007-03-06 Microfabrica Inc. Complex microdevices and apparatus and methods for fabricating such devices
US6894359B2 (en) * 2002-09-04 2005-05-17 Nanomix, Inc. Sensitivity control for nanotube sensors
US20030219801A1 (en) * 2002-03-06 2003-11-27 Affymetrix, Inc. Aptamer base technique for ligand identification
US7049625B2 (en) * 2002-03-18 2006-05-23 Max-Planck-Gesellschaft Zur Fonderung Der Wissenschaften E.V. Field effect transistor memory cell, memory device and method for manufacturing a field effect transistor memory cell
DE60221346T2 (en) * 2002-03-22 2008-04-17 Instrumentarium Corp. Gas analyzer using thermal sensors
US6872645B2 (en) * 2002-04-02 2005-03-29 Nanosys, Inc. Methods of positioning and/or orienting nanostructures
US20030189202A1 (en) * 2002-04-05 2003-10-09 Jun Li Nanowire devices and methods of fabrication
US20040134772A1 (en) * 2002-10-01 2004-07-15 Microfabrica Inc. Monolithic structures including alignment and/or retention fixtures for accepting components
DE10221799A1 (en) * 2002-05-15 2003-11-27 Fujitsu Ltd Semiconductor sensor for detecting target molecules and molecular change effects in protein recognition, analysis and quantification comprises a field effect transistor with a gate produced from SOI substrates
US20030224435A1 (en) * 2002-05-16 2003-12-04 Scott Seiwert Detection of abused substances and their metabolites using nucleic acid sensor molecules
US7138330B2 (en) * 2002-09-27 2006-11-21 Medtronic Minimed, Inc. High reliability multilayer circuit substrates and methods for their formation
JP3862671B2 (en) * 2003-05-19 2006-12-27 松下電器産業株式会社 Nitride semiconductor device
US7223611B2 (en) * 2003-10-07 2007-05-29 Hewlett-Packard Development Company, L.P. Fabrication of nanowires
US7132298B2 (en) * 2003-10-07 2006-11-07 Hewlett-Packard Development Company, L.P. Fabrication of nano-object array

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6022669A (en) * 1995-05-02 2000-02-08 Symetrix Corporation Method of fabricating an integrated circuit using self-patterned thin films
US5879862A (en) * 1995-09-30 1999-03-09 Daewoo Electronics Co., Ltd. Method for planarizing a non planar layer
US6365059B1 (en) * 2000-04-28 2002-04-02 Alexander Pechenik Method for making a nano-stamp and for forming, with the stamp, nano-size elements on a substrate
US6664031B2 (en) * 2000-06-13 2003-12-16 Hynix Semiconductor Inc Process for forming photoresist pattern by using gas phase amine treatment
US20050221235A1 (en) * 2004-04-02 2005-10-06 Pavel Kornilovich Fabrication and use of superlattice

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050221235A1 (en) * 2004-04-02 2005-10-06 Pavel Kornilovich Fabrication and use of superlattice
US7407738B2 (en) * 2004-04-02 2008-08-05 Pavel Kornilovich Fabrication and use of superlattice
US20070178229A1 (en) * 2006-01-30 2007-08-02 Bergendahl Albert S Systems and methods for forming magnetic nanocomposite materials
WO2008054833A3 (en) * 2006-01-30 2009-05-07 Albert S Bergendahl Systems and methods for forming magnetic nanocomposite materials
US8273407B2 (en) * 2006-01-30 2012-09-25 Bergendahl Albert S Systems and methods for forming magnetic nanocomposite materials
US20170334255A1 (en) * 2013-05-22 2017-11-23 Kevin McAllister Ball assembly for measuring tongue weight of a trailer

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