US20050224455A1 - Method for making a semiconductor device using treated photoresist as an implant mask - Google Patents
Method for making a semiconductor device using treated photoresist as an implant mask Download PDFInfo
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- US20050224455A1 US20050224455A1 US11/143,295 US14329505A US2005224455A1 US 20050224455 A1 US20050224455 A1 US 20050224455A1 US 14329505 A US14329505 A US 14329505A US 2005224455 A1 US2005224455 A1 US 2005224455A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/945—Special, e.g. metal
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/947—Subphotolithographic processing
Definitions
- This invention relates generally to semiconductor devices, and more specifically, to methods of manufacturing semiconductors with photoresist masks.
- the photolithography has been moving to smaller and smaller wavelengths.
- the light provided at these reduced wavelengths has resulted in the need for different photoresists. This has been caused not just by the change in character of the light due to wavelength but also the reduced intensity of the light. With these required changes in the photoresist, the photoresists have also changed in their composition and thus affect semiconductor processing chemistries.
- the conventional thickness of photoresist masks also needs to shrink.
- a conventional photoresist mask has a high aspect ratio which is difficult to pattern. Therefore, a thinner photoresist typically allows more depth of focus and process latitude. Also, the height of the photoresist causes unwanted shadowing of angled implants used at various points in semiconductor processing.
- Photoresist layers are often used as a masking layer to direct implantation in only certain areas.
- a known method to avoid the issues caused by thick photoresist is to use a thinner resist.
- thinner photoresists have the inherent disadvantage of a reduced stopping ability for any implantation process.
- a breakthrough may occur during an implant step and negatively impact the semiconductor devices in regions under the photoresist.
- U.S. Pat. No. 6,815,359 Gabriel et al. propose a plasma process for treating a photoresist with fluorine wherein only exposed outer surfaces of the photoresist are modified.
- a plasma process is typically at an elevated process temperature, and the processing equipment and chemistry are complex. Plasma processes act by enhancing cross-linking of a polymer contained in the photoresist. This cross-linking is known to lead to stresses in the photoresist which can lead to modification or deformation of the intended pattern.
- a disadvantage of having a treated photoresist layer only at exposed surfaces is that various subsequent processing, such as etching and implanting, can readily penetrate the thin treated portion of the photoresist. Once penetrated, the remaining area of the photoresist is vulnerable and may fail to provide the desired masking protection.
- U.S. Pat. No. 6,544,894 is another example of a photoresist mask that is plasma treated with a fluorine-containing gas to enhance etching resistance.
- the process taught therein addresses the manufacturing of chromium masks which will subsequently be used in semiconductor processing. These masks are formed by patterning photoresist layers and etching the chromium. By introducing fluorine into the photoresist, the photoresist becomes less susceptible to degradation during the chromium etch step.
- the manner of introducing fluorine is similar to that described in U.S. Pat. No. 6,815,359 described above and thus suffers the same disadvantages.
- FIGS. 1 and 2 illustrate in cross-sectional form aspects of how photoresist thickness affects semiconductor processing
- FIGS. 3-6 illustrate in cross-sectional form a method of manufacturing a semiconductor device using a treated photoresist mask in accordance with one form of the present invention
- FIGS. 7-12 illustrate in cross-sectional form a method of manufacturing a semiconductor device using a treated photoresist mask in accordance with another form of the present invention.
- FIG. 13 illustrates in flow chart form the method implemented in FIGS. 3-12 .
- FIG. 1 Illustrated in FIG. 1 is a known semiconductor device 10 having a substrate 12 having three distinct regions of differing conductivity.
- An NMOS region 14 is separated from a PMOS region 16 by an isolation region 20 .
- the PMOS region 16 is separated from an NMOS region 18 by an isolation region 22 .
- Overlying and in contact with the semiconductor device is a photoresist layer 24 which is uniformly in place over the semiconductor device 10 .
- a patterned chromium mask (not shown) overlies the semiconductor device 10 and allows light to expose only select regions of photoresist layer 24 .
- a region 25 of photoresist layer 24 is irradiated by light 28 having a wavelength of ⁇ .
- the ability of the light 28 to uniformly react in the desired region 25 depends upon the wavelength of the light and the height of the photoresist layer 24 .
- Conventional photoresist layers are relatively thick in comparison with the distance between two isolated semiconductor features.
- the height of the photoresist layer may lead to inaccuracies in the patterning. In particular, due to the relative depth of the opening, the light will scatter in a manner that leads to less light reaching the surface to be exposed. Since the wavelength is fixed for a given semiconductor generation, the height of the photoresist layer 24 is the primary variable that can be adjusted.
- photoresist layer 24 may not be readily thinned to address this problem because at lower thicknesses the photoresist does not adequately function as a mask for subsequent implant steps.
- FIG. 2 Illustrated in FIG. 2 is a known semiconductor device 40 having a substrate 42 with three distinct regions of differing conductivity.
- An NMOS region 44 is separated from a PMOS region 46 by an isolation region 50 .
- the PMOS region 46 is separated from an NMOS region 48 by an isolation region 52 .
- Overlying each of these three regions is a feature, such as gate electrodes 54 , 56 and 58 , respectively.
- gate electrode 54 and gate electrode 58 Overlying gate electrode 54 and gate electrode 58 is a patterned photoresist layer 60 having an opening exposing the gate electrode 56 .
- An angled implant operation is being shown in which implant ions are directed onto semiconductor device 40 at a fixed angle from the left.
- FIG. 3 Illustrated in FIG. 3 is a cross-section of a semiconductor device 100 .
- a semiconductor substrate 101 has formed therein isolation regions 102 , 104 and 106 to define intervening regions where devices will be formed.
- a thin dielectric layer 111 overlies semiconductor substrate 101 and functions to protect the semiconductor's surface between the isolation regions 102 , 104 and 106 .
- a patterned photoresist layer 112 is put into place overlying a portion of the semiconductor substrate 101 between the isolation regions 102 and 104 .
- the photoresist layer 112 is formed in a conventional manner. For example, photoresist layer 112 may be uniformly spun onto semiconductor device 100 and then selectively irradiated with light and developed with a chemical. No further depth of discussion will be made regarding the patterning of the photoresist layer 112 .
- the photoresist layer 112 comprises carbon, oxygen, fluorine and hydrogen. Only hydrogen and carbon are illustrated in FIG. 3 as the contributions of the other elements are not critical.
- molecular halogens which may be implemented are molecular bromine, molecular chlorine, molecular iodine and molecular fluorine.
- molecular halogen is implemented as molecular fluorine F 2 which is diluted with a carrier gas such as nitrogen.
- the percentage of the molecular fluorine in the carrier gas is small. In one form, the molecular fluorine is only one percent of the ambient gas, but it should be understood that other percentages may be used.
- the pressure of the carrier gas is within a range of 120 to 1500 Torr and the flow rate of the carrier gas in on the order of 1,000 standard cubic centimeters per minute.
- This molecular fluorine penetrates deep into the photoresist layer 112 , dissociates, and displaces the hydrogen (i.e. chemical substitution) from the polymer. It should be noted that this displacement does not occur in a plasma at an elevated temperature, but rather is implemented without plasma and at temperatures varying as low as room temperature. In one form, the molecular fluorine is flowed at a temperature below around 50 degrees Celsius and above around 10 degrees Celsius. This is a chemical reaction which fundamentally changes the properties of the photoresist layer 112 . The depth to which this reaction is allowed to occur can be controlled by the fluorination time and is implementation specific but may include the entire thickness of the resist. As a result, the fluorine content of the photoresist layer 112 extends significantly beyond the exposed perimeters of photoresist layer 112 .
- Illustrated in FIG. 4 is the result of processing of semiconductor device 100 in FIG. 3 wherein a resulting fluorinated photoresist layer 116 has been created.
- various chemistries may be used to remove the molecular fluorine ambient of FIG. 3 from semiconductor device 100 .
- Illustrated in FIG. 5 is further processing of semiconductor device 100 wherein an ion implant 118 is implemented while using the fluorinated photoresist layer 112 .
- Various ion materials may be used such as boron, phosphorous, arsenic and others common in semiconductor processing.
- fluorinated photoresist layer 116 contains significant amounts of fluorine, its ability to block the implant is enhanced over typical photoresist and photoresist with only a fluorinated perimeter.
- an initial thinner photoresist layer 112 may be used. As described above, the use of an initial thin photoresist layer as device geometries shrink avoids various problems.
- FIG. 6 Illustrated in FIG. 6 is further processing of semiconductor device 100 wherein the fluorinated photoresist layer 116 has been removed and an N-well region 120 created by ion implant 118 is illustrated.
- the N-well region 120 is a new conductivity region within semiconductor substrate 101 . It should be well understood that depending upon the conductivity of ion implant 118 , the N-well region 120 could be implemented as a P-well rather than an N-well. It should be understood that at this point in the processing, various additional semiconductor devices (not shown) may be formed in the N-well 120 to form a completed semiconductor.
- FIG. 7 Illustrated in FIG. 7 is processing of a semiconductor device 200 which represents another portion of the semiconductor device of FIGS. 2-6 .
- gate electrode 122 and gate electrode 124 have been formed respectively overlying gate dielectric 126 and gate dielectric 128 .
- Protective oxides 130 cover the semiconductor substrate 101 in regions where a transistor source and drain regions will subsequently be formed.
- a patterned photoresist layer 134 is formed and has been fluorinated as illustrated in FIGS. 3 and 4 . Because a fluorinated photoresist layer exists, a thinner photoresist layer may be used which will prevent the shadowing effect described above.
- Illustrated in FIG. 8 is further processing of semiconductor device 100 wherein an angled ion implant 140 is implemented.
- the ion implant 140 has an N-type doping concentration.
- Ion implant 140 is typical of what is commonly referred to as a ‘halo’ implant.
- FIG. 9 Illustrated in FIG. 9 are the resulting doping profiles 142 and 144 from the processing of FIG. 8 .
- the doping profiles 142 and 144 are the same conductivity as the N-well region 120 . It should be noted that because of the reduced height of photoresist layer 134 due to the fluorination with molecular fluorine, the shadowing common with devices such as in FIG. 2 does not occur. In particular, note that the height of photoresist layer 134 permits some implantation to occur to the left of gate electrode 124 .
- FIG. 10 Illustrated in FIG. 10 is further processing of semiconductor device 200 .
- II ion implant
- FIG. 11 Illustrated in FIG. 11 is further processing of semiconductor device 200 wherein the photoresist layer 134 has been removed and resulting halo regions 148 and 150 are illustrated. It should be well understood that depending upon the conductivity of ion implant 146 , the N-well region 120 could be implemented as a P-well. It should be understood that at this point in the processing, various additional semiconductor devices (not shown) may be formed in the N-well region 120 to form a completed semiconductor.
- Source and drain regions 152 and 154 are formed lateral to the gate electrode 124 and within the semiconductor substrate 101 to form a P-channel transistor. Adjacent the gate electrode 124 are gate liner 157 and sidewall spacer 156 . The gate liner 157 and sidewall spacer 156 are dielectric materials. A complementary N-channel transistor is formed on an opposing side of the isolation region 104 . In particular, halo regions 158 and 160 are formed similar to FIGS. 7-10 . Source and drain regions 162 and 164 are formed lateral to the gate electrode 122 and within the semiconductor substrate 101 .
- the ion implantation required to form the halo regions, source and drain to the left of isolation region 104 occurs with a treated photoresist layer (not shown) overlying the N-channel transistor to the right of isolation region 104 , wherein such photoresist layer is treated in accordance with the same method used in FIGS. 3 and 4 for fluorinated photoresist layer 116 .
- Gate electrode 122 overlies gate dielectric 126 .
- Gate liner 167 and sidewall spacer 168 are positioned adjacent to gate electrode 122 .
- FIG. 13 Illustrated in FIG. 13 is a flowchart of a method for making a semiconductor structure by treating a photoresist layer with molecular fluorine to be used as an implant mask.
- a photoresist layer is deposited overlying a semiconductor substrate and patterned in a step 172 .
- a step 174 either molecular fluorine diluted in an inert gas or a liquid fluorinating agent is flowed over the photoresist layer to replace hydrogen atoms in the photoresist layer with fluorine atoms throughout either a substantial portion or throughout the entire photoresist layer.
- a step 176 an ion implant, such as a halo implant, is performed using the treated photoresist layer as a mask to the ions.
- a step 178 the formation of a semiconductor device is completed prior to ending the process at step 180 . Any type of semiconductor structure or semiconductor device may be formed in step 178 . It should be noted that the method described herein is used integral with a manufacturing process to form a semiconductor device as opposed to separately treating and creating a masking layer that is later placed over a semiconductor device as a mask function.
- additional processing of the photoresist layer is needed. This additional processing includes either additional time, increased pressure, increased temperature or all of the above. It should be understood that rather than using molecular fluorine in a gas phase, a liquid fluorinating agent may be used instead to obtain a uniform fluorine profile. By using the disclosed method a very thin photoresist layer may be implemented. Exemplary thicknesses of photoresist that are fluorinated using the disclosed methods are one-half micron and less.
- MOS metal oxide semiconductor
- DSP digital signal processing
- DSP digital signal processing
- the treating of a photoresist film by using a molecular halogen or a liquid fluorinating agent is chemically different than previous suggested treatments of fluorine in a plasma.
- the exposure of photoresist to fluorine in a plasma is chemically limiting so that only exposed surfaces of the photoresist become fluorinated.
- a plasma is used the reaction that produces fluorination results from chemical linking of elements. This reaction by its nature does not penetrate further than a small perimeter region. Therefore, the use of a plasma does not allow photoresist to be made smaller without the consequences associated with subsequent implanting of having shadowing as described herein and inadequate blocking of implanted ions.
- a molecular halogen or a liquid fluorinating agent functions chemically to replace hydrogen contained within the photoresist and penetrate an entire depth of a photoresist layer. While any depth percentage of fluorination of the photoresist may be implemented using the methods described herein, when very thin photoresist layers are used in state-of-the-art processes having extremely small dimensions it is more likely that all of the photoresist layer needs to be fluorinated for enhanced ion implant blocking.
- a method of making a device structure by providing a semiconductor substrate.
- a layer of photoresist is deposited over the substrate.
- the layer of photoresist is patterned to form a layer of patterned photoresist.
- a molecular halogen or a liquid fluorinating agent is flowed over the layer of patterned photoresist to form a layer of treated photoresist.
- An implant is performed using the layer of treated photoresist as a mask to the implant to form an implanted region in the substrate. Formation of the device structure is completed, wherein the device structure includes the implanted region.
- the molecular halogen is molecular fluorine (F 2 ).
- the molecular halogen is one of bromine (Br 2 ), chlorine (Cl 2 ) or iodine (I 2 ).
- molecular halogen is flowed by flowing nitrogen, wherein the molecular halogen has an atomic concentration of about 1 percent.
- the molecular halogen is flowed at a temperature below 50 degrees Celsius and above 10 degrees Celsius.
- the layer of photoresist comprises hydrogen and the flowing the molecular halogen or the liquid fluorinating agent results in replacing hydrogen atoms with halogen atoms.
- the layer of patterned photoresist has a first thickness and flowing the molecular halogen or the liquid fluorinating agent results in replacing hydrogen atoms with halogen atoms to at least half of the first thickness.
- hydrogen atoms are replaced with halogen atoms at substantially all depth levels of the patterned photoresist.
- the implant is a halo implant.
- the implant is a well implant.
- Each of the molecular halogen and the liquid fluorinating agent comprises fluorine.
- the layer of treated photoresist has a top surface.
- the layer of patterned photoresist comprises hydrogen.
- the step of flowing replaces hydrogen atoms with fluorine atoms and is for controlling a profile of the fluorine atoms from the top surface to control a profile of molecular weight of the patterned photoresist.
- the molecular halogen is flowed at a pressure of at least 120 Torr.
- a method of making a device structure by providing a semiconductor substrate and depositing a layer of photoresist over the substrate.
- the layer of photoresist comprises hydrogen and is patterned to form a layer of patterned photoresist having an exposed top surface, a bottom surface that is closest to the substrate, and a first thickness from the exposed top surface to the bottom surface.
- a molecular halogen or a liquid fluorinating agent is flowed over the layer of patterned photoresist to form a layer of treated photoresist by replacing substantially all of the hydrogen from at least the exposed top surface to half of the first thickness.
- An implant is performed using the layer of treated photoresist as a mask to the implant to form an implanted region in the substrate.
- the molecular halogen comprises molecular fluorine (F 2 ).
- the molecular halogen comprises one of the group consisting of chlorine, fluorine, bromine, and iodine.
- the molecular halogen comprises about 1 percent fluorine:
- the molecular halogen is carried by nitrogen at a flow rate of about 1000 standard cubic centimeters per minute (SCCM).
- SCCM standard cubic centimeters per minute
- the flowing the molecular halogen is performed at a temperature between 10 and 50 degrees Celsius.
- the implant comprises one of a group consisting of a well implant and a halo implant.
- a method of making a device structure by providing a semiconductor substrate having a first region for forming N channel transistors and a second region for forming P channel transistors.
- a first layer of photoresist is deposited over the substrate wherein the layer of photoresist comprises hydrogen.
- the first layer of photoresist is patterned to form a first layer of patterned photoresist over the first region, wherein the first layer of patterned photoresist has an exposed top surface, a bottom surface that is closest to the substrate, and a first thickness from the exposed top surface to the bottom surface.
- a first molecular halogen is flowed over the first layer of patterned photoresist to replace substantially all of the hydrogen from the first layer of patterned photoresist from at least the exposed top surface to half of the first thickness.
- a well implant is performed using the first layer of treated photoresist as a mask to the implant to form the N-well. The first layer of treated photoresist is removed.
- a gate is formed over the N-well.
- a second layer of photoresist is deposited over the first region. The second layer of photoresist is patterned to form a second layer of patterned photoresist over the first region and exposing the second region.
- a second molecular halogen is flowed over the second layer of patterned photoresist.
- first molecular halogen and second molecular halogen comprise molecular fluorine (F 2 ).
- first molecular halogen and the second molecular halogen each comprise a same or a differing one of a group consisting of chlorine (Cl 2 ), fluorine (F 2 ), bromine (Br 2 ), and iodine (I 2 ).
- plurality is defined as two or more than two.
- another is defined as at least a second or more.
- including and/or having, as used herein, are defined as comprising (i.e., open language).
- coupled is defined as connected, although not necessarily directly, and not necessarily mechanically.
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Abstract
Description
- This application is a continuation-in-part under 37 C.F.R. 1.53(b) of the following pending application:
- (1) U.S. Ser. No. 10/779,007 entitled “Method of Masking A Semiconductor Device Using Treated Photoresist” filed on Feb. 13, 2004 by Garza et al. and assigned to the assignee hereof.
- This invention relates generally to semiconductor devices, and more specifically, to methods of manufacturing semiconductors with photoresist masks.
- As manufacturing of semiconductors has involved smaller and smaller dimensions, the photolithography has been moving to smaller and smaller wavelengths. The light provided at these reduced wavelengths has resulted in the need for different photoresists. This has been caused not just by the change in character of the light due to wavelength but also the reduced intensity of the light. With these required changes in the photoresist, the photoresists have also changed in their composition and thus affect semiconductor processing chemistries.
- As the semiconductor dimensions shrink, the conventional thickness of photoresist masks also needs to shrink. For example, when the dimension between adjoining semiconductor well regions that are separated by a narrow isolation shrinks, a conventional photoresist mask has a high aspect ratio which is difficult to pattern. Therefore, a thinner photoresist typically allows more depth of focus and process latitude. Also, the height of the photoresist causes unwanted shadowing of angled implants used at various points in semiconductor processing.
- Photoresist layers are often used as a masking layer to direct implantation in only certain areas. A known method to avoid the issues caused by thick photoresist is to use a thinner resist. However, thinner photoresists have the inherent disadvantage of a reduced stopping ability for any implantation process. When thin photoresists are used in conventional processes, a breakthrough may occur during an implant step and negatively impact the semiconductor devices in regions under the photoresist.
- In U.S. Pat. No. 6,815,359 Gabriel et al. propose a plasma process for treating a photoresist with fluorine wherein only exposed outer surfaces of the photoresist are modified. A plasma process is typically at an elevated process temperature, and the processing equipment and chemistry are complex. Plasma processes act by enhancing cross-linking of a polymer contained in the photoresist. This cross-linking is known to lead to stresses in the photoresist which can lead to modification or deformation of the intended pattern. A disadvantage of having a treated photoresist layer only at exposed surfaces is that various subsequent processing, such as etching and implanting, can readily penetrate the thin treated portion of the photoresist. Once penetrated, the remaining area of the photoresist is vulnerable and may fail to provide the desired masking protection.
- U.S. Pat. No. 6,544,894 is another example of a photoresist mask that is plasma treated with a fluorine-containing gas to enhance etching resistance. The process taught therein addresses the manufacturing of chromium masks which will subsequently be used in semiconductor processing. These masks are formed by patterning photoresist layers and etching the chromium. By introducing fluorine into the photoresist, the photoresist becomes less susceptible to degradation during the chromium etch step. The manner of introducing fluorine is similar to that described in U.S. Pat. No. 6,815,359 described above and thus suffers the same disadvantages.
- The present invention is illustrated by way of example and not limited to the accompanying figures, in which like references indicate similar elements.
-
FIGS. 1 and 2 illustrate in cross-sectional form aspects of how photoresist thickness affects semiconductor processing; -
FIGS. 3-6 illustrate in cross-sectional form a method of manufacturing a semiconductor device using a treated photoresist mask in accordance with one form of the present invention; -
FIGS. 7-12 illustrate in cross-sectional form a method of manufacturing a semiconductor device using a treated photoresist mask in accordance with another form of the present invention; and -
FIG. 13 illustrates in flow chart form the method implemented inFIGS. 3-12 . - Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.
- Illustrated in
FIG. 1 is a knownsemiconductor device 10 having asubstrate 12 having three distinct regions of differing conductivity. AnNMOS region 14 is separated from aPMOS region 16 by anisolation region 20. ThePMOS region 16 is separated from an NMOS region 18 by an isolation region 22. Overlying and in contact with the semiconductor device is aphotoresist layer 24 which is uniformly in place over thesemiconductor device 10. A patterned chromium mask (not shown) overlies thesemiconductor device 10 and allows light to expose only select regions ofphotoresist layer 24. In particular, aregion 25 ofphotoresist layer 24 is irradiated bylight 28 having a wavelength of λ. - The ability of the
light 28 to uniformly react in the desiredregion 25 depends upon the wavelength of the light and the height of thephotoresist layer 24. Conventional photoresist layers are relatively thick in comparison with the distance between two isolated semiconductor features. The height of the photoresist layer may lead to inaccuracies in the patterning. In particular, due to the relative depth of the opening, the light will scatter in a manner that leads to less light reaching the surface to be exposed. Since the wavelength is fixed for a given semiconductor generation, the height of thephotoresist layer 24 is the primary variable that can be adjusted. However,photoresist layer 24 may not be readily thinned to address this problem because at lower thicknesses the photoresist does not adequately function as a mask for subsequent implant steps. - Illustrated in
FIG. 2 is a knownsemiconductor device 40 having asubstrate 42 with three distinct regions of differing conductivity. AnNMOS region 44 is separated from aPMOS region 46 by anisolation region 50. The PMOSregion 46 is separated from anNMOS region 48 by anisolation region 52. Overlying each of these three regions is a feature, such as 54, 56 and 58, respectively. Overlyinggate electrodes gate electrode 54 andgate electrode 58 is a patternedphotoresist layer 60 having an opening exposing thegate electrode 56. An angled implant operation is being shown in which implant ions are directed ontosemiconductor device 40 at a fixed angle from the left. As a result of the height of conventionalphotoresist layer 60, a portion of the circuitry within the opening will not be exposed. In particular, aregion 62 is not adequately exposed to the ion implant, if at all. This effect is known in the art as ‘shadowing’. It should be understood that when an angled ion implant from the opposing direction is implemented, a similar problem will be encountered for a region to the right side ofgate electrode 56. Therefore, the net effect is that the area from thegate electrode 56 to each of 50 and 52 will be inadequately implanted. However, if theisolation regions photoresist layer 60 is intentionally thinned to eliminate this noted problem, another problem is created. In particular, whenphotoresist layer 60 is thinned, thephotoresist layer 60 does not adequately function as a mask for subsequent implant steps as noted above. - Illustrated in
FIG. 3 is a cross-section of asemiconductor device 100. Asemiconductor substrate 101 has formed therein 102, 104 and 106 to define intervening regions where devices will be formed. Aisolation regions thin dielectric layer 111 overliessemiconductor substrate 101 and functions to protect the semiconductor's surface between the 102, 104 and 106. A patternedisolation regions photoresist layer 112 is put into place overlying a portion of thesemiconductor substrate 101 between the 102 and 104. Theisolation regions photoresist layer 112 is formed in a conventional manner. For example,photoresist layer 112 may be uniformly spun ontosemiconductor device 100 and then selectively irradiated with light and developed with a chemical. No further depth of discussion will be made regarding the patterning of thephotoresist layer 112. Thephotoresist layer 112 comprises carbon, oxygen, fluorine and hydrogen. Only hydrogen and carbon are illustrated inFIG. 3 as the contributions of the other elements are not critical. - Also illustrated in
FIG. 3 is an ambient 114 of molecular halogen. Molecular halogens which may be implemented are molecular bromine, molecular chlorine, molecular iodine and molecular fluorine. In the illustrated form the molecular halogen is implemented as molecular fluorine F2 which is diluted with a carrier gas such as nitrogen. The percentage of the molecular fluorine in the carrier gas is small. In one form, the molecular fluorine is only one percent of the ambient gas, but it should be understood that other percentages may be used. The pressure of the carrier gas is within a range of 120 to 1500 Torr and the flow rate of the carrier gas in on the order of 1,000 standard cubic centimeters per minute. However, these parameters are exemplary and other pressures and flow rates may be used. This molecular fluorine penetrates deep into thephotoresist layer 112, dissociates, and displaces the hydrogen (i.e. chemical substitution) from the polymer. It should be noted that this displacement does not occur in a plasma at an elevated temperature, but rather is implemented without plasma and at temperatures varying as low as room temperature. In one form, the molecular fluorine is flowed at a temperature below around 50 degrees Celsius and above around 10 degrees Celsius. This is a chemical reaction which fundamentally changes the properties of thephotoresist layer 112. The depth to which this reaction is allowed to occur can be controlled by the fluorination time and is implementation specific but may include the entire thickness of the resist. As a result, the fluorine content of thephotoresist layer 112 extends significantly beyond the exposed perimeters ofphotoresist layer 112. - Illustrated in
FIG. 4 is the result of processing ofsemiconductor device 100 inFIG. 3 wherein a resultingfluorinated photoresist layer 116 has been created. Depending upon processing equipment, various chemistries may be used to remove the molecular fluorine ambient ofFIG. 3 fromsemiconductor device 100. - Illustrated in
FIG. 5 is further processing ofsemiconductor device 100 wherein anion implant 118 is implemented while using thefluorinated photoresist layer 112. Various ion materials may be used such as boron, phosphorous, arsenic and others common in semiconductor processing. Becausefluorinated photoresist layer 116 contains significant amounts of fluorine, its ability to block the implant is enhanced over typical photoresist and photoresist with only a fluorinated perimeter. As a result of the advantages provided by the process described herein, an initialthinner photoresist layer 112 may be used. As described above, the use of an initial thin photoresist layer as device geometries shrink avoids various problems. - Illustrated in
FIG. 6 is further processing ofsemiconductor device 100 wherein thefluorinated photoresist layer 116 has been removed and an N-well region 120 created byion implant 118 is illustrated. The N-well region 120 is a new conductivity region withinsemiconductor substrate 101. It should be well understood that depending upon the conductivity ofion implant 118, the N-well region 120 could be implemented as a P-well rather than an N-well. It should be understood that at this point in the processing, various additional semiconductor devices (not shown) may be formed in the N-well 120 to form a completed semiconductor. - Illustrated in
FIG. 7 is processing of asemiconductor device 200 which represents another portion of the semiconductor device ofFIGS. 2-6 . In this portion of thesemiconductor device 200,gate electrode 122 andgate electrode 124 have been formed respectively overlyinggate dielectric 126 andgate dielectric 128.Protective oxides 130 cover thesemiconductor substrate 101 in regions where a transistor source and drain regions will subsequently be formed. At the point illustrated inFIG. 7 , a patternedphotoresist layer 134 is formed and has been fluorinated as illustrated inFIGS. 3 and 4 . Because a fluorinated photoresist layer exists, a thinner photoresist layer may be used which will prevent the shadowing effect described above. - Illustrated in
FIG. 8 is further processing ofsemiconductor device 100 wherein an angled ion implant 140 is implemented. In the illustrated form, the ion implant 140 has an N-type doping concentration. Ion implant 140 is typical of what is commonly referred to as a ‘halo’ implant. - Illustrated in
FIG. 9 are the resulting doping profiles 142 and 144 from the processing ofFIG. 8 . The doping profiles 142 and 144 are the same conductivity as the N-well region 120. It should be noted that because of the reduced height ofphotoresist layer 134 due to the fluorination with molecular fluorine, the shadowing common with devices such as inFIG. 2 does not occur. In particular, note that the height ofphotoresist layer 134 permits some implantation to occur to the left ofgate electrode 124. - Illustrated in
FIG. 10 is further processing ofsemiconductor device 200. Those areas immediately to the right of the reduced-height photoresist layer 134 which were not implanted inFIG. 8 become implanted by a complementary angle implant referenced as ion implant (II) 146. This use of complementary angle implants is conventional and therefore no depth of discussion will be devoted to this portion of the method taught herein. - Illustrated in
FIG. 11 is further processing ofsemiconductor device 200 wherein thephotoresist layer 134 has been removed and resulting 148 and 150 are illustrated. It should be well understood that depending upon the conductivity of ion implant 146, the N-halo regions well region 120 could be implemented as a P-well. It should be understood that at this point in the processing, various additional semiconductor devices (not shown) may be formed in the N-well region 120 to form a completed semiconductor. - Illustrated in
FIG. 12 is further processing ofsemiconductor device 200 wherein completed N-channel and P-channel transistor devices are illustrated. Source and 152 and 154 are formed lateral to thedrain regions gate electrode 124 and within thesemiconductor substrate 101 to form a P-channel transistor. Adjacent thegate electrode 124 aregate liner 157 andsidewall spacer 156. Thegate liner 157 andsidewall spacer 156 are dielectric materials. A complementary N-channel transistor is formed on an opposing side of theisolation region 104. In particular, 158 and 160 are formed similar tohalo regions FIGS. 7-10 . Source and 162 and 164 are formed lateral to thedrain regions gate electrode 122 and within thesemiconductor substrate 101. The ion implantation required to form the halo regions, source and drain to the left ofisolation region 104 occurs with a treated photoresist layer (not shown) overlying the N-channel transistor to the right ofisolation region 104, wherein such photoresist layer is treated in accordance with the same method used inFIGS. 3 and 4 forfluorinated photoresist layer 116.Gate electrode 122 overliesgate dielectric 126.Gate liner 167 andsidewall spacer 168 are positioned adjacent togate electrode 122. - Illustrated in
FIG. 13 is a flowchart of a method for making a semiconductor structure by treating a photoresist layer with molecular fluorine to be used as an implant mask. In particular, after astart step 170, a photoresist layer is deposited overlying a semiconductor substrate and patterned in astep 172. In astep 174 either molecular fluorine diluted in an inert gas or a liquid fluorinating agent is flowed over the photoresist layer to replace hydrogen atoms in the photoresist layer with fluorine atoms throughout either a substantial portion or throughout the entire photoresist layer. In astep 176 an ion implant, such as a halo implant, is performed using the treated photoresist layer as a mask to the ions. In astep 178 the formation of a semiconductor device is completed prior to ending the process atstep 180. Any type of semiconductor structure or semiconductor device may be formed instep 178. It should be noted that the method described herein is used integral with a manufacturing process to form a semiconductor device as opposed to separately treating and creating a masking layer that is later placed over a semiconductor device as a mask function. - At this point it should be appreciated that there has been provided a method for enhancing a photoresist layer with a molecular halogen for the purpose of enabling a thinner photoresist layer to be used without negative consequences. Although a discussion of molecular fluorine has been made, other elements which are halogens may be used. The penetration of molecular fluorine into the photoresist is dependent upon time, temperature and pressure. With a constant temperature and pressure, increased time exposure to the molecular fluorine gas allows deeper penetration into the photoresist. It is possible that molecular fluorine will penetrate to the lower portion of the photoresist. The fluorine profile in the photoresist may be either non-uniform or uniform in nature. To obtain a uniform fluorine profile, additional processing of the photoresist layer is needed. This additional processing includes either additional time, increased pressure, increased temperature or all of the above. It should be understood that rather than using molecular fluorine in a gas phase, a liquid fluorinating agent may be used instead to obtain a uniform fluorine profile. By using the disclosed method a very thin photoresist layer may be implemented. Exemplary thicknesses of photoresist that are fluorinated using the disclosed methods are one-half micron and less.
- In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, while the semiconductor devices described herein are in the context of metal oxide semiconductor (MOS) technology, it should be understood that various semiconductor processes may be used. Such processes include, but are not limited to, gallium arsenide and bipolar semiconductor processes. Various other structures may be used. For example, silicon on insulator (SOI) may be used and various transistor structures may be implemented. Such other transistor structures include elevated source/drain devices. Similarly, the semiconductor circuit function may vary widely from memory and data storage circuitry, digital signal processing (DSP), processor and microcontroller circuitry as well as special function logic circuitry.
- The treating of a photoresist film by using a molecular halogen or a liquid fluorinating agent is chemically different than previous suggested treatments of fluorine in a plasma. In addition to increased complexity and expense associated with a plasma, the exposure of photoresist to fluorine in a plasma is chemically limiting so that only exposed surfaces of the photoresist become fluorinated. When a plasma is used the reaction that produces fluorination results from chemical linking of elements. This reaction by its nature does not penetrate further than a small perimeter region. Therefore, the use of a plasma does not allow photoresist to be made smaller without the consequences associated with subsequent implanting of having shadowing as described herein and inadequate blocking of implanted ions. In contrast, the use of a molecular halogen or a liquid fluorinating agent functions chemically to replace hydrogen contained within the photoresist and penetrate an entire depth of a photoresist layer. While any depth percentage of fluorination of the photoresist may be implemented using the methods described herein, when very thin photoresist layers are used in state-of-the-art processes having extremely small dimensions it is more likely that all of the photoresist layer needs to be fluorinated for enhanced ion implant blocking.
- In one form there is herein provided a method of making a device structure by providing a semiconductor substrate. A layer of photoresist is deposited over the substrate. The layer of photoresist is patterned to form a layer of patterned photoresist. A molecular halogen or a liquid fluorinating agent is flowed over the layer of patterned photoresist to form a layer of treated photoresist. An implant is performed using the layer of treated photoresist as a mask to the implant to form an implanted region in the substrate. Formation of the device structure is completed, wherein the device structure includes the implanted region. In one form the molecular halogen is molecular fluorine (F2). In other forms the molecular halogen is one of bromine (Br2), chlorine (Cl2) or iodine (I2). In another form molecular halogen is flowed by flowing nitrogen, wherein the molecular halogen has an atomic concentration of about 1 percent. In yet another form the molecular halogen is flowed at a temperature below 50 degrees Celsius and above 10 degrees Celsius. In another form the layer of photoresist comprises hydrogen and the flowing the molecular halogen or the liquid fluorinating agent results in replacing hydrogen atoms with halogen atoms. In another form the layer of patterned photoresist has a first thickness and flowing the molecular halogen or the liquid fluorinating agent results in replacing hydrogen atoms with halogen atoms to at least half of the first thickness. In another form hydrogen atoms are replaced with halogen atoms at substantially all depth levels of the patterned photoresist. In one form the implant is a halo implant. In another form the implant is a well implant. Each of the molecular halogen and the liquid fluorinating agent comprises fluorine. The layer of treated photoresist has a top surface. The layer of patterned photoresist comprises hydrogen. The step of flowing replaces hydrogen atoms with fluorine atoms and is for controlling a profile of the fluorine atoms from the top surface to control a profile of molecular weight of the patterned photoresist. In yet another form the molecular halogen is flowed at a pressure of at least 120 Torr.
- In another form there is provided a method of making a device structure by providing a semiconductor substrate and depositing a layer of photoresist over the substrate. The layer of photoresist comprises hydrogen and is patterned to form a layer of patterned photoresist having an exposed top surface, a bottom surface that is closest to the substrate, and a first thickness from the exposed top surface to the bottom surface. A molecular halogen or a liquid fluorinating agent is flowed over the layer of patterned photoresist to form a layer of treated photoresist by replacing substantially all of the hydrogen from at least the exposed top surface to half of the first thickness. An implant is performed using the layer of treated photoresist as a mask to the implant to form an implanted region in the substrate. In one form the molecular halogen comprises molecular fluorine (F2). In another form the molecular halogen comprises one of the group consisting of chlorine, fluorine, bromine, and iodine. In yet another form the molecular halogen comprises about 1 percent fluorine: The molecular halogen is carried by nitrogen at a flow rate of about 1000 standard cubic centimeters per minute (SCCM). The flowing the molecular halogen is performed at a temperature between 10 and 50 degrees Celsius. In another form the implant comprises one of a group consisting of a well implant and a halo implant.
- In yet another form there is provided a method of making a device structure by providing a semiconductor substrate having a first region for forming N channel transistors and a second region for forming P channel transistors. A first layer of photoresist is deposited over the substrate wherein the layer of photoresist comprises hydrogen. The first layer of photoresist is patterned to form a first layer of patterned photoresist over the first region, wherein the first layer of patterned photoresist has an exposed top surface, a bottom surface that is closest to the substrate, and a first thickness from the exposed top surface to the bottom surface. A first molecular halogen is flowed over the first layer of patterned photoresist to replace substantially all of the hydrogen from the first layer of patterned photoresist from at least the exposed top surface to half of the first thickness. A well implant is performed using the first layer of treated photoresist as a mask to the implant to form the N-well. The first layer of treated photoresist is removed. A gate is formed over the N-well. A second layer of photoresist is deposited over the first region. The second layer of photoresist is patterned to form a second layer of patterned photoresist over the first region and exposing the second region. A second molecular halogen is flowed over the second layer of patterned photoresist. An angled implant is performed to form a halo region under the gate. Source/drain regions are formed in the second region substantially adjacent to the gate, wherein the device structure is a transistor. In another form the first molecular halogen and second molecular halogen comprise molecular fluorine (F2). In yet another form the first molecular halogen and the second molecular halogen each comprise a same or a differing one of a group consisting of chlorine (Cl2), fluorine (F2), bromine (Br2), and iodine (I2).
- Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention.
- Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The terms a or an, as used herein, are defined as one or more than one. The term plurality, as used herein, is defined as two or more than two. The term another, as used herein, is defined as at least a second or more. The terms including and/or having, as used herein, are defined as comprising (i.e., open language). The term coupled, as used herein, is defined as connected, although not necessarily directly, and not necessarily mechanically.
Claims (20)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/143,295 US20050224455A1 (en) | 2004-02-13 | 2005-06-02 | Method for making a semiconductor device using treated photoresist as an implant mask |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/779,007 US7157377B2 (en) | 2004-02-13 | 2004-02-13 | Method of making a semiconductor device using treated photoresist |
| US11/143,295 US20050224455A1 (en) | 2004-02-13 | 2005-06-02 | Method for making a semiconductor device using treated photoresist as an implant mask |
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| US10/779,007 Continuation-In-Part US7157377B2 (en) | 2004-02-13 | 2004-02-13 | Method of making a semiconductor device using treated photoresist |
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| US20050224455A1 true US20050224455A1 (en) | 2005-10-13 |
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| US11/143,295 Abandoned US20050224455A1 (en) | 2004-02-13 | 2005-06-02 | Method for making a semiconductor device using treated photoresist as an implant mask |
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| US10/779,007 Expired - Fee Related US7157377B2 (en) | 2004-02-13 | 2004-02-13 | Method of making a semiconductor device using treated photoresist |
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| EP (1) | EP1719162B8 (en) |
| JP (1) | JP2007522673A (en) |
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| CN (1) | CN100487873C (en) |
| WO (1) | WO2005082122A2 (en) |
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| US20050026084A1 (en) * | 2003-07-31 | 2005-02-03 | Garza Cesar M. | Semiconductor device and method for elimination of resist linewidth slimming by fluorination |
| US8057143B2 (en) * | 2004-10-05 | 2011-11-15 | Fontaine Trailer Company, Inc. | Trailer load securement system |
| US7435354B2 (en) * | 2005-01-06 | 2008-10-14 | United Microelectronic Corp. | Treatment method for surface of photoresist layer and method for forming patterned photoresist layer |
| US8915684B2 (en) | 2005-09-27 | 2014-12-23 | Fontaine Trailer Company, Inc. | Cargo deck |
| JP2007311508A (en) * | 2006-05-17 | 2007-11-29 | Nikon Corp | Fine pattern forming method and device manufacturing method |
| US7703826B1 (en) * | 2006-09-08 | 2010-04-27 | German Mark K | Bed liner rail system for cargo holddown |
| JP4638550B2 (en) * | 2008-09-29 | 2011-02-23 | 東京エレクトロン株式会社 | Mask pattern forming method, fine pattern forming method, and film forming apparatus |
| CN102573329B (en) * | 2010-12-08 | 2014-04-02 | 北大方正集团有限公司 | Method for fabricating conductive column of circuit board, system and circuit board |
| WO2012173698A1 (en) * | 2011-06-15 | 2012-12-20 | Applied Materials, Inc. | Methods and apparatus for controlling photoresist line width roughness with enhanced electron spin control |
| US8647817B2 (en) * | 2012-01-03 | 2014-02-11 | Tokyo Electron Limited | Vapor treatment process for pattern smoothing and inline critical dimension slimming |
| JP2015115599A (en) * | 2013-12-13 | 2015-06-22 | 株式会社東芝 | Patterning method |
| EP3719576A1 (en) * | 2019-04-04 | 2020-10-07 | IMEC vzw | Resistless pattering mask |
| DE102020206696A1 (en) | 2020-05-28 | 2021-12-02 | Robert Bosch Gesellschaft mit beschränkter Haftung | Method and control device for producing a carrier element for receiving a sample liquid, carrier element, carrier module and method for using a carrier element |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4187331A (en) * | 1978-08-24 | 1980-02-05 | International Business Machines Corp. | Fluorine plasma resist image hardening |
| US6245489B1 (en) * | 1997-10-22 | 2001-06-12 | Imec Vzw | Fluorinated hard mask for micropatterning of polymers |
| US6544894B1 (en) * | 1999-01-26 | 2003-04-08 | Sharp Kabushiki Kaisha | Method of producing chromium mask |
| US6815359B2 (en) * | 2001-03-28 | 2004-11-09 | Advanced Micro Devices, Inc. | Process for improving the etch stability of ultra-thin photoresist |
| US6849515B1 (en) * | 2003-09-25 | 2005-02-01 | Freescale Semiconductor, Inc. | Semiconductor process for disposable sidewall spacers |
| US20050026084A1 (en) * | 2003-07-31 | 2005-02-03 | Garza Cesar M. | Semiconductor device and method for elimination of resist linewidth slimming by fluorination |
| US6924200B2 (en) * | 2000-03-13 | 2005-08-02 | International Business Machines Corporation | Methods using disposable and permanent films for diffusion and implantation doping |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5332653A (en) * | 1992-07-01 | 1994-07-26 | Motorola, Inc. | Process for forming a conductive region without photoresist-related reflective notching damage |
| JPH0669190A (en) * | 1992-08-21 | 1994-03-11 | Fujitsu Ltd | Method for forming fluororesin film |
| US5912187A (en) * | 1993-12-30 | 1999-06-15 | Lucent Technologies Inc. | Method of fabricating circuits |
| JPH0831720A (en) * | 1994-07-13 | 1996-02-02 | Nkk Corp | Method of forming resist mask |
| JPH11251295A (en) * | 1998-02-27 | 1999-09-17 | Sanyo Electric Co Ltd | Semiconductor device and manufacture thereof |
| US6716571B2 (en) * | 2001-03-28 | 2004-04-06 | Advanced Micro Devices, Inc. | Selective photoresist hardening to facilitate lateral trimming |
| US6630288B2 (en) * | 2001-03-28 | 2003-10-07 | Advanced Micro Devices, Inc. | Process for forming sub-lithographic photoresist features by modification of the photoresist surface |
| US6589709B1 (en) * | 2001-03-28 | 2003-07-08 | Advanced Micro Devices, Inc. | Process for preventing deformation of patterned photoresist features |
| JP2002305181A (en) * | 2001-04-06 | 2002-10-18 | Seiko Epson Corp | Method for manufacturing semiconductor device |
| JP4780264B2 (en) * | 2001-05-16 | 2011-09-28 | 信越化学工業株式会社 | Method for forming chromium-based photomask |
| JP3725811B2 (en) * | 2001-10-11 | 2005-12-14 | ローム株式会社 | Manufacturing method of semiconductor device |
| US6790782B1 (en) * | 2001-12-28 | 2004-09-14 | Advanced Micro Devices, Inc. | Process for fabrication of a transistor gate including high-K gate dielectric with in-situ resist trim, gate etch, and high-K dielectric removal |
| US6716570B2 (en) * | 2002-05-23 | 2004-04-06 | Institute Of Microelectronics | Low temperature resist trimming process |
| US6979408B2 (en) * | 2002-12-30 | 2005-12-27 | Intel Corporation | Method and apparatus for photomask fabrication |
-
2004
- 2004-02-13 US US10/779,007 patent/US7157377B2/en not_active Expired - Fee Related
-
2005
- 2005-01-12 CN CN200580004804.8A patent/CN100487873C/en not_active Expired - Fee Related
- 2005-01-12 JP JP2006553127A patent/JP2007522673A/en active Pending
- 2005-01-12 EP EP05711379.7A patent/EP1719162B8/en not_active Expired - Lifetime
- 2005-01-12 KR KR1020067016205A patent/KR101128260B1/en not_active Expired - Fee Related
- 2005-01-12 WO PCT/US2005/000961 patent/WO2005082122A2/en not_active Ceased
- 2005-06-02 US US11/143,295 patent/US20050224455A1/en not_active Abandoned
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4187331A (en) * | 1978-08-24 | 1980-02-05 | International Business Machines Corp. | Fluorine plasma resist image hardening |
| US6245489B1 (en) * | 1997-10-22 | 2001-06-12 | Imec Vzw | Fluorinated hard mask for micropatterning of polymers |
| US6544894B1 (en) * | 1999-01-26 | 2003-04-08 | Sharp Kabushiki Kaisha | Method of producing chromium mask |
| US6924200B2 (en) * | 2000-03-13 | 2005-08-02 | International Business Machines Corporation | Methods using disposable and permanent films for diffusion and implantation doping |
| US6815359B2 (en) * | 2001-03-28 | 2004-11-09 | Advanced Micro Devices, Inc. | Process for improving the etch stability of ultra-thin photoresist |
| US20050026084A1 (en) * | 2003-07-31 | 2005-02-03 | Garza Cesar M. | Semiconductor device and method for elimination of resist linewidth slimming by fluorination |
| US6849515B1 (en) * | 2003-09-25 | 2005-02-01 | Freescale Semiconductor, Inc. | Semiconductor process for disposable sidewall spacers |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1719162B8 (en) | 2016-05-11 |
| US20050181630A1 (en) | 2005-08-18 |
| KR101128260B1 (en) | 2012-03-26 |
| KR20060114716A (en) | 2006-11-07 |
| CN100487873C (en) | 2009-05-13 |
| US7157377B2 (en) | 2007-01-02 |
| JP2007522673A (en) | 2007-08-09 |
| EP1719162A2 (en) | 2006-11-08 |
| CN1918700A (en) | 2007-02-21 |
| WO2005082122A2 (en) | 2005-09-09 |
| WO2005082122A3 (en) | 2006-02-16 |
| EP1719162B1 (en) | 2016-03-23 |
| EP1719162A4 (en) | 2009-05-20 |
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