US20020076924A1

US20020076924A1 - Method for forming an electrical interconnection providing improved surface morphololgy of tungsten

Info

Publication number: US20020076924A1
Application number: US09/859,823
Authority: US
Inventors: Kyung-Bum Koo
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2000-12-20
Filing date: 2001-05-17
Publication date: 2002-06-20
Also published as: KR100375230B1; KR20020049730A

Abstract

In a fabrication method for forming an electrical interconnection of CVD tungsten film, a via hole is formed in a dielectric layer. A lower conductive layer is formed in the via hole and over the dielectric layer. A portion of the lower conductive layer is removed. As a result, the dielectric layer is exposed. An upper conductive layer is formed over the lower conductive layer and over the dielectric layer. The lower conductive layer has a rough surface and the upper conductive layer has a smooth surface. In this manner, following patterning of conductive stripes over the conductive layer, residue is mitigated, and thus, inadvertent interconnection of neighboring stripes is eliminated.

Description

RELATED APPLICATIONS

This application relies for priority upon Korean Patent Application No. 2000-78998, filed on Dec. 20, 2000, the contents of which are herein incorporated by reference in their entirety.

1. Field of the Invention

The invention relates to methods for the fabrication of semiconductor devices and more particularly to methods for forming an electrical interconnection of CVD tungsten film.

2. Background of the Invention

Fabrication of semiconductor devices generally involves a procedure of forming thin films and layers of various materials on wafers of base semiconductor materials, and removing selected areas of such films to provide structures and circuitry. Tungsten is one of the materials commonly deposited on wafers during fabrication. Tungsten provides many advantageous features that render it especially amenable for forming electrical interconnections including plugs and interconnecting stripes. In this capacity, tungsten film is deposited into via holes, and etched or polished to an intermediate insulating layer, leaving tungsten plugs remaining in the via holes. Where the interconnecting stripes are desired, the deposited tungsten film is patterned with photoresist and anisotropically etched, leaving the interconnecting stripes over the insulating layer.

Chemical vapor deposition (CVD) is a well-known process for depositing the tungsten films. In a typical CVD process for forming the tungsten films, wafers are placed on supports within a sealable chamber, the chamber is sealed and evacuated, the wafers are heated, and a gas mixture is introduced into the chamber. A source gas comprising tungsten hexafluoride (WF ₆) is subjected to reduction by hydrogen gas, silane (SiH₄) gas or a mixture of hydrogen and silane. Typically the gases flow continuously during the process. Temperature of the substrate (wafer) to be coated is one of variables that drive the chemical reaction to cause tungsten to be deposited on the substrate surface. It is important to control the temperature and the concentration of the gases in the mixture introduced in the tungsten CVD process.

According to a number of studies, while low tensile stress films are promoted by a relatively lower flow rate of WF ₆and relatively higher wafer temperature, step coverage is promoted by a relatively higher flow rate of WF₆and relatively lower wafer temperature. High tensile stress of a film induces distortion of the wafer on which the film is deposited. This distortion of the wafer makes an adjustment of focus extremely difficult during a photo process to be performed after the deposition of the film. The step coverage is a measure of how well a deposited layer maintains its nominal thickness as it crosses a step. This measure is illustrated in Wolf, S., “Silicon Processing for the VLSI Era”, Vol.2, Lattice Press, Sunset Beach, Calif., (1990), p.202.

Low tensile stress films are known to be quite important for interconnecting stripe applications, but tensile stress is not as critical for plug applications. Similarly, good step coverage is desirable for plug applications, but relatively less critical for interconnecting stripe applications. Because of the different requirements for tungsten film characteristics and the dependence on process parameters as described above, the optimization of process for both plug and interconnecting stripe application was very difficult. A number of approaches to address this issue in the optimization of tungsten CVD process have been reported, including U.S. Pat. No. 5,272,113 to Johannes J. Schmitz et al. and U.S. Pat. No. 6,030,893 to Yung-Tsun Lo et al.

FIGS. 1 and 2 are a cross sectional schematic view and a scanning electron microscope (SEM) view respectively illustrating a process for forming an electrical interconnection in a semiconductor device according to a prior art disclosed in the '893 Lo et al. patent.

Referring to FIG. 1, a

conductive region

3 is formed in a substrate 1. A dielectric layer 5 is then deposited on the substrate 1 and the conductive region 3. The dielectric layer 3 is etched to form a via hole 11 exposing the conductive region. After that, the wafer is sent into a first chamber to form a lower conductive layer 7 on the dielectric layer 5 and in the via hole 11 to contact the conductive region 3. The lower conductive layer 7 is a CVD tungsten film, which has the properties of high tensile stress and suitable step coverage. Thereafter, the wafer is sent into a second chamber to form an upper conductive layer 9 on the lower conductive layer 5. The upper conductive layer 9 is a CVD tungsten film, which has the properties of low tensile stress and moderate step coverage. The combination of the two tungsten layers is patterned with photoresist and anisotropically etched, leaving an interconnecting stripe over the dielectric layer.

However, according to the prior art, the anisotropic etching procedure is unable to entirely remove the combination of the two tungsten layers, leaving residue on the dielectric layer. The residue may cause undesired electrical connection between the interconnecting stripes. FIG. 2 shows an example of an undesired electrical connection between adjacent stripes.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a method for forming an electrical interconnection that confers the advantageous property of good step coverage in via holes and low tensile stress in interconnecting stripes, while mitigating, or eliminating, undesirable electrical connection between the interconnecting stripes.

The method comprises forming a dielectric layer over a substrate. A via hole is formed in the dielectric layer. A lower conductive layer is then formed in the via hole and over the dielectric layer. A portion of the lower conductive layer is removed to leave a plug in the via hole. An upper conductive layer is formed over the plug and over the dielectric layer. The upper conductive layer is patterned to form a interconnecting stripe.

A surface roughness of the lower conductive layer is preferably greater than that of the upper conductive layer. Step coverage of the lower conductive layer is preferably better than that of the upper conductive layer. A tensile stress of the lower conductive layer is preferably higher than that of the upper conductive layer.

Because the plug is formed of the lower conductive layer having the property of suitable step coverage, there is substantially no void in the via hole. Furthermore, since the interconnecting stripe is formed of the upper conductive layer having the attractive property of a smooth surface, there is substantially no residue after the patterning for forming the conductive stripe and therefore accurate alignment in a photo process can be readily obtained.

BRIEF DESCRIPTION OF THE DRAWINGS

Other features of the present invention will be more readily understood from the following detailed description of specific embodiments thereof when read in conjunction with the accompanying drawings, in which: [0016]
FIG. 1 is a cross sectional schematic view illustrating a process for forming an electrical interconnection according to a prior art configuration; [0017]
FIG. 2 is a scanning electron microscope (SEM) view illustrating undesired electrical connection between the interconnecting stripes in the process for forming the electrical interconnection according to the prior art; [0018]
FIGS. 3A and 3B are SEM views illustrating dependency of surface morphology on process temperature; [0019]
FIGS. [0020] 4 to 9 are cross sectional schematic views illustrating a process for forming an electrical interconnection according to a first embodiment of the present invention;
FIG. 10 is a cross sectional schematic views illustrating a process for forming an electrical interconnection according to a modified embodiment of the first embodiment of the present invention; [0021]
FIGS. 11 and 12 are cross sectional schematic views illustrating a process for forming an electrical interconnection according to a second embodiment of the present invention; and [0022]
FIGS. 13A and 13B are SEM views illustrating surface morphology of tungsten films according to the first embodiment of the present invention.[0023]

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention will now be described more fully hereinafter with reference to the accompanying drawings. [0024]
The present invention recognizes that process temperature and gas concentration are important variables that affect surface morphology as well as the properties of tensile stress and step coverage of the CVD tungsten film. In detail, smooth surface roughness is promoted by a relatively lower flow rate of SiH[0025] ₄and relatively higher wafer temperature during the tungsten deposition. FIGS. 3A and 3B show this dependency of surface morphology on process condition. FIG. 3A is a SEM view of a tungsten film which is formed at 365 C. with a thickness of 800 Angstroms. FIG. 3B is a SEM view of a tungsten film which is formed at 415 C. with a thickness of 800 Angstroms. The other process parameters are identical in the two tungsten films; namely, a total pressure of 40 Torr., WF₆flow rate of 300 sccm, SiH₄flow rate of 40 sccm and hydrogen flow rate of 9,000 sccm were used. WF₆is subjected to reduction by a mixture of SiH₄and hydrogen to deposit the tungsten films. As shown in the drawings, while the film of FIG. 3A has a rough surface, the film of FIG. 3B has a smooth surface. FIG. 3A and 3B are images which are magnified 40,000 times. In a similar experiment using the flow rate of SiH₄as a variable, the present inventor obtained a result which demonstrates the dependency of morphology of tungsten film as described above. That is to say, smooth surface roughness is promoted by a relatively lower flow rate of SiH₄during the tungsten deposition.
In view of this dependency of morphology of tungsten film, in the prior art method, it can be readily understood that the upper conductive layer has a smooth surface and the lower conductive layer has a rough surface. In addition, it was determined that the upper conductive layer of tungsten substantially replicates the surface roughness of the lower conductive layer in the prior art method. As a result, the combination of the two layers does not have a smooth surface, resulting in a number of adverse consequences. The residue problem discussed above is one of these problems. Furthermore, the irregular rough surface makes an adjustment of alignment extremely difficult during a photo process to be performed following the deposition of tungsten films. [0026]
FIGS. [0027] 4 to 9 are cross sectional schematic views illustrating a process for forming an electrical interconnection according to a first embodiment of the present invention and FIG. 10 is a cross sectional schematic view illustrating a modified embodiment thereof.
Referring to FIG. 4, there is shown a [0028] substrate 101, preferably composed of monocrystalline silicon. The substrate 101 has a conductive area 103 formed therein. The conductive area 103 is a impurity active region formed by ion implantation into the substrate 101. Other structures such as a polycrystalline silicon pattern, an aluminum wiring pattern, a metal plug or the like, though not shown, may be formed in and on the substrate 101.
A [0029] dielectric layer 105, composed of insulating material such as borophosphosilicate glass (BPSG), spin-on-glass (SOG) or the like, is deposited over the substrate 101 to a thickness of between about 2,000 to 15,000 Angstroms. A via hole 111 is formed through the dielectric layer 105 to the substrate 101.
In a modified embodiment of this embodiment, prior to the formation of via [0030] hole 111, a groove channel may be further formed. Referring to FIG. 10, The groove channel 113 is formed in the dielectric layer 105. After forming the groove channel 113, a via hole 111 is formed through the insulating layer 105. The via hole 111 may be formed in regions with or without groove channels 113.
Referring to FIG. 5, a [0031] barrier layer 115 is deposited conformally over the dielectric layer 105 and within the via hole 111. The barrier layer 115 is preferably formed of one selected from the group consisting of titanium, titanium nitride, tungsten silicide and combinations thereof. In this embodiment, the barrier layer 115 is formed of titanium nitride overlying titanium. This barrier layer 115 is deposited by sputtering or CVD to a thickness of between about 100 to 500 Angstroms. In the modified embodiment described above, the barrier layer 115 may be deposited within the groove channel 113 as well as over the dielectric layer 105 and within the via hole 111.
Referring now to FIG. 6, a lower [0032] conductive layer 117 of tungsten is deposited over the substrate in a CVD chamber to a thickness of between about 400 to 5,000 Angstroms. In this embodiment, the thickness of the lower conductive layer is 800 Angstroms. The lower conductive layer 117 is formed, for example under a condition of a total pressure of about 40 Torr, and at a temperature of about 365 C. using WF₆, SiH₄and hydrogen. The flow rate of the WF₆, SiH₄and hydrogen are 300 sccm, 40 sccm and 9,000 sccm respectively. The WF₆gas is subjected to reduction by a mixture of SiH₄and hydrogen. This lower conductive layer 117 of tungsten has a property of good step coverage and high tensile stress. The lower conductive layer 117 includes a rough surface, as shown in FIG. 13A
The lower [0033] conductive layer 117 is etched back, leaving a tungsten plug filling the via hole, as shown in FIG. 7. In other words, the rough lower conductive layer is removed except in the via hole.
Referring to FIG. 8, an upper [0034] conductive layer 119 is deposited over the resultant structure of FIG. 7, using, for example, a CVD technique, to a thickness of between about 400 to 5,000 Angstroms. In this embodiment, the thickness of the upper conductive layer is 800 Angstroms. The upper conductive layer 119 is formed in condition of a total pressure of about 40 Torr, temperature of about 437° C. using WF₆, SiH₄and hydrogen. Preferred flow rates of WF₆, SiH₄and hydrogen are 200 sccm, 26 sccm and 9,000 sccm respectively. The WF₆gas is subjected to reduction by a mixture of SiH₄and hydrogen. The upper conductive layer 119 of tungsten has the properties of moderate step coverage and low tensile stress. Also, the upper conductive layer 119 shows a smooth surface, as shown in FIG. 13B. FIG. 13A and 13B are images which are magnified 100,000 times.
Unlike the prior art, the upper conductive layer may be formed in the CVD chamber in which the lower conductive layer is formed. In the present invention, there is an intervening process of etching back the lower conductive layer between formation of the lower conductive layer and formation of the upper conductive layer. Therefore, there is time for changing process parameter settings for the upper conductive layer. On the contrary, in the prior art, a process forming the upper conductive layer is performed immediately following formation of the lower conductive layer. Therefore, there is inadequate time for changing the process parameter settings following formation of the lower conductive layer. [0035]
The upper [0036] conductive layer 119 may be deposited by sputtering instead of CVD. It is well known that sputtering of tungsten provides a better surface morphology than that of CVD tungsten.
The combination of the upper conductive layer and the barrier layer is patterned using a photo/etching process, leaving interconnecting stripes over the [0037] dielectric layer 105 as shown in FIG. 9. In the modified embodiment described above, the combination of the upper conductive layer and the barrier layer may be subject to polishing such as CMP (chemical mechanical polishing) to the surface of the dielectric layer. As a result, the interconnecting stripes are retained to within the groove channel 113.
FIGS. 11 and 12 are cross sectional schematic views illustrating a process for forming an electrical interconnection according to a second embodiment of the present invention. [0038]
Referring to FIG. 11, a [0039] substrate 301, a conductive area 303, a dielectric layer 305, a via hole 311, a barrier layer 315 and a lower conductive layer 317 are provided using same method as that of the first embodiment.
The lower [0040] conductive layer 317 and the barrier layer 315 are polished using CMP (chemical mechanical polishing) to expose a surface of the dielectric layer 305 and leave a tungsten plug filling the via hole.
Referring to FIG. 12, a [0041] glue layer 318 is deposited over the dielectric layer 305 and the tungsten plug. The glue layer 318 preferably is formed of one selected from the group consisting of titanium, titanium nitride, tungsten silicide and combinations thereof. In this embodiment, the glue layer 318 is formed of titanium nitride. This glue layer 318 is deposited by sputtering or CVD to a thickness of between about 100 to 500 Angstroms.
Subsequently, an upper [0042] conductive layer 319 is deposited over the glue layer 318 using the same method as the first embodiment. Though not shown, the combination of the upper conductive layer 319 and the glue layer is patterned using a conventional photo/etching process, thereby leaving an interconnecting stripe over the dielectric layer.
It has been determined that grain size of the upper conductive layer is smaller that that of the lower conductive layer, and that the smaller the grain size is, the smoother the surface of CVD tungsten film. [0043]
According to the present invention, the lower conductive layer having the property of rough surface and good step coverage is removed except for the portion that lies in the via hole such that the via hole is be completely filled by the lower conductive layer without void. Furthermore, the interconnecting stripe does not comprise the lower conductive layer having the property of rough surface and high tensile stress. Therefore, the present invention resolves the residue problem and the alignment adjustment problem discussed above in connection with the conventional methods. [0044]
While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention. [0045]
In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purpose of limitation, the scope of the invention being set forth in the following claims. [0046]

Claims

What is claimed is:

1 A method of fabricating a semiconductor device comprising:

forming a dielectric layer over a substrate;

forming a via hole in the dielectric layer;

forming a lower conductive layer in the via hole and over the dielectric layer;

removing a portion of the lower conductive layer to leave a plug in the via hole; and

forming an upper conductive layer over the plug and the dielectric layer, wherein a surface roughness of the lower conductive layer is greater than that of the upper conductive layer.

2 The method of claim 1, wherein the lower and upper conductive layers are formed of tungsten film.

3 The method of claim 1, wherein the lower conductive layer is formed at a lower temperature than a temperature at which the upper conductive layer is formed.

4 The method of claim 2, wherein the lower conductive layer and upper conductive layer are formed using a flow of SiH₄, and wherein the lower conductive layer is formed using a using a higher flow rate of SiH₄than that of the upper conductive layer.

5 The method of claim 4, wherein the upper and lower conductive films comprise tungsten films formed by a flow of WF₆reduced by a mixture of SiH₄and hydrogen.

6 The method of claim 1, wherein removing a portion of the lower conductive layer is performed by a process selected from the group consisting of an etch back process and a polishing process.

7 The method of claim 1, wherein the upper conductive layer is formed in a reactive chamber in which the lower conductive layer is formed.

8 The method of claim 1, further comprising forming a barrier layer in the via hole and over a surface of the dielectric layer prior to formation of the lower conductive layer.

9 The method of claim 8, wherein the barrier layer is formed of one selected from the group consisting of titanium, titanium nitride, tungsten silicide and combinations thereof.

10 The method of claim 8, further comprises removing a portion of the barrier layer located over a surface of the dielectric layer after removing a portion of the lower conductive layer.

11 The method of claim 10, further comprising forming a glue layer over the plug and over the surface of the dielectric layer prior to formation of the upper conductive layer.

12 The method of claim 1, wherein the lower conductive layer is formed by CVD and wherein the upper conductive layer is formed by sputtering.

13 The method of claim 1, wherein both the lower conductive layer and the upper conductive layer are formed by CVD.

14 A method of fabricating a semiconductor device comprising:

forming a dielectric layer over a substrate;

forming a via hole in the dielectric layer;

forming a lower conductive layer in the via hole and over the dielectric layer;

forming an upper conductive layer over the plug and the dielectric layer, wherein a tensile stress of the lower conductive layer is greater than that of the upper conductive layer.

15 A method of fabricating a semiconductor device comprising:

forming a dielectric layer over a substrate;

forming a via hole in the dielectric layer;

forming a lower conductive layer in the via hole and over the dielectric layer;

forming an upper conductive layer over the plug and the dielectric layer, wherein a step coverage property of the lower conductive layer is better than that of the upper conductive layer.

16 A method of fabricating a semiconductor device comprising:

forming a dielectric layer over a substrate;

forming a via hole in the dielectric layer;

forming a lower conductive layer in the via hole and over the dielectric layer;

forming an upper conductive layer over the plug and the dielectric layer, wherein a grain size of the lower conductive layer is larger than that of the upper conductive layer.