[go: up one dir, main page]

US20010054600A1 - Method and apparatus for simulating standard test wafers - Google Patents

Method and apparatus for simulating standard test wafers Download PDF

Info

Publication number
US20010054600A1
US20010054600A1 US09/923,725 US92372501A US2001054600A1 US 20010054600 A1 US20010054600 A1 US 20010054600A1 US 92372501 A US92372501 A US 92372501A US 2001054600 A1 US2001054600 A1 US 2001054600A1
Authority
US
United States
Prior art keywords
wafer including
simulate
wafer
support layer
simulates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US09/923,725
Inventor
Gregory Goldspring
Robert O'Donnell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US09/923,725 priority Critical patent/US20010054600A1/en
Publication of US20010054600A1 publication Critical patent/US20010054600A1/en
Priority to US11/244,335 priority patent/US7270760B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/926—Dummy metallization

Definitions

  • the present invention relates generally to semiconductor test wafers and, more particularly, to a test wafer that effectively simulates “patterned” standard test wafers and can be produced at a reduced cost.
  • standard test wafers are normally used in place of standard production wafers.
  • a cross-section of a standard production wafer 10 and a standard test wafer 20 are shown in FIGS. 1 and 2, respectively.
  • the standard test wafer 20 includes a wafer 22 including any type of materials thereon such as aluminum and the like.
  • This standard test wafer 20 further has a layer of photoresist 24 thereon.
  • the standard test wafer 20 simulates a pair of uppermost layers 26 of the standard production wafer 10 .
  • the photoresist 24 of the standard test wafer 20 be “patterned.”
  • the resist is ideally applied to the standard test wafer 20 to define a plurality of vias, channels, etc. which in turn leave a percentage of the standard test wafer 20 exposed as shown in FIG. 3.
  • standard test wafers 20 can be expensive, especially when standard test wafers 20 have multiple layers similar to standard production wafers 10 . This cost often fails to justify many conditioning exercises and marathon experiments which, in turn, leads to reduced quality and reliability during the subsequent processing of standard production wafers 10 .
  • One known prior art alternative to the use of such “patterned” standard test wafers 20 is to alternate between aluminum wafers and blanket photoresist wafers in a plasma chamber. Such method, however, tends to be cumbersome and time consuming since the aluminum and blanket photoresist wafers must be alternated during use. Further, the aluminum wafers and blanket photoresist wafers are not processed at the same time. As such, the present method fails to effectively simulate the composition of materials being deposited in the plasma chamber during the processing of standard production wafers. This in turn gives rise to detrimental ramifications in particle performance.
  • test wafer that effectively simulates “patterned” standard test wafers and can be produced at a reduced cost.
  • the present invention includes a method and apparatus for simulating a standard wafer in semiconductor manufacturing equipment.
  • the present invention includes a support layer suitable for being handled by the semiconductor manufacturing equipment. Applied to the support layer is a mixture including a process agent and a material. During use, the present invention simulates a standard wafer including material similar to that in the mixture of the present invention.
  • the present invention offers a cost-effective substitution for standard test wafers. Moreover, the present invention better simulates standard test wafers by ensuring that byproducts are produced simultaneously.
  • the ratio of byproducts of the present invention may also be tailored to simulate a specific percentages of area that is exposed through the process agent on a standard test wafer. This is accomplished by varying a volumetric ratio between the process agent and material within the mixture.
  • FIG. 1 is a vastly exaggerated cross-sectional view of a standard production wafer of the prior art.
  • FIG. 2 is a vastly exaggerated cross-sectional view of a standard test wafer of the prior art.
  • Prior Art FIG. 3 is a top view of the standard test wafer of Prior Art FIG. 2 with a detailed view of the “patterned” photoresist.
  • FIG. 4 is a flowchart delineating the process for manufacturing an apparatus suitable for use in simulating a standard test wafer in semiconductor manufacturing equipment, according to one embodiment of the present invention.
  • FIG. 5 is a vastly exaggerated cross-sectional view of the apparatus of the present invention prior to etching.
  • FIG. 6 is a vastly exaggerated cross-sectional view of the apparatus of the present invention after etching.
  • Prior Art FIG. 1 shows a standard production wafer 10 .
  • Prior Art FIGS. 2 and 3 illustrate a standard test wafer 20 .
  • one embodiment of the present invention includes a method and apparatus that is suitable for simulating the standard test wafer 20 in semiconductor manufacturing equipment such as a plasma chamber.
  • the wafer 28 includes a support layer 30 and a combination 29 of a process agent 32 and at least one predetermined material 34 .
  • The. support layer 30 may be constructed from any type of material suitable for being handled by the semiconductor manufacturing equipment.
  • the material 34 may include, but is not limited to, silicon, an oxide, metal, plastic, any material commonly known in the semiconductor arts, or any other material capable of being handled by the semiconductor manufacturing equipment.
  • the support layer 30 may be shaped in the form of a substantially planar disc or wafer having a generally circular periphery.
  • the support layer 30 may take the form of a flat panel, an optical substrate, or any other type of support mechanism which is capable of supporting the mixture.
  • the process agent 32 and the material 34 may take the form of a mixture which is applied to the support layer 30 .
  • the process agent 32 may include a photoresist such as a deep-UV photoresist or any components thereof, a polymer, or a resin such as NovolacTM resin which is a component of a conventional I-line photoresist. It should be noted, however, that the process agent 32 may include any type of suitable substance which is associated with photolithography, etching or any other manufacturing process.
  • the same may include any substance for the purpose of simulating a standard test wafer 20 including the material 34 .
  • the mixture need not be limited to only a single material 34 .
  • Table 1 shows a list of examples of potential materials 34 and the wafer which each is designed to simulate. Such list is not to be deemed as exhaustive and may include any type of material(s).
  • the material 34 and the process agent 32 are combined to form the mixture.
  • the material is aluminum in a power form
  • such powder may comprise of particulates with a size in the order of 20 ⁇ m. It should be understood, however, that the particulates may have any microscopic or macroscopic size.
  • a volumetric ratio between the material 34 and the process agent 32 may be selected in order to simulate a percentage of an area that is exposed through the process agent 32 on a “patterned” standard test wafer 20 .
  • a 2:1 volumetric ratio between the material 34 and the process agent 32 may simulate an exposed area A on the simulated standard test wafer 20 while a 3:1 volumetric ratio between the material 34 and the process agent 32 may simulate an exposed area greater than A on the simulated standard test wafer 20 .
  • other types of ratios may be employed for partitioning the material 34 and the process agent 32 such as a mass ratio, density ratio, etc.
  • the mixture is applied to the support layer 30 , as indicated by box 38 of FIG. 4.
  • Application of the mixture may be carried out in various ways including, but not limited to spraying, spinning or brushing the mixture onto the support layer 30 .
  • any type of known technique may be employed to prevent the accumulation of the mixture adjacent the periphery of the support layer 30 .
  • the mixture is subsequently baked at a temperature and for a period of time sufficient to “cure” the process agent.
  • the mixture may be baked at 120°-130° F. for 10-15 minutes. It should be noted that the baking may be carried out with any effective means including a hot plate, oven or the like.
  • the present invention is then complete and ready to be used in place of a standard test wafer 20 in a plasma chamber or the like.
  • the present invention is placed within the semiconductor plasma chamber and is subsequently etched using conventional processes and techniques. During etching, the present invention produces byproducts and behaves in a manner similar to the “patterned” standard test wafer 20 that is to be simulated. As mentioned earlier, the process agent 32 on a “patterned” standard test wafer 20 is distributed upon a predetermined percentage of the surface area of the wafer. Accordingly, as the process agent 32 and wafer are etched, byproducts from the process agent 32 and the wafer are emitted simultaneously during the etching processes.
  • the present invention simulates the etching of a “patterned” standard test wafer 20 , but by a means that is vastly less expensive in comparison.
  • the present invention appears to offer a sizable reduction in cost with respect to conditioning plasma chambers and running related marathon experiments with “patterned” standard test wafers 20 .
  • marathon experiments are procedures wherein a vast number of wafers are placed in the plasma chamber and etched in a conventional manner for testing purposes.
  • the reduction in cost results from not only avoiding the use of expensive standard test wafers 20 , but also providing a test article that can be processed for a greater amount of time.
  • a standard test wafer 20 manufactured by SematechTM costs approximately $300.00 and can be etched for 1.3 RF minutes. This translates into a cost of $230.00/RF minute to use such standard test wafer 20 .
  • each unit costs $6.70 and can be etched for 120 RF minutes. This results in a cost of approximately $0.63/RF minute, less than 1% the cost associated with processing the standard test wafer 20 .

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

A method and apparatus are provided for simulating a standard wafer in semiconductor manufacturing equipment. The apparatus includes a support layer suitable for being handled by the semiconductor manufacturing equipment. Applied to the support layer is a mixture including a process agent and a material. During use, the present invention simulates a standard production wafer including material similar to that in the mixture of the present invention.

Description

    FIELD OF THE INVENTION
  • The present invention relates generally to semiconductor test wafers and, more particularly, to a test wafer that effectively simulates “patterned” standard test wafers and can be produced at a reduced cost. [0001]
    • BACKGROUND OF THE INVENTION
  • In semiconductor fabrication, the necessary related equipment must often be tested and conditioned prior to being used to manufacture integrated circuits. Such testing and conditioning improve the quality and reliability of the manufactured integrated circuits by providing a preview of how the semiconductor manufacturing equipment operates during various processes. For example, “marathon experiments” are often conducted wherein a vast number of wafers are placed in a plasma chamber and etched in a conventional manner. Analysis of various device parameters and the end product during such marathon experiments provides information that is beneficial during the preparation for actual production of integrated circuits. In particular, data regarding particle emissions may be collected during the course of the marathon experiments to anticipate particle failure during the manufacture of integrated circuits. [0002]
  • To carryout such conditioning exercises and marathon experiments on semiconductor manufacturing equipment such as plasma chambers, standard test wafers are normally used in place of standard production wafers. A cross-section of a standard production wafer [0003] 10 and a standard test wafer 20 are shown in FIGS. 1 and 2, respectively. As shown, the standard test wafer 20 includes a wafer 22 including any type of materials thereon such as aluminum and the like. This standard test wafer 20 further has a layer of photoresist 24 thereon. By this structure, the standard test wafer 20 simulates a pair of uppermost layers 26 of the standard production wafer 10.
  • In order to properly simulate a [0004] standard production wafer 10, it is preferred that the photoresist 24 of the standard test wafer 20 be “patterned.” In other words, the resist is ideally applied to the standard test wafer 20 to define a plurality of vias, channels, etc. which in turn leave a percentage of the standard test wafer 20 exposed as shown in FIG. 3.
  • Therefore, the use of [0005] standard test wafers 20 can be expensive, especially when standard test wafers 20 have multiple layers similar to standard production wafers 10. This cost often fails to justify many conditioning exercises and marathon experiments which, in turn, leads to reduced quality and reliability during the subsequent processing of standard production wafers 10.
  • One known prior art alternative to the use of such “patterned” [0006] standard test wafers 20 is to alternate between aluminum wafers and blanket photoresist wafers in a plasma chamber. Such method, however, tends to be cumbersome and time consuming since the aluminum and blanket photoresist wafers must be alternated during use. Further, the aluminum wafers and blanket photoresist wafers are not processed at the same time. As such, the present method fails to effectively simulate the composition of materials being deposited in the plasma chamber during the processing of standard production wafers. This in turn gives rise to detrimental ramifications in particle performance.
  • There is thus a need for a test wafer that effectively simulates “patterned” standard test wafers and can be produced at a reduced cost. [0007]
    • DISCLOSURE OF THE INVENTION
  • The present invention includes a method and apparatus for simulating a standard wafer in semiconductor manufacturing equipment. The present invention includes a support layer suitable for being handled by the semiconductor manufacturing equipment. Applied to the support layer is a mixture including a process agent and a material. During use, the present invention simulates a standard wafer including material similar to that in the mixture of the present invention. [0008]
  • By this design, the present invention offers a cost-effective substitution for standard test wafers. Moreover, the present invention better simulates standard test wafers by ensuring that byproducts are produced simultaneously. The ratio of byproducts of the present invention may also be tailored to simulate a specific percentages of area that is exposed through the process agent on a standard test wafer. This is accomplished by varying a volumetric ratio between the process agent and material within the mixture. [0009]
  • These and other advantages of the present invention will become apparent upon reading the following detailed description and studying the various figures of the drawings. [0010]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings, which are incorporated in and constitute part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the principles of the invention. [0011]
  • Prior Art FIG. 1 is a vastly exaggerated cross-sectional view of a standard production wafer of the prior art. [0012]
  • Prior Art FIG. 2 is a vastly exaggerated cross-sectional view of a standard test wafer of the prior art. [0013]
  • Prior Art FIG. 3 is a top view of the standard test wafer of Prior Art FIG. 2 with a detailed view of the “patterned” photoresist. [0014]
  • FIG. 4 is a flowchart delineating the process for manufacturing an apparatus suitable for use in simulating a standard test wafer in semiconductor manufacturing equipment, according to one embodiment of the present invention. [0015]
  • FIG. 5 is a vastly exaggerated cross-sectional view of the apparatus of the present invention prior to etching. [0016]
  • FIG. 6 is a vastly exaggerated cross-sectional view of the apparatus of the present invention after etching. [0017]
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Reference will now be made to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. [0018]
  • Prior Art FIG. 1 shows a [0019] standard production wafer 10. Prior Art FIGS. 2 and 3 illustrate a standard test wafer 20. As shown in FIGS. 4-6, one embodiment of the present invention includes a method and apparatus that is suitable for simulating the standard test wafer 20 in semiconductor manufacturing equipment such as a plasma chamber.
  • Turning to FIG. 5, a [0020] wafer 28 in accordance with one embodiment of the present invention will now be described. The wafer 28 includes a support layer 30 and a combination 29 of a process agent 32 and at least one predetermined material 34. The. support layer 30 may be constructed from any type of material suitable for being handled by the semiconductor manufacturing equipment. In various embodiments, the material 34 may include, but is not limited to, silicon, an oxide, metal, plastic, any material commonly known in the semiconductor arts, or any other material capable of being handled by the semiconductor manufacturing equipment. Further, in one embodiment, the support layer 30 may be shaped in the form of a substantially planar disc or wafer having a generally circular periphery. In the alternative, the support layer 30 may take the form of a flat panel, an optical substrate, or any other type of support mechanism which is capable of supporting the mixture.
  • The [0021] process agent 32 and the material 34 may take the form of a mixture which is applied to the support layer 30. Further, the process agent 32 may include a photoresist such as a deep-UV photoresist or any components thereof, a polymer, or a resin such as Novolac™ resin which is a component of a conventional I-line photoresist. It should be noted, however, that the process agent 32 may include any type of suitable substance which is associated with photolithography, etching or any other manufacturing process.
  • With respect to the [0022] material 34, the same may include any substance for the purpose of simulating a standard test wafer 20 including the material 34. Depending on the application at hand, the mixture need not be limited to only a single material 34. Table 1 shows a list of examples of potential materials 34 and the wafer which each is designed to simulate. Such list is not to be deemed as exhaustive and may include any type of material(s).
    TABLE 1
    Standard Wafer Type Appropriate Simulation Material
    Aluminum Aluminum (Al)
    Polysilicon Silicon (Si)
    Tungsten interconnect/etchback Tungsten (W)
    Tungsten Silicide Tungsten Silicide (WSi2)
    Titanium Titanium (Ti)
    Titanium Nitride Titanium Nitride (TiN)
    Silicon Dioxide Silicon Dioxide (SiO2)
    Platinum Platinum (Pt)
    Ruthenium Ruthenium (Ru)
    Ruthenium Oxide Ruthenium Oxide (RuO2)
    Copper Copper (Cu)
    Tantalum Tantalum (Ta)
    Nickel Nickel (Ni)
  • The method associated with the construction of the apparatus of the present invention will now be set forth with specific reference to FIG. 4. As mentioned earlier, the [0023] material 34 and the process agent 32 are combined to form the mixture. Note box 36 of FIG. 4. In the case where the material is aluminum in a power form, such powder may comprise of particulates with a size in the order of 20 μm. It should be understood, however, that the particulates may have any microscopic or macroscopic size.
  • As will soon become apparent, a volumetric ratio between the material [0024] 34 and the process agent 32 may be selected in order to simulate a percentage of an area that is exposed through the process agent 32 on a “patterned” standard test wafer 20. For example, a 2:1 volumetric ratio between the material 34 and the process agent 32 may simulate an exposed area A on the simulated standard test wafer 20 while a 3:1 volumetric ratio between the material 34 and the process agent 32 may simulate an exposed area greater than A on the simulated standard test wafer 20. In various alternate embodiments, other types of ratios may be employed for partitioning the material 34 and the process agent 32 such as a mass ratio, density ratio, etc.
  • Thereafter, the mixture is applied to the [0025] support layer 30, as indicated by box 38 of FIG. 4. Application of the mixture may be carried out in various ways including, but not limited to spraying, spinning or brushing the mixture onto the support layer 30. While applying the mixture to the support layer 30, any type of known technique may be employed to prevent the accumulation of the mixture adjacent the periphery of the support layer 30.
  • As indicated by [0026] box 40 of FIG. 4, the mixture is subsequently baked at a temperature and for a period of time sufficient to “cure” the process agent. In one embodiment, the mixture may be baked at 120°-130° F. for 10-15 minutes. It should be noted that the baking may be carried out with any effective means including a hot plate, oven or the like. After baking, the present invention is then complete and ready to be used in place of a standard test wafer 20 in a plasma chamber or the like.
  • In use, the present invention is placed within the semiconductor plasma chamber and is subsequently etched using conventional processes and techniques. During etching, the present invention produces byproducts and behaves in a manner similar to the “patterned” [0027] standard test wafer 20 that is to be simulated. As mentioned earlier, the process agent 32 on a “patterned” standard test wafer 20 is distributed upon a predetermined percentage of the surface area of the wafer. Accordingly, as the process agent 32 and wafer are etched, byproducts from the process agent 32 and the wafer are emitted simultaneously during the etching processes.
  • Similarly, during the etching of the present invention, the mixture of the [0028] material 34 and process agent 32 are exposed together as a combination, as shown in FIG. 6. As such, within the plasma chamber the present invention appears as being no different than a corresponding “patterned” standard test wafer 20. Therefore, the present invention simulates the etching of a “patterned” standard test wafer 20, but by a means that is vastly less expensive in comparison.
  • In terms of cost effectiveness, the present invention appears to offer a sizable reduction in cost with respect to conditioning plasma chambers and running related marathon experiments with “patterned” [0029] standard test wafers 20. As mentioned earlier, marathon experiments are procedures wherein a vast number of wafers are placed in the plasma chamber and etched in a conventional manner for testing purposes. The reduction in cost results from not only avoiding the use of expensive standard test wafers 20, but also providing a test article that can be processed for a greater amount of time.
  • For example, a [0030] standard test wafer 20 manufactured by Sematech™ costs approximately $300.00 and can be etched for 1.3 RF minutes. This translates into a cost of $230.00/RF minute to use such standard test wafer 20. In contrast, in one embodiment of the present invention wherein aluminum powder is employed with a 1:2 volumetric ratio to a process agent such as photoresist, each unit costs $6.70 and can be etched for 120 RF minutes. This results in a cost of approximately $0.63/RF minute, less than 1% the cost associated with processing the standard test wafer 20.
  • Although only a few embodiments of the present invention have been described in detail herein, it should be understood that the present invention may be embodied in many other specific forms without departing from the spirit or scope of the invention. Therefore, the present examples and embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope of the appended claims. [0031]

Claims (59)

What is claimed is:
1. An apparatus suitable for simulating a standard wafer in semiconductor manufacturing equipment, comprising:
a support layer suitable for being handled by the semiconductor manufacturing equipment; and
a mixture including a process agent and a material, the mixture being applied to the support layer,
wherein the apparatus simulates a wafer including the material and having the process agent thereon.
2. The apparatus of
claim 1
, wherein the process agent is photoresist.
3. The apparatus of
claim 1
, wherein the material is silicon and the apparatus simulates a wafer including polysilicon.
4. The apparatus of
claim 1
, wherein the material is tungsten and the apparatus simulates a wafer including tungsten.
5. The apparatus of
claim 1
, wherein the material is tungsten silicide and the apparatus simulates a wafer including tungsten silicide.
6. The apparatus of
claim 1
, wherein the material is titanium and the apparatus simulates a wafer including titanium.
7. The apparatus of
claim 1
, wherein the material is titanium nitride and the apparatus simulates a wafer including titanium nitride.
8. The apparatus of
claim 1
, wherein the material is silicon dioxide and the apparatus simulates a wafer including silicon dioxide.
9. The apparatus of
claim 1
, wherein the material is aluminum and the apparatus simulates a wafer including aluminum.
10. The apparatus of
claim 1
, wherein the material is platinum and the apparatus simulates a wafer including platinum.
11. The apparatus of
claim 1
, wherein the material is ruthenium and the apparatus simulates a wafer including ruthenium.
12. The apparatus of
claim 1
, wherein the material is ruthenium oxide and the apparatus simulates a wafer including ruthenium oxide.
13. The apparatus of
claim 1
, wherein the material is copper and the apparatus simulates a wafer including copper.
14. The apparatus of
claim 1
, wherein the material is tantalum and the apparatus simulates a wafer including tantalum.
15. The apparatus of
claim 1
, wherein the material is nickel and the apparatus simulates a wafer including nickel.
16. The apparatus of
claim 1
, wherein the support layer is at least one of a disc and a wafer.
17. The apparatus of
claim 1
, wherein the support layer includes at least one of silicon, metal, plastic, and an oxide.
18. The apparatus of
claim 1
, wherein the material and the process agent of the mixture are baked on the support layer.
19. The apparatus of
claim 1
, wherein a ratio between the material to the process agent corresponds to an exposed area on the wafer to be simulated.
20. A process for manufacturing an apparatus suitable for use in simulating a standard wafer in semiconductor manufacturing equipment, comprising:
combining a process agent and a material; and
applying the combination of the process agent and the material to a support layer to simulate a wafer including the material and having the process agent thereon.
21. The process of
claim 20
, wherein the process agent is a photoresist.
22. The process of
claim 20
, wherein the material is silicon dioxide to simulate a wafer including polysilicon.
23. The process of
claim 20
, wherein the material is tungsten to simulate a wafer including tungsten.
24. The process of
claim 20
, wherein the material is tungsten silicide to simulate a wafer including tungsten silicide.
25. The process of
claim 20
, wherein the material is titanium to simulate a wafer including titanium.
26. The process of
claim 20
, wherein the material is titanium nitride to simulate a wafer including titanium nitride.
27. The process of
claim 20
, wherein the material is silicon dioxide to simulate a wafer including silicon dioxide.
28. The process of
claim 20
, wherein the material is aluminum to simulate a wafer including aluminum.
29. The process of
claim 20
, wherein the material is platinum to simulate a wafer including platinum.
30. The process of
claim 20
, wherein the material is ruthenium to simulate a wafer including ruthenium.
31. The process of
claim 20
, wherein the material is ruthenium oxide to simulate a wafer including ruthenium oxide.
32. The process of
claim 20
, wherein the material is copper to simulate a wafer including copper.
33. The process of
claim 20
, wherein the material is tantalum to simulate a wafer including tantalum.
34. The process of
claim 20
, wherein the material is nickel to simulate a wafer including nickel.
35. The process of
claim 20
, wherein the support layer is at least one of a disc and a wafer.
36. The process of
claim 20
, wherein the support layer includes at least one of silicon, metal, plastic, and an oxide.
37. The process of
claim 20
, comprising:
baking the combination of the material and the process agent onto the support layer.
38. The process of
claim 20
, comprising:
selecting a ratio between the material and the process agent that corresponds to an exposed area on the wafer to be simulated.
39. The process of
claim 38
, comprising:
mixing the process agent and the material such that the combination is a mixture.
40. In a semiconductor plasma chamber, a method for simulating a standard wafer using an apparatus composed of a combination of a process agent and a material applied to a support layer, the method comprising:
placing the apparatus within the semiconductor plasma chamber;
etching the apparatus; and
simulating the standard wafer by simultaneously producing byproducts during the etching that are similar to byproducts produced by the standard wafer.
41. The method of
claim 40
, wherein the process agent is photoresist.
42. The method of
claim 40
, wherein the material is silicon dioxide to simulate a wafer including polysilicon.
43. The method of
claim 40
, wherein the material is tungsten to simulate a wafer including tungsten.
44. The method of
claim 40
, wherein the material is tungsten silicide to simulate a wafer including tungsten silicide.
45. The method of
claim 40
, wherein the material is titanium to simulate a wafer including titanium.
46. The method of
claim 40
, wherein the material is titanium nitride to simulate a wafer including titanium nitride.
47. The method of
claim 40
, wherein the material is silicon dioxide to simulate a wafer including silicon dioxide.
48. The method of
claim 40
, wherein the material is aluminum to simulate a wafer including aluminum.
49. The method of
claim 40
, wherein the material is platinum to simulate a wafer including platinum.
50. The method of
claim 40
, wherein the material is ruthenium to simulate a wafer including ruthenium.
51. The method of
claim 40
, wherein the material is ruthenium oxide to simulate a wafer including ruthenium oxide.
52. The method of
claim 40
, wherein the material is copper to simulate a wafer including copper.
53. The method of
claim 40
, wherein the material is tantalum to simulate a wafer including tantalum.
54. The method of
claim 40
, wherein the material is nickel to simulate a wafer including nickel.
55. The method of
claim 40
, wherein the support layer is at least one of a disc and a wafer.
56. The method of
claim 40
, wherein the support layer includes at least one of silicon, metal, plastic, and an oxide.
57. The method of
claim 40
, wherein the material and the process agent are baked on the support layer.
58. The method of
claim 40
, wherein a ratio between the material and the process agent corresponds to an exposed area on the wafer to be simulated.
59. An apparatus suitable for simulating a standard manufactured device in manufacturing equipment, comprising:
a support layer suitable for being handled by the manufacturing equipment; and
a mixture including a process agent and a material, the mixture being applied to the support layer,
wherein the apparatus simulates a manufactured device including the material and having the process agent thereon.
US09/923,725 1999-03-31 2001-08-06 Method and apparatus for simulating standard test wafers Abandoned US20010054600A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US09/923,725 US20010054600A1 (en) 1999-03-31 2001-08-06 Method and apparatus for simulating standard test wafers
US11/244,335 US7270760B2 (en) 1999-03-31 2005-10-04 Method and apparatus for simulating standard test wafers

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/282,585 US6296778B1 (en) 1999-03-31 1999-03-31 Method and apparatus for simulating standard test wafers
US09/923,725 US20010054600A1 (en) 1999-03-31 2001-08-06 Method and apparatus for simulating standard test wafers

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/282,585 Division US6296778B1 (en) 1999-03-31 1999-03-31 Method and apparatus for simulating standard test wafers

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/244,335 Division US7270760B2 (en) 1999-03-31 2005-10-04 Method and apparatus for simulating standard test wafers

Publications (1)

Publication Number Publication Date
US20010054600A1 true US20010054600A1 (en) 2001-12-27

Family

ID=23082161

Family Applications (3)

Application Number Title Priority Date Filing Date
US09/282,585 Expired - Lifetime US6296778B1 (en) 1999-03-31 1999-03-31 Method and apparatus for simulating standard test wafers
US09/923,725 Abandoned US20010054600A1 (en) 1999-03-31 2001-08-06 Method and apparatus for simulating standard test wafers
US11/244,335 Expired - Fee Related US7270760B2 (en) 1999-03-31 2005-10-04 Method and apparatus for simulating standard test wafers

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US09/282,585 Expired - Lifetime US6296778B1 (en) 1999-03-31 1999-03-31 Method and apparatus for simulating standard test wafers

Family Applications After (1)

Application Number Title Priority Date Filing Date
US11/244,335 Expired - Fee Related US7270760B2 (en) 1999-03-31 2005-10-04 Method and apparatus for simulating standard test wafers

Country Status (1)

Country Link
US (3) US6296778B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080259111A1 (en) * 2007-04-20 2008-10-23 Intermec Ip Corp. Method and apparatus for registering and maintaining registration of a medium in a content applicator

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4200463A (en) * 1975-12-19 1980-04-29 Motorola, Inc. Semiconductor device manufacture using photoresist protective coating
US4243696A (en) * 1979-01-22 1981-01-06 W. S. Rockwell Company Method of making a particle-containing plastic coating
US5521052A (en) * 1994-12-30 1996-05-28 Hoechst Celanese Corporation Metal ion reduction in novolak resin using an ion exchange catalyst in a polar solvent and photoresists compositions therefrom
US5719495A (en) * 1990-12-31 1998-02-17 Texas Instruments Incorporated Apparatus for semiconductor device fabrication diagnosis and prognosis
US5886909A (en) * 1997-12-19 1999-03-23 Advanced Micro Devices, Inc. Defect diagnosis using simulation for IC yield improvement
US6081659A (en) * 1997-05-08 2000-06-27 Lsi Logic Corporation Comparing aerial image to actual photoresist pattern for masking process characterization

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5711848A (en) * 1995-06-06 1998-01-27 Sony Corporation Non-product patterned particle test wafer and testing method therefor
US5866437A (en) * 1997-12-05 1999-02-02 Advanced Micro Devices, Inc. Dynamic process window control using simulated wet data from current and previous layer data
TW449854B (en) * 1998-08-29 2001-08-11 United Microelectronics Corp Inspection method for water mark on wafer

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4200463A (en) * 1975-12-19 1980-04-29 Motorola, Inc. Semiconductor device manufacture using photoresist protective coating
US4243696A (en) * 1979-01-22 1981-01-06 W. S. Rockwell Company Method of making a particle-containing plastic coating
US5719495A (en) * 1990-12-31 1998-02-17 Texas Instruments Incorporated Apparatus for semiconductor device fabrication diagnosis and prognosis
US5521052A (en) * 1994-12-30 1996-05-28 Hoechst Celanese Corporation Metal ion reduction in novolak resin using an ion exchange catalyst in a polar solvent and photoresists compositions therefrom
US6081659A (en) * 1997-05-08 2000-06-27 Lsi Logic Corporation Comparing aerial image to actual photoresist pattern for masking process characterization
US5886909A (en) * 1997-12-19 1999-03-23 Advanced Micro Devices, Inc. Defect diagnosis using simulation for IC yield improvement

Also Published As

Publication number Publication date
US6296778B1 (en) 2001-10-02
US7270760B2 (en) 2007-09-18
US20060032835A1 (en) 2006-02-16

Similar Documents

Publication Publication Date Title
DE102018215812A1 (en) High-density metal-insulator-metal capacitors
JPH01216278A (en) Testing of random defect for electronically microscopic structural body
DE19629249B4 (en) Method for analyzing defects of semiconductor devices with three dimensions
US7012031B2 (en) Photoresist pattern, method of fabricating the same, and method of assuring the quality thereof
US7767473B2 (en) Multiple die wafers having increased reliability and methods of increasing reliability in same
DE102019201202B4 (en) Method of improving heterodyne performance in semiconductor devices
US6296778B1 (en) Method and apparatus for simulating standard test wafers
DE10393364T5 (en) Hole microprobe using a MEMS technique and a method of making the same
US20060148241A1 (en) System for and method of forming via holes by use of selective plasma etching in a continuous inline shadow mask deposition process
US7907770B2 (en) Method for inspecting photomask and real-time online method for inspecting photomask
CN1882883B (en) System and method for characterizing lithography effects on a wafer
US7845868B1 (en) Apparatus for semiconductor manufacturing process
JP3732100B2 (en) Method for the manufacture and inspection of electronic circuit structures on semiconductor substrates
US7910289B2 (en) Use of dual mask processing of different composition such as inorganic/organic to enable a single poly etch using a two-print-two-etch approach
DE102009015718B4 (en) Test system and method for reducing damage in seed layers in metallization systems of semiconductor devices
JP4253860B2 (en) Exposure method and exposure apparatus
JPH0620903A (en) Method for manufacturing semiconductor device
CN101958279B (en) Method for improving width uniformity of grooves
DE102017208398A1 (en) DEVICES AND METHOD FOR MAKING A LOW-RAISE PRECAST METAL INTERCONNECTION WITH IMPROVED LIABILITY
DE102023118115B4 (en) Structure for capacitor with defect-preventing areas in metal electrode
JP3752151B2 (en) Method for removing development related defects in a photoresist mask
US20060247894A1 (en) Method and system for processing commonality of semiconductor devices
JP3473821B2 (en) Exposure amount setting method, exposure method, exposure apparatus, and device manufacturing method
US6809019B2 (en) Method for producing a semiconductor structure, and use of the method
DE112022006244T5 (en) METAL-INSULATOR-METAL (MIM) CAPACITOR MODULE WITH A CUP-SHAPED STRUCTURE WITH A ROUNDED CORNER AREA

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION